Fall 2006: Dec. 5 ELEC 5270-001/6270-001 Lecture 13 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power...

Fall 2006: Dec. 5Fall 2006: Dec. 5 ELEC 5270-001/6270-001 Lecture 13ELEC 5270-001/6270-001 Lecture 13 11

ELEC 5270-001/6270-001(Fall ELEC 5270-001/6270-001(Fall 2006)2006)

Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits

Adiabatic LogicAdiabatic Logic

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering

Auburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal

[email protected]@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal

mailto:[email protected]


Examples of Power Saving and Examples of Power Saving and Energy RecoveryEnergy Recovery

Power saving by power transmission at high Power saving by power transmission at high voltage:voltage: 1000W transmitted at 100V, current I = 10A1000W transmitted at 100V, current I = 10A If resistance of transmission circuit is 1If resistance of transmission circuit is 1ΩΩ, then , then

power loss = Ipower loss = I22R = 100WR = 100W Transmit at 1000V, current I = 1A, transmission Transmit at 1000V, current I = 1A, transmission

loss = 1Wloss = 1W Energy recovery from automobile brakes:Energy recovery from automobile brakes:

Normal brake converts mechanical energy into Normal brake converts mechanical energy into heatheat

Instead, the energy can be stored in a flywheel, orInstead, the energy can be stored in a flywheel, or Converted to electricity to charge a batteryConverted to electricity to charge a battery


Reexamine CMOS GateReexamine CMOS Gate

i = Ve-t/RpC/Rp

i2Rp

VV2/Rp

C

Time, t

Po

we

r

Most energy dissipated here

VI = V2e-2t/RpC/Rp

0

Energy dissipation = Area/2 = CV2/2

v(t)

V v(t)

v(t

)

3RpC


Charging with Constant Charging with Constant CurrentCurrent

i = K i2Rp

V(t)

C

Po

we

r0

v(t) = Kt/C

Time (T) to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/KCurrent, i = K = CV/T

Ou

tpu

t vo

ltag

e, v

(t)

0

V

Time, t t=CV/K

Kt/C

Power = i2Rp = C2V2Rp/T2

Energy dissipation = Power × T = (RpC/T) CV2

C2V2Rp/T2


Or, Charge in StepsOr, Charge in Steps

i = Ve-t/RpC/2Rp

i2Rp

0→V/2→V

V2/4Rp

C

Time, t

Po

we

r

V2e-2t/RpC/4Rp

0Energy = Area = CV2/8

v(t)

V v(t)

v(t

)

V/2

Total energy = CV2/8 + CV2/8 = CV2/4

3RpC 6RpC


Energy Dissipation of a StepEnergy Dissipation of a Step

TE = ∫ V2e-2t/RpC/(N2Rp) dt 0

= [CV2/(2N2)] (1 – e-2T/RpC)

≈ CV2/(2N2) for large T ≥ 3RpC

Voltage step = V/N


Charge in N StepsCharge in N Steps

Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N

Current, i(t) = Ve-t/RpC/NRp

Power, i2(t)Rp = V2e-2t/RpC/N2Rp

Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞

Delay = N × 3RpC → ∞ for N → ∞


ReferencesReferences

C. L. Seitz, A. H. Frey, S. Mattisson, S. D. C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Proc. Chapel Hill Conf. VLSIHill Conf. VLSI, 1985, pp. 1-17., 1985, pp. 1-17.

W. C. Athas, L. J. Swensson, J. D. Koller, N. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Digital Systems Based on Adiabatic-Switching Principles,” Switching Principles,” IEEE Trans. VLSI IEEE Trans. VLSI SystemsSystems, vol. 2, no. 4, pp. 398-407, Dec. , vol. 2, no. 4, pp. 398-407, Dec. 1994.1994.


A Conventional Dynamic CMOS A Conventional Dynamic CMOS InverterInverter

V

C

v(t)

CK

vin

CK

vin

v(t)

P E P E P E


Adiabatic Dynamic CMOS Adiabatic Dynamic CMOS InverterInverter

C

v(t)

CK

vin

A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.

CK

vin

v(t)

V

0

V-Vf

0

Vf+

P E P E P E P E


Cascaded Adiabatic Cascaded Adiabatic InvertersInverters

CK1 CK2 CK1’ CK2’

vin

CK1

CK2

CK1’

CK2’

precharge

input

evaluatehold


Complex ADL GateComplex ADL Gate

CK

B

A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.

AC

AB + C

Vf < Vth


Quasi-Adiabatic LogicQuasi-Adiabatic Logic Two sets of Two sets of

diodes: One diodes: One controls the controls the charging path charging path (D1) while the (D1) while the other (D2) other (D2) controls the controls the discharging pathdischarging path

Supply lines have Supply lines have EVALUATEEVALUATE phase phase (( swings up) and swings up) and HOLDHOLD phase ( phase ( swings low)swings low)

D1


ClocksClocksEVAL. HOLD EVAL. HOLD

0

0

VDD

VDD


Possible Cases:• The circuit output node X is LOW

and the pMOS tree is turned ON: X

follows as it swings to HIGH (EVALUATE phase)

• The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase)

• The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase)

• The circuit node X is HIGH and the

nMOS tree is ON. X follows down to LOW.

Quasi-Adiabatic Logic Quasi-Adiabatic Logic DesignDesign


A Case StudyA Case Study

K. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.


Quasi-Adiabatic 32-bit ARM Based Quasi-Adiabatic 32-bit ARM Based Microprocessor Design Microprocessor Design

SpecificationsSpecifications Operating voltage: 2.5 VOperating voltage: 2.5 V Operating temperature: 25Operating temperature: 25ooCC Operating frequency: 10 MHz to 100 Operating frequency: 10 MHz to 100

MHzMHz Leakage current: 0.5 Leakage current: 0.5 fAmpsfAmps Load capacitance: 6X10Load capacitance: 6X10-18 -18 FF (15% (15%

activity)activity) Transistor Count:Transistor Count:


Technology DistributionTechnology Distribution Microprocessor has a mix of static Microprocessor has a mix of static

CMOS and Quasi-adiabatic componentsCMOS and Quasi-adiabatic components

ALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit

ALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit

Control UnitsControl Units• ARM controller unit• Bus control unit

Pipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unit

Control UnitsControl Units• ARM controller unit• Bus control unit

Pipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unit

Quasi-Adiabatic Static CMOS


Power AnalysisPower AnalysisDatapathDatapath

ComponentComponent

Power Consumption Power Consumption (mW)(mW)

Frequency 25 MHzFrequency 25 MHz

Power Consumption (mW)Power Consumption (mW)


Quasi-Quasi-adiabatiadiabati

cc

Static Static CMOSCMOS

Power Power SavedSaved


cc



32-bit Adder 32-bit Adder SubtracterSubtracter

1.011.01 1.551.55 44%44% 1.291.29 1.621.62 20%20%

32-bit Barrel 32-bit Barrel ShifterShifter

0.90.9 1.6811.681 46%46% 1.3681.368 1.81.8 24%24%

32-bit Booth 32-bit Booth MultiplierMultiplier

3.43.4 5.85.8 40%40% 5.155.15 6.26.2 17%17%Power Consumption Power Consumption

(mW)(mW)



cc



60 60 mWmW 85 85 mWmW 40%40%


Power Analysis (Cont’d.)Power Analysis (Cont’d.)


Area AnalysisArea AnalysisDatapathDatapath

ComponentComponent

Area (mmArea (mm22))

Quasi-Quasi-adiabaticadiabatic

Static CMOSStatic CMOS Area Area IncreaseIncrease

32-bit Adder 32-bit Adder SubtracterSubtracter

0.050.05 0.030.03 66%66%

32-bit Barrel Shifter32-bit Barrel Shifter 0.250.25 0.110.11 120%120%

32-bit Booth Multiplier32-bit Booth Multiplier 1.21.2 0.50.5 140%140%

Chip Area (mmChip Area (mm22))


cc


Area Area IncreaseIncrease

1.551.55 1.011.01 44%44%


SummarySummary In principle, two types of adiabatic logic In principle, two types of adiabatic logic

designs have been proposed:designs have been proposed: Fully-adiabaticFully-adiabatic

Adiabatic chargingAdiabatic charging Charge recovery: charge from a discharging Charge recovery: charge from a discharging

capacitor is used to charge the capacitance from the capacitor is used to charge the capacitance from the next stage.next stage.

W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” on Adiabatic-Switching Principles,” IEEE Trans. VLSI IEEE Trans. VLSI SystemsSystems, vol. 2, no. 4, pp. 398-407, Dec. 1994., vol. 2, no. 4, pp. 398-407, Dec. 1994.

Quasi-adiabaticQuasi-adiabatic Adiabatic charging and dischargingAdiabatic charging and discharging Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Y. Ye and K. Roy, “QSERL: Quasi-Static Energy

Recovery Logic,” Recovery Logic,” IEEE J. Solid-State CircuitsIEEE J. Solid-State Circuits, vol. 36, , vol. 36, pp. 239-248, Feb. 2001.pp. 239-248, Feb. 2001.

Fall 2006: Dec. 5 ELEC 5270-001/6270-001 Lecture 13 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power...

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Transcript of Fall 2006: Dec. 5 ELEC 5270-001/6270-001 Lecture 13 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power...