ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Adiabatic Logic

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 09, Lecture 13ELEC6270 Spring 09, Lecture 13 11

ELEC 5270/6270 Spring 2009ELEC 5270/6270 Spring 2009Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits

Adiabatic LogicAdiabatic Logic

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html


Examples of Power Saving and Examples of Power Saving and Energy RecoveryEnergy Recovery

Power saving by power transmission at high Power saving by power transmission at high voltage:voltage: 1000W transmitted at 100V, current I = 10A1000W transmitted at 100V, current I = 10A If resistance of transmission circuit is 1If resistance of transmission circuit is 1ΩΩ, then power loss , then power loss

= I= I22R = 100WR = 100W Transmit at 1000V, current I = 1A, transmission loss = Transmit at 1000V, current I = 1A, transmission loss =

1W1W Energy recovery from automobile braking:Energy recovery from automobile braking:

Normal brake converts mechanical energy into heatNormal brake converts mechanical energy into heat Instead, the energy can be stored in a flywheel, orInstead, the energy can be stored in a flywheel, or Converted to electricity to charge a batteryConverted to electricity to charge a battery


Reexamine CMOS GateReexamine CMOS Gate

i = Ve–t/RpC/Rp

i2Rp

VV2/ Rp

C

Time, t

Po

we

r

Most energy dissipated here

V×i = V2e–2t/RpC/ Rp

0

Energy dissipation per transition = Area/2 = C V 2/ 2

v(t)

V v(t)

v(t

)

3RpC


Charging with Constant CurrentCharging with Constant Current

i = K i2Rp

V(t)

C

Po

we

r0

v(t) = Kt/C

Time (T) to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/KCurrent, i = K = CV/T

Ou

tpu

t vo

ltag

e, v

(t)

0

V

Time, t T=CV/K

Kt/C

Power = i2Rp = C2V2Rp/T2

Energy dissipation = Power × T = (RpC/T) CV2

C2V2Rp/T2


Or, Charge in StepsOr, Charge in Steps

i = Ve–t/RpC/2Rp

i2Rp

0→V/2→V

V2/4Rp

C

Time, t

Po

we

r

V2e–2t/RpC/4Rp

0Energy = Area = CV2/8

v(t)

V v(t)

v(t

)

V/2

Total energy = CV2/8 + CV2/8 = CV2/4

3RpC 6RpC


Energy Dissipation of a StepEnergy Dissipation of a Step

TE = ∫ V2e–2t/RpC/(N2Rp) dt 0

= [CV2/(2N2)] (1 – e–2T/RpC)

≈ CV2/(2N2) for large T ≥ 3RpC

Voltage step = V/N


Charge in N StepsCharge in N Steps

Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N

Current, i(t) = Ve–t/RpC/NRp

Power, i2(t)Rp = V2e–2t/RpC/N2Rp

Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞

Delay = N × 3RpC → ∞ for N → ∞


Reexamine Charging of a CapacitorReexamine Charging of a Capacitor

V C

R

i(t) v(t)

Charge on capacitor, q(t) = C v(t)

Current, i(t) = dq(t)/dt = C dv(t)/dt

t = 0


i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC

dv(t) dt∫ ───── = ∫ ──── V – v(t) RC

– t ln [V – v(t)] = ── + A

RC

Initial condition, t = 0, v(t) = 0 → A = ln V – t

v(t) = V [1 – exp(───)]

RC


– t v(t) = V [1 – exp( ── )]

RC

dv(t) V – ti(t) = C ─── = ── exp( ── )

dt R RC


Total Energy Per Charging Total Energy Per Charging Transition from Power SupplyTransition from Power Supply

∞ ∞ V 2 – tEtrans = ∫ V i(t) dt = ∫ ── exp( ── ) dt

0 0 R RC

= CV2


Energy Dissipated per Transition in Energy Dissipated per Transition in ResistanceResistance

∞ V 2 ∞ –2tR ∫ i 2(t) dt= R ── ∫ exp( ── ) dt 0 R2 0 RC

1= ─ CV 2

2


Energy Stored in Charged Energy Stored in Charged Capacitor Capacitor

∞ ∞ – t V – t∫ v(t) i(t) dt = ∫ V [1– exp( ── )] ─ exp( ── ) dt0 0 RC R RC

1 = ─ CV 2

2


Slow Charging of a CapacitorSlow Charging of a Capacitor

V(t) C

R

i(t) v(t)

Charge on capacitor, q(t) = C v(t)

Current, i(t) = dq(t)/dt = C dv(t)/dt

t = 0


i(t) = C dv(t)/dt = [V(t) – v(t)] /R

dv(t) V(t) – v(t) ─── = ───── dt RC

dv(t) dt∫ ────── = ∫ ──── V(t) – v(t) RC


Effects of Slow ChargingEffects of Slow Charging

V(t) v(t)

t

Voltage across R

Vo

ltage


ReferencesReferences

C. L. Seitz, A. H. Frey, S. Mattisson, S. D. C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Proc. Chapel Hill Conf. VLSIHill Conf. VLSI, 1985, pp. 1-17., 1985, pp. 1-17.

W. C. Athas, L. J. Swensson, J. D. Koller, N. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Digital Systems Based on Adiabatic-Switching Principles,” Principles,” IEEE Trans. VLSI SystemsIEEE Trans. VLSI Systems, vol. 2, , vol. 2, no. 4, pp. 398-407, Dec. 1994.no. 4, pp. 398-407, Dec. 1994.


A Conventional Dynamic CMOS A Conventional Dynamic CMOS InverterInverter

V

C

v(t)

CK

vin

CK

vin

v(t)

P E P E P E


Adiabatic Dynamic CMOS InverterAdiabatic Dynamic CMOS Inverter

C

v(t)

CK

vin

A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.

CK

vin

v(t)

V

0

V-Vf

0

Vf+

P E P E P E P E


Cascaded Adiabatic InvertersCascaded Adiabatic Inverters

CK1 CK2 CK1’ CK2’

vin

CK1

CK2

CK1’

CK2’

precharge

input

evaluatehold


Complex ADL GateComplex ADL Gate

CK

B

A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.

AC

AB + C

Vf < Vth


Quasi-Adiabatic LogicQuasi-Adiabatic LogicTwo sets of diodes: Two sets of diodes:

One controls the One controls the charging path (D1) charging path (D1) while the other (D2) while the other (D2) controls the controls the discharging pathdischarging path

Supply lines have Supply lines have EVALUATEEVALUATE phase phase (( swings up) and swings up) and HOLDHOLD phase ( phase ( swings up)swings up)

D1

Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State CircuitsIEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001., vol. 36, pp. 239-248, Feb. 2001.


ClocksClocks

EVAL. HOLD EVAL. HOLD

0

0

VDD

VDD


Possible Cases:• The circuit output node X is LOW

and the pMOS tree is turned ON: X

follows as it swings to HIGH (EVALUATE phase)

• The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase)

• The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase)

• The circuit node X is HIGH and the

nMOS tree is ON. X follows down to LOW.

Quasi-Adiabatic Logic DesignQuasi-Adiabatic Logic Design


A Case StudyA Case Study

K. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.


Quasi-Adiabatic 32-bit ARM Based Quasi-Adiabatic 32-bit ARM Based Microprocessor Design SpecificationsMicroprocessor Design Specifications

Operating voltage: 2.5 VOperating voltage: 2.5 V Operating temperature: 25Operating temperature: 25ooCC Operating frequency: 10 MHz to 100 MHzOperating frequency: 10 MHz to 100 MHz Leakage current: 0.5 Leakage current: 0.5 fAmpsfAmps Load capacitance: 6X10Load capacitance: 6X10-18 -18 FF (15% activity) (15% activity) Transistor Count:Transistor Count:


Technology DistributionTechnology Distribution Microprocessor has a mix of static CMOS Microprocessor has a mix of static CMOS

and Quasi-adiabatic componentsand Quasi-adiabatic components

ALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit

Control UnitsControl Units• ARM controller unit• Bus control unit

Pipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unit

Quasi-Adiabatic Static CMOS


Power AnalysisPower Analysis

DatapathDatapath

ComponentComponent

Power Consumption (mW)Power Consumption (mW)

Frequency 25 MHzFrequency 25 MHz



Quasi-Quasi-adiabaticadiabatic

Static Static CMOSCMOS

Power Power SavedSaved




32-bit Adder 32-bit Adder SubtracterSubtracter

1.011.01 1.551.55 44%44% 1.291.29 1.621.62 20%20%

32-bit Barrel 32-bit Barrel ShifterShifter

0.90.9 1.6811.681 46%46% 1.3681.368 1.81.8 24%24%

32-bit Booth 32-bit Booth MultiplierMultiplier

3.43.4 5.85.8 40%40% 5.155.15 6.26.2 17%17%






60 60 mWmW 85 85 mWmW 40%40%


Power Analysis (Cont’d.)Power Analysis (Cont’d.)


Area AnalysisArea AnalysisDatapathDatapath

ComponentComponent

Area (mmArea (mm22))


Static CMOSStatic CMOS Area Area IncreaseIncrease

32-bit Adder Subtracter32-bit Adder Subtracter 0.050.05 0.030.03 66%66%

32-bit Barrel Shifter32-bit Barrel Shifter 0.250.25 0.110.11 120%120%

32-bit Booth Multiplier32-bit Booth Multiplier 1.21.2 0.50.5 140%140%

Chip Area (mmChip Area (mm22))



Area Area IncreaseIncrease

1.551.55 1.011.01 44%44%


SummarySummary In principle, two types of adiabatic logic designs In principle, two types of adiabatic logic designs

have been proposed:have been proposed: Fully-adiabaticFully-adiabatic

Adiabatic chargingAdiabatic charging Charge recovery: charge from a discharging capacitor is Charge recovery: charge from a discharging capacitor is

used to charge the capacitance from the next stage.used to charge the capacitance from the next stage. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and

E. Y.-C. Chou, “Low-Power Digital Systems Based on E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” Adiabatic-Switching Principles,” IEEE Trans. VLSI SystemsIEEE Trans. VLSI Systems, , vol. 2, no. 4, pp. 398-407, Dec. 1994.vol. 2, no. 4, pp. 398-407, Dec. 1994.

Quasi-adiabaticQuasi-adiabatic Adiabatic charging and dischargingAdiabatic charging and discharging Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery

Logic,” Logic,” IEEE J. Solid-State CircuitsIEEE J. Solid-State Circuits, vol. 36, pp. 239-248, , vol. 36, pp. 239-248, Feb. 2001.Feb. 2001.

ELEC 5270/6270 Spring 2009 Low-Power Design of Electronic Circuits Adiabatic Logic

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