Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 9 1 ELEC 5270/6270 Fall 2007 Low-Power Design of...

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 9ELEC6270 Fall 07, Lecture 9 11

ELEC 5270/6270 Fall 2007ELEC 5270/6270 Fall 2007Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits

Test PowerTest Power

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html


Power Considerations in DesignPower Considerations in Design A circuit is designed for certain function. Its design A circuit is designed for certain function. Its design

must allow the power consumption necessary to must allow the power consumption necessary to execute that function.execute that function.

Power buses are laid out to carry the maximum Power buses are laid out to carry the maximum current necessary for the function.current necessary for the function.

Heat dissipation of package conforms to the average Heat dissipation of package conforms to the average power consumption during the intended function.power consumption during the intended function.

Layout design and verification must account for “hot Layout design and verification must account for “hot spots” and “voltage droop” – delay, coupling noise, spots” and “voltage droop” – delay, coupling noise, weak signals.weak signals.


Testing Differs from Functional Testing Differs from Functional OperationOperation

VLSI chip

system

Systeminputs

Systemoutputs

Functional inputs Functional outputs

Other chips


Basic Mode of TestingBasic Mode of Testing

VLSI chipTest vectors:

Pre-generated and stored in

ATE

DUT output for comparison with expected response stored in ATE

Automatic Test Equipment (ATE):Control processor, vector memory,timing generators, power module,

response comparator

PowerClock

Packaged or unpackaged device under test (DUT)


Functional Inputs vs. Test VectorsFunctional Inputs vs. Test Vectors

Functional inputs:Functional inputs: Functionally meaningful Functionally meaningful

signalssignals Generated by circuitryGenerated by circuitry

Restricted set of inputsRestricted set of inputs

May have been May have been optimized to reduce optimized to reduce logic activity and powerlogic activity and power

Test vectors:Test vectors: Functionally irrelevant Functionally irrelevant

signalssignals Generated by software Generated by software

to test modeled faultsto test modeled faults Can be random or Can be random or

pseudorandompseudorandom May be optimized to May be optimized to

reduce test time; can reduce test time; can have high logic activityhave high logic activity

May use testability logic May use testability logic for test applicationfor test application


An ExampleAn Example

VLSI chipBinary to decimal

converter

3-bit random vectors

8-bit1-hot

vectors

VLSI chip

system

VLSI chip in system operation

VLSI chip under test

High activity8-bit

test vectors from ATE


Comb. Circuit Power OptimizationComb. Circuit Power Optimization

Given a set of test vectorsGiven a set of test vectorsReorder vectors to minimize the number of Reorder vectors to minimize the number of

transitions at primary inputstransitions at primary inputs

Combinational circuit(tested by exhaustive

vectors)

010101010011001100001111

01111000Rearranged vector set 00110011 produces 7 transitions

00011110

11 transitions


Reducing Comb. Test Power Reducing Comb. Test Power

1 1 0 0 01 0 1 0 01 0 1 0 11 0 1 1 1

V1 V2 V3

V4 V5

3 4

1

3 223

2

1

1

Original tests:V1 V2 V3 V4 V5

10 input transitions

Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once.But, we need an open loop solution.

Reordered tests:V1 V3 V5 V4 V21 0 0 0 11 1 0 0 01 1 1 0 01 1 1 1 0

5 input transitions


Open-Loop TSP Open-Loop TSP

Add a node V0 at distance 0 from all other nodes.Add a node V0 at distance 0 from all other nodes. Solve TSP for the new graph.Solve TSP for the new graph. Delete V0 from the solution.Delete V0 from the solution.

V1 V2 V3

V4 V5

3 4

1

32

23

2

1

1V0

0

0 0 0

0


Traveling Salesperson ProblemTraveling Salesperson Problem A. V. Aho, J. E. Hopcroft anf J. D. Ullman, A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data Data

Structures and AlgorithmsStructures and Algorithms, Reading, , Reading, Massachusetts: Addison-Wesley, 1983.Massachusetts: Addison-Wesley, 1983.

E. Horowitz and S. Sahni, E. Horowitz and S. Sahni, Fundamentals of Fundamentals of Computer AlgorithmsComputer Algorithms, Computer Science Press, , Computer Science Press, 1984.1984.

B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, R. Coombes, J. E. Osborn and G. J. Stuck, A A Guide to MATLAB for Beginners and Guide to MATLAB for Beginners and Experienced UsersExperienced Users, Cambridge University , Cambridge University Press, 2006.Press, 2006.


Scan TestingScan Testing

Combinational logic

Scan flip- flops

Primary inputs

Primary outputs

Scan-inSI

Scan-outSO

Scan enableSE DFF

mu

x

SE

SI

D

D

D’

D’

SO1

0


Example: State MachineExample: State Machine

S5

S1

S4

S2

S3

Reduced power state encodingS1 = 000S2 = 011S3 = 001S4 = 010S5 = 100

State transitionState transition Comb. State input Comb. State input changes/clockchanges/clock

000 → 001000 → 001 11

000 → 100000 → 100 11

011 → 010011 → 010 11

001 → 011001 → 011 11

010 → 000010 → 000 11

100 → 010100 → 010 22

Functional transitionsFunctional state transitions


Scan Testing of State MachineScan Testing of State Machine

Combinational logic

FF=0

FF=0

FF=1

Primary inputs

Primary outputs

Scan-in010

Scan-out100

State State transitiontransition

Per clock Per clock state state

changeschanges

100 → 010100 → 010 22

010 → 101010 → 101 33

101 → 010101 → 010 33

Scan transitions


Low Power Scan Flip-FlopLow Power Scan Flip-Flop

DFF

mu

x

SE

SI

DDFFm

ux

SE

SI

DSO

D’ D’

SO

Scan FF cell Low power scan FF cell

1

0


Built-In Self-Test (BIST)Built-In Self-Test (BIST)

Linear feedback shift register (LFSR)

Multiple input signature register (MISR)

Circuit under test (CUT)

Pseudo-random patterns

Circuit responses

BISTController

Clock

C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Springer,2002.


Test Scheduling ExampleTest Scheduling Example

R1 R2

M1 M2

R3 R4

A datapath


BIST Configuration 1: Test TimeBIST Configuration 1: Test Time

LFSR1 LFSR2

M1 M2

MISR1 MISR2

Test time

Te

st p

ow

er

T1: test for M1

T2: test for M2


BIST Configuration 2: Test PowerBIST Configuration 2: Test Power

R1 LFSR2

M1 M2

MISR1 MISR2Test time

Te

st p

ow

er

T1: test for M1T2: test for M2


Testing of MCM and SOCTesting of MCM and SOC

Test resources: Typically registers and Test resources: Typically registers and multiplexers that can be reconfigured as test multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR).response analyzers (e.g., MISR).

Test resources (R1, . . .) and tests (T1, . . .) Test resources (R1, . . .) and tests (T1, . . .) are identified for the system to be tested.are identified for the system to be tested.

Each test is characterized for test time, Each test is characterized for test time, power dissipation and resources it requires.power dissipation and resources it requires.


Resource Allocation GraphResource Allocation Graph

T1 T2 T3 T4 T5 T6

R2R1 R3 R4 R5 R6 R7 R8 R9


Test Compatibility Graph (TCG)Test Compatibility Graph (TCG)T1

(2, 100)

T2(1,10)

T3(1, 10)

T4(1, 5)

T5(2, 10)

T6(1, 100)

Tests that form a clique can be performed concurrently.

Power Test time

Pmax = 4


Test Scheduling AlgorithmTest Scheduling Algorithm

Identify all possible cliques in TCG:Identify all possible cliques in TCG:C1 = {T1, T3, T5}C1 = {T1, T3, T5}C2 = {T1, T3, T4}C2 = {T1, T3, T4}C3 = {T1, T6}C3 = {T1, T6}C4 = {T2, T5}C4 = {T2, T5}C5 = {T2, T6}C5 = {T2, T6}

Break up clique sets into power compatible Break up clique sets into power compatible sets (PCS), that satisfy the power sets (PCS), that satisfy the power constraint.constraint.


Test Scheduling Algorithm . . .Test Scheduling Algorithm . . . PCS (Pmax = 4), tests within a set are ordered for PCS (Pmax = 4), tests within a set are ordered for

decreasing test length:decreasing test length: C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5)C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5) C2 = {T1, T3, T4} → (T1, T3, T4)C2 = {T1, T3, T4} → (T1, T3, T4) C3 = {T1, T6} → (T1, T6)C3 = {T1, T6} → (T1, T6) C4 = {T2, T5} → (T2, T5)C4 = {T2, T5} → (T2, T5) C5 = {T2, T6} → (T2, T6)C5 = {T2, T6} → (T2, T6)

Greedy solution:Greedy solution: Expand PCS into subsets of decreasing test lengths. Each subset is Expand PCS into subsets of decreasing test lengths. Each subset is

an independent test session, consisting of tests that can be an independent test session, consisting of tests that can be concurrently applied.concurrently applied.

Select test sessions, starting from the shortest-time PCS, to cover all Select test sessions, starting from the shortest-time PCS, to cover all tests.tests.

Remove redundant PCS from the selected sessions.Remove redundant PCS from the selected sessions.


TS Algorithm: Cover TableTS Algorithm: Cover TableTest session T1 T2 T3 T4 T5 T6 Length

(T1, T3, T4) X X X 100

(T1, T5) X X 100

(T1, T6) X X 100

(T2, T6)* X X 100

(T3, T5) X X 10

(T2, T5) X X 10

(T3, T4) X X 10

(T5)* X 10

(T4)* X 5

•Dropped as redundant sessions.•Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.


An ILP Solution to Cover ProblemAn ILP Solution to Cover ProblemTest session Integer 0,1 variable T1 T2 T3 T4 T5 T6 Length

(T1, T3, T4) S1 X X X 100

(T1, T5) S2 X X 100

(T1, T6) S3 X X 100

(T2, T6) S4 X X 100

(T3, T5) S5 X X 10

(T2, T5) S6 X X 10

(T3, T4) S7 X X 10

(T5) S8 X 10

(T4) S9 X 5

Constraints: S1+S2+S3 ≥ 1 implies T1 is coveredS4+S6 ≥ 1 implies T2 is coveredsimilar constraints to cover T3, T4, T5 and T6


An ILP Solution (Cont.)An ILP Solution (Cont.)Test session Si: Integer 0,1 variable T1 T2 T3 T4 T5 T6 Length, Li

(T1, T3, T4) S1 X X X 100

(T1, T5) S2 X X 100

(T1, T6) S3 X X 100

(T2, T6) S4 X X 100

(T3, T5) S5 X X 10

(T2, T5) S6 X X 10

(T3, T4) S7 X X 10

(T5) S8 X 10

(T4) S9 X 5

9Minimize ∑ (Li × Si) ILP solution: S3=S6=S7 = 1

i=1 S1=S2=S4=S5=S8=S9 = 0Test length = 120


A System Example: ASIC Z*A System Example: ASIC Z*

RAM 2Time=61

Power=241

RAM 3Time=38

Power=213

ROM 1Time=102

Power=279

ROM 2Time=102

Power=279

RAM 1Time=69

Power=282

RAM 4Time=23

Power=96

Reg. fileTime = 10Power=95

Random logic 1, time=134, power=295

Random logic 2, time=160, power=352

*Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,” Proc. VLSI Test Symp., April 1993, pp. 4-9.


Test Scheduling for ASIC ZTest Scheduling for ASIC Z1200

900

600

300

Po

we

r

Power limit = 900

0 100 200 300 400Test time 331

RAM 1

RAM 3

Random logic 2

Random logic 1

ROM 2

ROM 1

RAM 2

Reg. file

RAM 4

R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175-185, June 1997.


ReferencesReferences

N. Nicolici and B. M. Al-Hashimi, N. Nicolici and B. M. Al-Hashimi, Power-Power-Constrained Testing of VLSI CircuitsConstrained Testing of VLSI Circuits, , Boston: Springer, 2003.Boston: Springer, 2003.

E. Larsson, E. Larsson, Introduction to Advanced Introduction to Advanced System-on-Chip Test Design and System-on-Chip Test Design and OptimizationOptimization, Springer 2005., Springer 2005.

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