6 CMOS Fabrication

8/13/2019 6 CMOS Fabrication

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IC FabricationIC is fabricated on a single piece of a silicon wafer

The wafer surface is subjected to various processingsteps in which impurities and other materials are addedwith specific geometrical patternsThe fabrication steps are sequenced to form 3D regionsthat act as transistors and interconnects



Silicon WaferWafer is the basic building block for IC fabrication

Is made from an ingotIngot :-Cylindrical, single-crystal semiconductorBy Czochralski crystal growth process

A wafer is measured by its diameter :-4 inches, 6 inches, 8 inches, 12 inches

Wafers cut from ingotSilicon Ingot



A Wafer with Dies



Categories for processing stepsChange the surface material

Add extra materialRemove materialMixture of above three



PhotolithographyFabrication sequence of a chip consists of a processcalled photolithography

Photolithography :-process used to transfer patterns to each layer of theIC

Photolithography sequence steps:Designer:Drawing the layer patterns on a layout editor

Silicon Foundry:

Masks generation from the layer patterns in thedesign data basePrinting: transfer the mask pattern to the wafersurfaceProcess the wafer to physically pattern each layer ofthe IC



Basic sequence The surface to be patterned is:

spin-coated with photoresistthe photoresist is dehydrated in anoven (photo resist: light-sensitiveorganic polymer)

The photoresist is exposed toultra violet light:For a positive photoresist exposedareas become soluble and nonexposed areas remain hard

The soluble photoresist ischemically removed(development).

The patterned photoresist will nowserve as an etching mask for theSiO2

1. Photoresist coating

SiO2

Photoresist

Substrate

3. Development

Substrate

Substrate

Mask

Ultra violet lightOpaque

ExposedUnexposed

2. Exposure

Photolithography



The SiO2 is etched awayleaving the substrate

exposed:the patterned resist is used asthe etching mask

Ion Implantation:

the substrate is subjected tohighly energized donor oracceptor atomsThe atoms impinge on thesurface and travel below it

The patterned silicon SiO 2 serves as an implantation maskThe doping is further driveninto the bulk by a thermalcycle

4. Etching

Substrate

Substrate

5. Ion implant

Substrate

6. After doping

diffusion

Photolithography



The lithographic sequence is repeated foreach physical layer used to construct theIC. The sequence is always the same:

Photoresist applicationPrinting (exposure)Development

Etching

Photolithography



Patterning a layer above the silicon surface

SubstrateSiO 2

Polysilicon

1. Polysilicon deposition

2. Photoresist coating

photoresist

Substrate

Substrate

3. Exposure UV light

Substrate

4. Photoresist development

Substrate

5. Polysilicon etching

Substrate

6. Final polysilicon pattern

Photolithography



CMOS Inverter Cross Sectionn-well process :-

Use p-type substrate for nMOS transistorsRequires n-well for body of pMOS transistors

A

Y

V DD

GN

D

nM

O S

pM

O S

s s

n+

p substrate

p+

n well

A

YGND V

DD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor



Well and Substrate TapsSubstrate must be tied to GND and n-well to V DD

Metal to lightly-doped semiconductor forms poorconnection called Schottky DiodeUse heavily doped well and substrate contacts /taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+



Inverter Mask SetTransistors and wires are defined by

masksCross-section taken along dashed line

GND V DD

Y

A

substrate tap well tapnMOS transistor pMOS transistor



Detailed Mask Views

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

6 Masks:-

n-well

Polysilicon

n+ diffusion

p+ diffusionContact

Metal



Fabrication steps : Inverter

n+

p substrate

p+

n well

A

YGND

VDD

n+p+

substrate tap well tap

n+ p+



Fabrication steps : InverterStart with a blank waferBuild the inverter from the bottom upFirst step is to build n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2

p substrate



OxidationGrow SiO2 on top of Si wafer

900 – 1200 C with H2O or O2 in oxidationfurnace

p substrate

SiO 2



Photoresist coatingSpin on photoresist

Photoresist is a light-sensitive organicpolymerSoftens where exposed to light

p substrate

SiO 2

Photoresist



Photoresist exposureExpose photoresist through n-well mask

Strip off exposed photoresist

p substrate

SiO 2

Photoresist



EtchingEtch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone; nastystuff!!!

Only attacks oxide where resist has been

exposed

p substrate

SiO 2

Photoresist



Strip photoresistStrip off remaining photoresist

Use mixture of acids called piranah etchNecessary so resist doesn ’ t melt in nextstep

p substrate

SiO 2

ll



n-Welln-well is formed with diffusion or ion implantation

DiffusionPlace wafer in furnace with arsenic gasHeat until As atoms diffuse into exposed Si

Ion Implantation

Blast wafer with beam of As ionsIons blocked by SiO2, only enter exposed Si

n well

SiO 2

d



Strip oxideStrip off the remaining oxide using HF

Back to bare wafer with n-wellSubsequent steps involve similar series ofsteps

p substraten well

l ili



PolysiliconDeposit very thin layer of gate oxide

< 20 Å (6-7 atomic layers)Grow polysilicon layer through chemical vapor depositionPlace wafer in furnace with Silane gas (SiH 4)Forms many small crystals called polysilicon

Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substrate n well

P l ili i



Polysilicon patterning

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well

Use same photolithography process to pattern

polysilicon

diff i



n+ diffusionSimilar to n-well process

Use oxide and masking to expose where n+dopants should be diffused or implantedn-diffusion forms nMOS source, drain, and n-well contact

p substrate

n well

diff i



n+ diffusionPattern oxide and form n+ regions

Self-aligned process where gate blocks diffusionPolysilicon is better than metal for self-alignedgates because it doesn ’ t melt during laterprocessing

p substraten well

n+ Diffusion

diff i



n+ diffusionHistorically dopants were diffused

Usually ion implantation todayBut regions are still called diffusion

n wellp substrate

n+n+ n+

diff i



p+ diffusionSimilar set of steps form p+ diffusion regions

for pMOS source and drain and substratecontact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

C



ContactsNow we need to wire together the devices

Cover chip with thick field oxideTo insulate wafer from metalPatterned with the contact mask

Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

M t lli ti



MetallizationSputter on aluminum over whole wafer

Pattern to remove excess metal, leavingwires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

6 CMOS Fabrication

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