Seminar: Fabrication and Characteristics of CMOS

FABRICATION AND CHARACTERISTICS OF

CMOS

GUNJAN GUPTA 10BEC112JAY BAXI 10BEC115

Institute of Technology, Nirma University Semester V

Under Guidance of : Prof Vijay Savani

Flow of the Presentation

• 2 Terminal MOS• Energy Band Diagrams of MOS in various operating

regions• nMOS I-V Characteristics• pMOS I-V Characteristics• Pass Transistors• MOS Capacitor• Gate and Diffusion Capacitance• RC Delay Models

2 Terminal MOS

• Structure consists of three layers:– The metal gate electrode– The insulating oxide (SiO2) layer, – The p-type bulk semiconductor (Si), called the

substrate.• MOS structure forms a capacitor, with the gate

and the substrate acting as the two terminals (plates) and the oxide layer as the dielectric.

2 Terminal MOS

2 Terminal MOS

• Thickness of the silicon dioxide layer is usually between 10 nm and 50nm.

• The carrier concentration and its local distribution within the semiconductor substrate can now be manipulated by the external voltages applied to the gate and substrate terminals.

Energy Band Diagrams (nMOS)

• The energy band diagram of the p-type substrate is shown in Fig. below. The band-gap between the conduction band and the valence band for silicon is approximately 1.1 eV.

• The location of the equilibrium Fermi level EF within the band-gap is determined by the doping type and the doping concentration in the silicon substrate.

• The Fermi potential OF, which is a function of temperature and doping, denotes the difference between the intrinsic Fermi level Ej, and the Fermi level Ef


• For a p-type semiconductor, the Fermi potential can be approximated by:

• Whereas for a n-type semiconductor, the Fermi potential can be approximated by:

• Here, k denotes the Boltzmann constant and q denotes the unit (electron) charge.


• The electron affinity of silicon, which is the potential difference between the conduction band level and the vacuum (free-space) level, is denoted by qX in upcoming figure.

• The energy required for an electron to move from the Fermi level into free space is called the work function qs, and is given by

Energy Band Diagrams of the combined nMOS systems

• The insulating silicon dioxide layer between the silicon substrate and the gate has a large band-gap of about 8 eV and an electron affinity of about 0.95 eV. On the other hand, the work function q0M of an aluminum gate is about 4.1 eV.

• Part of this built-in voltage drop occurs across the insulating oxide layer. The rest of the voltage drop (potential difference) occurs at the silicon surface next to the silicon-oxide interface, forcing the energy bands of silicon to bend in this region.

• The Fermi potential at the surface, also called surface potential, is smaller in magnitude than the bulk Fermi potential,


Resulting Combined Energy Band Diagram Of The nMOS System


Resulting Combined Energy Band Diagram Of The pMOS System

nMOS under External Bias

• Assume that the substrate voltage is set at VB = 0, and let the gate voltage be the controlling parameter.

• Depending on the polarity and the magnitude of VG, three different operating regions can be observed for the MOS system:– Accumulation– Depletion, and – Inversion.

Energy Band Diagram – nMOS operating in Accumulation region

• If a negative voltage VG is applied to the gate electrode, the holes in the p-type substrate are attracted to the semiconductor-oxide interface.

• The majority carrier concentration near the surface becomes larger than the equilibrium hole concentration in the substrate; hence, this condition is called carrier accumulation on the surface.

• In this case, the oxide electric field is directed towards the gate electrode.

• The negative surface potential also causes the energy bands to bend upward near the surface.

Energy Band Diagram – nMOS operating in Accumulation region

Energy Band Diagram – nMOS operating in Depletion region

• Consider a small positive gate bias VG is applied to the gate electrode. Since the substrate bias is zero, the oxide electric field will be directed towards the substrate in this case.

• The positive surface potential causes the energy bands to bend downward near the surface.

• The majority carriers, i.e., the holes in the substrate, will be repelled back into the substrate as a result of the positive gate bias, and these holes will leave negatively charged fixed acceptor ions behind.

• Thus, a depletion region is created near the surface.


• The cross-sectional view and the energy band diagram of the MOS structure operating in depletion mode, under small gate bias.

• The change in surface potential required to displace this charge sheet dQ by a distance Xd away from the surface can be found by using the Poisson equation.


• Integrating along the vertical dimension (perpendicular to the surface) yields

• Thus, the depth of the depletion region is

Energy Band Diagram – nMOS operating in Inversion region

• To complete qualitative overview of different bias conditions and their effects upon the MOS system, consider a further increase in the positive gate bias.

• As a result of the increasing surface potential, the downward bending of the energy bands will increase as well.

• Eventually, the mid-gap energy level Ei becomes smaller than the Fermi level EFP on the surface, which means that the substrate semiconductor in this region becomes n-type.

• Within this thin layer, the electron density is larger than the majority hole density, since the positive gate potential attracts additional minority carriers(e-) from the bulk substrate to the surface.

• The n-type region created near the surface by the positive gate bias is called the inversion layer, and this condition is called surface inversion.

• It will be seen that the thin inversion layer on the surface with a large mobile electron concentration can be utilized for conducting current between two terminals of the MOS transistor.



• Once the surface is inverted, any further increase in the gate voltage leads to an increase of mobile electron concentration on the surface, but not to an increase of the depletion depth.

• Thus, the depletion region depth achieved at the onset of surface inversion is also equal to the maximum depletion depth xdm , which remains constant for higher gate voltages.

• Using the inversion condition, the maximum depletion region depth at the onset of surface inversion can be given as:

pMOS Accumulation

pMOS Depletion

pMOS Inversion

nMOS Capacitor

• Gate and body form MOS capacitor• Operating modes

– Accumulation– Depletion– Inversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < Vt

depletion region

(c)

+-

Vg > Vt

depletion regioninversion region

nMOS Cutoff

• No channel• Ids = 0

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d

nMOS Linear

• Channel forms• Current flows from d to s

– e- from s to d

• Ids increases with Vds

• Similar to linear resistor

+-

Vgs > Vt

n+ n+

+-

Vgd = Vgs

+-

Vgs > Vt

n+ n+

+-

Vgs > Vgd > Vt

Vds = 0

0 < Vds < Vgs-Vt

p-type body

p-type body

b

g

s d

b

g

s dIds

nMOS Saturation

• Channel pinches off• Ids independent of Vds

• We say current saturates• Similar to current source

+-

Vgs > Vt

n+ n+

+-

Vgd < Vt

Vds > Vgs-Vt

p-type body

b

g

s d Ids

I-V Characteristics

• In Linear region, Ids depends on– How much charge is in the channel?– How fast is the charge moving?

Channel Charge

• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

• Qchannel = CV

• C = Cg = eoxWL/tox = CoxWL

• V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9)

polysilicongate

Cox = eox / tox

Carrier velocity

• Charge is carried by e-• Carrier velocity v proportional to lateral E-field

between source and drain• v = mE m called mobility• E = Vds/L• Time for carrier to cross channel:

– t = L / v

nMOS Linear I-V

• Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

tW VC V V VL

VV V V

ox = W

CL

nMOS I-V Summary

• Shockley 1st order transistor models

2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

pMOS I-V characteristics

• All dopings and voltages are inverted for pMOS

• Mobility mp is determined by holes– Typically 2-3x lower than that of electrons mn

• Thus pMOS must be wider to provide same current– In this class, assume mn / mp = 2

Capacitance

• Any two conductors separated by an insulator have capacitance

• Gate to channel capacitor is very important– Creates channel charge necessary for operation

• Source and drain have capacitance to body– Across reverse-biased diodes– Called diffusion capacitance because it is

associated with source/drain diffusion

Gate Capacitance

• Approximate channel as connected to source• Cgs = eoxWL/tox = CoxWL = Cper-micronW

• Cpermicron is typically about 2 fF/mm

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.90)

polysilicongate

Diffusion Capacitance

• Undesirable• Capacitance depends on area and perimeter

– Use small diffusion nodes– Comparable to Cg

for contacted diff– ½ Cg for uncontacted– Varies with process

MOS Capacitance SummeryMOSFET Device

CapacitanceMOS Transistor Gate Capacitance Model

Pass Transistors

• We have assumed source is grounded• What if source > 0?

– e.g. pass transistor passing VDD

• Vg = VDD

– If Vs > VDD-Vt, Vgs < Vt

– Hence transistor would turn itself off

• nMOS pass transistors pull no higher than VDD-Vtn

– Called a degraded “1”– Approach degraded value slowly (low Ids)

• pMOS pass transistors pull no lower than Vtp

VDDVDD

Effective Resistance

• Shockley models have limited value– Not accurate enough for modern transistors– Too complicated for much hand analysis

• Simplification: treat transistor as resistor– Replace Ids(Vds, Vgs) with effective resistance R

• Ids = Vds/R

– R averaged across switching of digital gate• Too inaccurate to predict current at any given time

– But good enough to predict RC delay

RC Delay Model

• Use equivalent circuits for MOS transistors– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width• Resistance inversely proportional to width

kg

s

d

g

s

d

kCkC

kCR/k

kg

s

d

g

s

d

kC

kC

kC

2R/k

RC Values

• Capacitance– C = Cg = Cs = Cd = 2 fF/mm of gate width– Values similar across many processes

• Resistance– R 6 KW*mm in 0.6um process– Improves with shorter channel lengths

• Unit transistors– May refer to minimum contacted device (4/2 l)– Or maybe 1 mm wide device– Doesn’t matter as long as you are consistent

Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

d = 6RC

REFERENCES

• CMOS: Digital Integrated Circuits- Mao Su Kang and Yusuf Leblebici

• E-Digital Integrated• Principles of Data Conversion System Design-Behzad

Razavi• CMOS Integrated Analog-to-Digital and Digital-to-Analog

Converters- Rudy J. van• CMOS Circuit Design, Layout, and Simulation- Bake Li

Boyce• Design of Analog CMOS Integrated Circuits- Behzad Razavi

Thank You

Seminar: Fabrication and Characteristics of CMOS

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