Topic 3- CMOS Fabrication Steps

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    EE466: CMOS VLSI

    Lecture 04: Fabrication

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    CMOS VLSI Design0: Introduction Slide 2

    CMOS Fabrication

    CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or

    etched Easiest to understand by viewing both top and

    cross-section of wafer in a simplified manufacturingprocess

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    CMOS VLSI Design0: Introduction Slide 3

    Inverter Cross-section

    Typically use p-type substrate for nMOS transistors e!uires n-well for body of pMOS transistors

    n"

    p substrate

    p"

    n well

    #

    $

    %&' (''

    n" p"

    SiO)

    n" diffusion

    p" diffusion

    polysilicon

    metal*

    nMOS transistor pMOS transistor

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    CMOS VLSI Design0: Introduction Slide 4

    Well and Substrate Tas

    Substrate must be tied to %&' and n-well to ('' Metal to lightly-doped semiconductor forms poor

    connection called Shott+y 'iode se heavily doped well and substrate contacts taps

    n"

    p substrate

    p"

    n well

    #

    $%&' (''

    n"p"

    substrate tap well tap

    n" p"

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    CMOS VLSI Design0: Introduction Slide 5

    Inverter Mas! Set

    Transistors and wires are defined by masks Cross-section ta+en along dashed line

    %&' (''

    $

    #

    substrate tap well tap

    nMOS transistor pMOS transistor

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    CMOS VLSI Design0: Introduction Slide 6

    "etailed Mas! Vie#s

    Si. mas+s

    / n-well

    / 0olysilicon

    / n" diffusion/ p" diffusion

    / Contact

    / Metal

    Metal

    0olysilicon

    Contact

    n" 'iffusion

    p" 'iffusion

    n well

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    CMOS VLSI Design0: Introduction Slide 7

    Fabrication Stes

    Start with blan+ wafer 1uild inverter from the bottom up 2irst step will be to form the n-well

    / Cover wafer with protective layer of SiO)3o.ide4/ emove layer where n-well should be built

    / 5mplant or diffuse n dopants into e.posed wafer

    / Strip off SiO)

    p substrate

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    CMOS VLSI Design0: Introduction Slide 8

    O$idation

    %row SiO)on top of Si wafer

    / 677 / *)77 C with 8)O or O)in o.idation furnace

    p substrate

    SiO)

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    CMOS VLSI Design0: Introduction Slide 9

    %&otoresist

    Spin on photoresist

    / 0hotoresist is a light-sensitive organic polymer

    / Softens where e.posed to light

    p substrate

    SiO)

    0hotoresist

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    CMOS VLSI Design0: Introduction Slide 0

    Lit&o'ra&(

    E.pose photoresist through n-well mas+ Strip off e.posed photoresist

    p substrate

    SiO)

    0hotoresist

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    CMOS VLSI Design0: Introduction Slide

    Etc&

    Etch o.ide with hydrofluoric acid 3824

    / Seeps through s+in and eats bone9 nasty stuff::: Only attac+s o.ide where resist has been e.posed

    p substrate

    SiO)

    0hotoresist

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    CMOS VLSI Design0: Introduction Slide 2

    Stri %&otoresist

    Strip off remaining photoresist

    / se mi.ture of acids called piranah etch &ecessary so resist doesn;t melt in ne.t step

    p substrate

    SiO)

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    CMOS VLSI Design0: Introduction Slide 3

    n-#ell

    n-well is formed with diffusion or ion implantation 'iffusion

    / 0lace wafer in furnace with arsenic gas

    / 8eat until #s atoms diffuse into e.posed Si 5on 5mplanatation

    / 1last wafer with beam of #s ions

    / 5ons bloc+ed by SiO), only enter e.posed Si

    n well

    SiO)

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    CMOS VLSI Design0: Introduction Slide 4

    Stri O$ide

    Strip off the remaining o.ide using 82 1ac+ to bare wafer with n-well Subse!uent steps involve similar series of steps

    p substrate

    n well

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    CMOS VLSI Design0: Introduction Slide 5

    %ol(silicon

    'eposit very thin layer of gate o.ide/ < )7 = 3>-? atomic layers4

    Chemical (apor 'eposition 3C('4 of silicon layer

    / 0lace wafer in furnace with Silane gas 3Si8@4/ 2orms many small crystals called polysilicon

    / 8eavily doped to be good conductor

    Thin gate o.ide

    0olysilicon

    p substraten well

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    CMOS VLSI Design0: Introduction Slide 6

    %ol(silicon %atternin'

    se same lithography process to pattern polysilicon

    0olysilicon

    p substrate

    Thin gate o.ide

    0olysilicon

    n well

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    CMOS VLSI Design0: Introduction Slide 8

    +-di))usion

    0attern o.ide and form n" regions Self-aligned processwhere gate bloc+s diffusion 0olysilicon is better than metal for self-aligned gates

    because it doesn;t melt during later processing

    p substraten well

    n" 'iffusion

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    CMOS VLSI Design0: Introduction Slide 9

    +-di))usion cont,

    8istorically dopants were diffused sually ion implantation today 1ut regions are still called diffusion

    n wellp substrate

    n"n" n"

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    CMOS VLSI Design0: Introduction Slide 20

    +-di))usion cont,

    Strip off o.ide to complete patterning step

    n wellp substrate

    n"n" n"

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    CMOS VLSI Design0: Introduction Slide 2

    %-"i))usion

    Similar set of steps form p" diffusion regions forpMOS source and drain and substrate contact

    p" 'iffusion

    p substraten well

    n"n" n"p"p"p"

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    CMOS VLSI Design0: Introduction Slide 22

    Contacts

    &ow we need to wire together the devices Cover chip with thic+ field o.ide Etch o.ide where contact cuts are needed

    p substrate

    Thic+ field o.ide

    n well

    n"n" n"p"p"p"

    Contact

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    CMOS VLSI Design0: Introduction Slide 23

    Metaliation

    Sputter on aluminum over whole wafer 0attern to remove e.cess metal, leaving wires

    p substrate

    MetalThic+ field o.ide

    n well

    n"n" n"p"p"p"

    Metal

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    CMOS VLSI Design0: Introduction Slide 24

    Transistors as S#itc&es

    Ae can view MOS transistors as electricallycontrolled switches

    (oltage at gate controls path from source to drain

    g

    s

    d

    g B 7

    s

    d

    g B *

    s

    d

    g

    s

    d

    s

    d

    s

    d

    nMOS

    pMOS

    O22O&

    O&O22

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    CMOS VLSI Design0: Introduction Slide 25

    CMOS Inverter

    # $

    7

    *

    (''

    # $

    %&'# $

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    CMOS VLSI Design0: Introduction Slide 26

    CMOS Inverter

    # $

    7

    0

    (''

    #B* $B7

    %&'

    O&

    O22

    # $

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    CMOS VLSI Design0: Introduction Slide 27

    CMOS Inverter

    # $

    0

    * 7

    (''

    #B7 $B*

    %&'

    O22

    O&

    # $

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    CMOS VLSI Design0: Introduction Slide 28

    CMOS +*+" .ate

    # 1 $

    7 7

    7 *

    * 7

    * *#

    1

    $

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    CMOS VLSI Design0: Introduction Slide 29

    CMOS +*+" .ate

    # 1 $

    0 0

    7 *

    * 7

    * *

    #B7

    1B7

    $B*

    O22

    O& O&

    O22

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    CMOS VLSI Design0: Introduction Slide 30

    CMOS +*+" .ate

    # 1 $

    7 7 *

    0

    * 7

    * *

    #B7

    1B*

    $B*

    O22

    O22 O&

    O&

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    CMOS VLSI Design0: Introduction Slide 3

    CMOS +*+" .ate

    # 1 $

    7 7 *

    7 * *

    0

    * *

    #B*

    1B7

    $B*

    O&

    O& O22

    O22

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    CMOS VLSI Design0: Introduction Slide 32

    CMOS +*+" .ate

    # 1 $

    7 7 *

    7 * *

    * 7 *

    0

    #B*

    1B*

    $B7

    O&

    O22 O22

    O&

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    CMOS VLSI Design0: Introduction Slide 33

    CMOS +O/ .ate

    # 1 $

    7 7 *

    7 * 7

    * 7 7

    * * 7

    #

    1$

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    CMOS VLSI Design0: Introduction Slide 34

    -inut +*+" .ate

    $ pulls low if #LL inputs are * $ pulls high if #&$ input is 7

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    CMOS VLSI Design0: Introduction Slide 35

    -inut +*+" .ate

    $ pulls low if #LL inputs are * $ pulls high if #&$ input is 7

    #

    1

    $

    C

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    CMOS VLSI Design0: Introduction Slide 36

    La(out

    Chips are specified with set of mas+s Minimum dimensions of mas+s determine transistor

    sie 3and hence speed, cost, and power4

    2eature sie fB distance between source and drain

    / Set by minimum width of polysilicon

    2eature sie improves D7 every D years or so

    &ormalie for feature sie when describing design

    rules E.press rules in terms of B f)

    / EFgF B 7FD m in 7F> m process

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    CMOS VLSI Design0: Introduction Slide 37

    Si1li)ied "esi'n /ules

    Conservative rules to get you started

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    CMOS VLSI Design0: Introduction Slide 38

    Inverter La(out

    Transistor dimensions specified as Aidth Length/ Minimum sie is @ ), sometimes called * unit

    / 5n fB 7F> m process, this is *F) m wide, 7F> mlong

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    CMOS VLSI D i0 I t d ti Slid 39

    Su11ar(

    MOS Transistors are stac+ of gate, o.ide, silicon Can be viewed as electrically controlled switches 1uild logic gates out of switches 'raw mas+s to specify layout of transistors

    &ow you +now everything necessary to startdesigning schematics and layout for a simple chip: