CMOS Fabrication [Compatibility Mode]

7/29/2019 CMOS Fabrication [Compatibility Mode]

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CMOS FabricationCMOS FabricationEMT 251


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Objectives

To discussed the fundamentals ofCMOS fabrication steps.

To examined the major steps of the

process flow. To overview the cross section view of

a circuit


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Chip making Process


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Introduction

MOSFET

CMOSPMOSNMOS


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SourceDrain

Gate

Metal Oxide Semiconductor Field Effect Transistor

Source (Arsenic, Phosphorous, Boron)

Drain (Arsenic, Phosphorous, Boron)

Gate (Aluminum, Polysilicon)

MOSFET


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NMOS

P-type substrate

N-type dopant for Source & Drain

Inversion layer is formed to conduct electricity


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NMOS

P-type substrate

N-type dopant for Source & Drain



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PMOS

N-type substrate

P-type dopant for Source & Drain



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PMOS

N-type substrate

P-type dopant for Source & Drain



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CMOS

A combination of both NMOS & PMOS technology

Most basic example: inverter


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WELL FORMATIONWELL FORMATION

ISOLATION FORMATIONISOLATION FORMATION

TRANSISTOR MAKINGTRANSISTOR MAKING

INTERCONNECTIONINTERCONNECTION

PASSIVATIONPASSIVATION

PROCESS FLOW


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CMOS FABRICATION PROCESSwell formation

Start with clean p-typesubstrate (p-type wafer)


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Grow epitaxy layer (made fromSiO2) as mask layer for wellformation


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By *photolithography andetching process, well opening aremade

*photolithography and etch processes are shown in next slides

Well will be formedhere


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Photolithography (CED)

P-substrateSi02

photoresist

Photoresist coating (C)

Masking and exposureunder UV light(E) Resist dissolved after

developed (D) Pre-shape the well

pattern at resist layer

P-substrate

mask

UV light

Opaquearea

Transparentarea


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etching

Removing the unwantedpattern by wet etching

Resist clean Desired pattern formed

P-substrate

P-substrate


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Ion bombardment by ion implantation

SiO2 as mask, uncovered area will

exposed to dophant ion

Phosphorus ion


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CMOS FABRICATION PROCESS

transistor making

Grow very thin gate oxide atelevated temperature in veryshort time

Gate oxide


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Deposit polisilicon layer


transistor making

polisilicon


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Photolithography (photo) andetching to form gate pattern


transistor making

gate


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transistor making

Photo process to define the nmossactive (source and drain) area and

VDD contact Ion implantation with Arsenic ion forn+ dophant.

Photoresist and polisilicon gate act asmask

photoresist

Arsenic ion


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CMOS FABRICATION PROCESStransistor making

Nmoss Source and drain with VDDcontact formation

Resist removal

source drainVDD

contact


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transistor making

Photo process to define the GND contact

and pmoss active area (source and drain) Ion implantation with boron ionto have p+

dophant Photoresist and gate act as mask

Boron ion

photoresist


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interconnection

Deposit SiO2 layer throughout wafer surface

SiO2


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Photo and etching process tomake contact


interconnection

contact


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Metal 1 deposition throughout

wafer surface

CMOS FABRICATION PROCESSinterconnection

Metal 1


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interconnection

Photo and etching processes topattern interconnection


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Mask Layout


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Mask Layout


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Mask Layout


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Mask Layout


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A A

oxide

p-substrate

n+ n+

N-well

p+p+

Metal 1


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AssignmentB

B


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GLOSSARY Photolithography (photo)

Process of transferring pattern on mask to photoresist layer on wafersurface (pre-pattern the chip)

Etching Process of permanently removed the unwanted part of design on wafer

surface to get the desired pattern Diffusion

Process of introducing dophant layer by movement of dophant atomsfrom high concentration to low concentration area at high temperature

Ion implantation Process of introducing dophant layer by bombardment of high energydophant ion in high electric field chamber

Oxidation Process of growing thick or thin SiO2 layer depend on oxide application

CMP Process to physically grind flat to have a planar surface for better

exposure at photo process.


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CMOS Fabrication [Compatibility Mode]

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