Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

CMOSManufacturing

Process

CMOS Process

Circuit Under Design

This two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.

VDD VDD

Vin Vout

Circuit Layout

Process Flow

These slides only present only a couple of snapshots of the

manufacturing process for the circuits presented in the textbook.

For a complete overview of all 62 steps, please refer to:

http://tanqueray.eecs.berkeley.edu/~ehab/inv.html.

Credits for these pictures go to Ehab Hakeem, Prof. Andrew Neureuther and the Simpl program.

Start Material

Starting wafer: n-type withdoping level = 10 13/cm3

* Cross-sections will be shown along vertical line A-A’

N-well Construction

(1) Oxidize wafer(2) Deposit silicon nitride(3) Deposit photoresist

N-well Construction

(4) Expose resist using n-wellmask

N-well Construction

(5) Develop resist(6) Etch nitride and(7) Grow thick oxide

N-well Construction

(8) Implant n-dopants (phosphorus)

(up to 1.5 m deep)

P-well Construction

Repeat previous steps

Grow Gate Oxide

0.055 m thin

Grow Thick Field Oxide

Uses Active Area mask

Is followed by threshold-adjusting implants

0.9 m thick

Polysilicon layer

Source-Drain Implants

n+ source-drain implant(using n+ select mask)

Source-Drain Implants

p+ source-drain implant(using p+ select mask)

Contact-Hole Definition

(1) Deposit inter-level dielectric (SiO2) — 0.75 m

(2) Define contact opening using contact mask

Aluminum-1 Layer

Aluminum evaporated (0.8 m thick)

followed by other metal layers and glass

Advanced Metalization

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

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