Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

19
Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Manufacturing Process CMOS Manufacturing Process

Transcript of Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Page 1: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

CMOSManufacturing

Process

Page 2: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

CMOS Process

Page 3: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Circuit Under Design

This two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.

VDD VDD

Vin Vout

M1

M2

M3

M4

Vout2

Page 4: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Circuit Layout

Page 5: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Process Flow

These slides only present only a couple of snapshots of the

manufacturing process for the circuits presented in the textbook.

For a complete overview of all 62 steps, please refer to:

http://tanqueray.eecs.berkeley.edu/~ehab/inv.html.

Credits for these pictures go to Ehab Hakeem, Prof. Andrew Neureuther and the Simpl program.

Page 6: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Start Material

Starting wafer: n-type withdoping level = 10 13/cm3

* Cross-sections will be shown along vertical line A-A’

A

A’

Page 7: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

N-well Construction

(1) Oxidize wafer(2) Deposit silicon nitride(3) Deposit photoresist

Page 8: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

N-well Construction

(4) Expose resist using n-wellmask

Page 9: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

N-well Construction

(5) Develop resist(6) Etch nitride and(7) Grow thick oxide

Page 10: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

N-well Construction

(8) Implant n-dopants (phosphorus)

(up to 1.5 m deep)

Page 11: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

P-well Construction

Repeat previous steps

Page 12: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Grow Gate Oxide

0.055 m thin

Page 13: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Grow Thick Field Oxide

Uses Active Area mask

Is followed by threshold-adjusting implants

0.9 m thick

Page 14: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Polysilicon layer

Page 15: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Source-Drain Implants

n+ source-drain implant(using n+ select mask)

Page 16: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Source-Drain Implants

p+ source-drain implant(using p+ select mask)

Page 17: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Contact-Hole Definition

(1) Deposit inter-level dielectric (SiO2) — 0.75 m

(2) Define contact opening using contact mask

Page 18: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Aluminum-1 Layer

Aluminum evaporated (0.8 m thick)

followed by other metal layers and glass

Page 19: Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Digital Integrated Circuits © Prentice Hall 1995Manufacturing ProcessManufacturing Process

Advanced Metalization