Lect2 CMOS Process - Yonsei Universitytera.yonsei.ac.kr/class/2013_1/lecture/Lect3 CMOS...

Review of CMOS Processing Technology

Prof. Woo-Young ChoiSpecial Topics in Computers and Circuits (13/1)

- Scaling and Integration

Moore’s Law



Unit processes

Thin Film Deposition

Etching

Ion Implantation

Photolithography

Chemical Mechanical Polishing



1. Thin Film Deposition

Layer of materials ranging from fractions of nanometer to several micro meters in thickness

- Types of Thin Film Deposition

• Physical Vapor Deposition (PVD)

- Vaporized material bombards onto substrate.

• Chemical Vapor Deposition (CVD)

- Gaseous material reacts on substrate to form thin film



• Evaporation (Thermal, E-beam)

• Sputtering (DC, RF, Ion beam)

• Aluminum, Copper, Titanium,

Tungsten silicide

Physical Vapor Deposition (PVD)




Chemical Vapor Deposition (CVD)

• Gases react on the substrate

to form the desired thin films

• LPCVD (Low Pressure)

PECVD (Plasma Enhanced)

LACVD (Laser Assisted)

MOCVD (Metal Organic) …




- SiO2 etching by HF- Si3N4 etching by H3PO4- Si etching by KOH

-Wet etching avoided if possible: hazard materials, undercut

2. Etching

Wet Etching

Semiconductor

Solution

Film

ProductsReaction

Reactants



2. Etching

- Dry etching: chemical reaction with gases to eliminate desired material- RIE (Reactive Ion Etching), ICP (Inductive Coupled Plama) , IBE (Ion Beam Etching)

Typical parallel-plate reactive ion etching system.



3. Ion Implantation

Ion implantation for doping:

As, P for N-doping

B for for P-doping



3. Ion Implantation

- Gas Source: Ionizes source gas- Acceleration by bias- Beam control by magnetic field

Key Control Parameters: - Beam Currents (tens of A ~ tens of mA) No. of ions implanted

- Implantation Energy (tens of keV ~ MeV)Depth of implantation

- Thermal annealing is required after implantation



Produces patterns by transferring mask patterns onto the substrate

(Example: patterning of oxide/nitride thin film)

4. Photolithography



4. Photolithography

- Resolution mainly limited by of light

UV Deep UV Extreme UV (tens of nms)

- Masks are typically realized withdirect e-beam writing



5. Chemical Mechanical Polishing (CMP)

Makes the wafer surface flat for better lithography

• Chemical Mechanical Planarization(CMP) combines chemical action with

mechanical abrasion to achieve selective material removal through polishing



Metal 1

GateSource Drain

Invertor

Schematic●

Layout●



P-substrate

N-well

SiN Spacersilicide

Metal 1

Dielectric

P+ N+STI

Gate Oxide

Polysilicon

CMOS Structure●



Active region

SiO

Shallow Trench Isolation(STI)

Silicon dioxide

●

P-substrate



Well Formation●

P-substrate

N-well

Active region

Photolithography Ion implantation



Gate

Drain &Source

Poly Silicon Thin Gate Oxide

N+P+

P-substrate

N-well

Gate and Source/Drain Formation●

Gate Oxide Formation Photolithography Ion implantation



P-substrate

N-well

Metal 1

SiN Spacersilicide

Metal 1

Dielectric

Contacts and Metallization●



P-substrate

N-well

SiN Spacersilicide

Metal 1

Dielectric

P+ N+STI

ThinGateOxide

Polysilicon

CMOS Fabrication Result●



- CMOS Circuit Design Process



Design example: CMOS inverter●

<Inverter schematic>

● Schematic Simulation(Synopsis HSPICE, Cadence SPECTRE)



● Layout(Cadence VIRTUOSO)

Layout of mask patterns for photolithography



● Rule Checking (Mentor CALIBRE, Synopsis HERCULES, Cadence ASSURA)

- Design Rule Checking (DRC)

No design rules for a given process should be violated during layout

- These rule checking must be satisfied before fabrication can start

- Layout vs. Schematic (LVS)

Make sure layout is identical to schematic



● Parasitic RC extraction(Synopsis StarRC)



● Post Layout Simulation

Pre-simPo-sim

Pre-simPo-sim

- Modify your design if needed



- Complicated Digital Circuit Design

- Impossible to do transistor-level simulation- Impossible to layout by hands

Behavior-level design using Hardware Description Language (Mentor ModelSim)



- Automatic Gate-level Synthesis (Synopsis Design_Vision)

-Auto Layout(Synopsis Astro)



● Example

<Layout>

<Fabricated chip>

Lect2 CMOS Process - Yonsei Universitytera.yonsei.ac.kr/class/2013_1/lecture/Lect3 CMOS...

Documents

Transcript of Lect2 CMOS Process - Yonsei Universitytera.yonsei.ac.kr/class/2013_1/lecture/Lect3 CMOS...