Lecture 2- CMOS Fabrication Process · CMOS Fabrication Process The CMOS process requires that both...

Lecture 2- CMOS Fabrication

Process

Dr. Mohamed Refky Amin

Electronics and Electrical Communications Engineering Department (EECE)

Cairo University

[email protected]

http://scholar.cu.edu.eg/refky/

Outline of this Lecture

• Previously on ELCN321

• CMOS Fabrication Process

– The Clean Room

– The Silicon Wafer

– Fabrication Steps

• Poly-Gate NMOS Process Sequence

2

First bipolar

transistor

(1947)

First MOSFET

transistor

(1960)

One-transistor

DRAM cell

(1968)

IC invented

(1958)

First

Microprocessor

(1971)

CMOS

(1963)

1940 1950 1960 1970 1980 1990 2000 2010

First bipolar

transistor

(1947)

First MOSFET

transistor

(1960)

One-transistor

DRAM cell

(1968)

IC invented

(1958)

First

Microprocessor

(1971)

CMOS

(1963)

VLSI era

1940 1950 1960 1970 1980 1990 2000 2010

Previously on ELCN321

3


Since the beginning of the VLSI era, the minimum feature length

of an integrated circuit has been reduced at a rate of about 20%

per year.

Introduction

4

Design Stages


Specifications

Implementation

Prototyping

Manufacturing

Pre-silicon

Post-silicon

Sy

nth

esis

an

d V

alid

atio

n

Man

ufa

ctu

rin

g a

nd

tes

tin

g

5


DefinitionDesign metrics are the properties that we use to evaluate the

performance of the integrated circuit.

The design metrics are:

The importance of these metrics depends upon the application

(speed is a crucial property in a compute server while energy

consumption is a dominant metric for cell phones).

Cost Reliability

Speed Scalability

Power and Energy Consumption

6

Introduction

Fabrication process is the steps through which the design go to be

converted into a physical circuit.

Learning the steps of the fabrication process is quite handy in

understanding:

• The physical constraints that are imposed on a designer

of an integrated circuit.

• The impact of the fabrication process on issues such as

cost.

Our focus will be on the CMOS fabrication process.

Fabrication Process

7

CMOS Fabrication Process

The CMOS process requires that both n-channel (NMOS) and p-

channel (PMOS) transistors be built in the same silicon material.

To accommodate both types of devices, wells must be created in

which the semiconductor material is opposite to the type of the

channel.

Fabrication Process

8


A clean room is an environment used in manufacturing

semiconductor engineering applications with a low level of

environmental pollutants such as dust, airborne microbes, aerosol

particles, and chemical vapors.

The Clean Room

A clean room is classified by

the level of contamination that

is specified by the number of

particles per cubic meter at a

specified particle size.

9


The typical urban environment contains 35,200,000 particles per

cubic meter in the size range 0.5μm and larger in diameter.

The Clean Room

Class

Maximum particles/m3 FED STD

209E

equivalent≥0.1 µm ≥0.2 µm ≥0.3 µm ≥0.5 µm ≥1 µm ≥5 µm

ISO 1 10

ISO 2 100 24 10

ISO 3 1,000 237 102 35 Class 1

ISO 4 10,000 2,370 1,020 352 83 Class 10

ISO 5 100,000 23,700 10,200 3,520 832 Class 100

ISO 6 1,000,000 237,000 102,000 35,200 8,320 293 Class 1,000

ISO 7 352,000 83,200 2,930 Class 10,000

ISO 8 3,520,000 832,000 29,300 Class 100,000

ISO 9 35,200,000 8,320,000 293,000 Room air

10


An ISO 1 cleanroom allows no particles in the size range 0.5μm

and only 10 particles per cubic meter of 0.1μm and smaller.

The Clean Room

Class

Maximum particles/m3 FED STD

209E

equivalent≥0.1 µm ≥0.2 µm ≥0.3 µm ≥0.5 µm ≥1 µm ≥5 µm

ISO 1 10

ISO 2 100 24 10

ISO 3 1,000 237 102 35 Class 1

ISO 4 10,000 2,370 1,020 352 83 Class 10

ISO 5 100,000 23,700 10,200 3,520 832 Class 100

ISO 6 1,000,000 237,000 102,000 35,200 8,320 293 Class 1,000

ISO 7 352,000 83,200 2,930 Class 10,000

ISO 8 3,520,000 832,000 29,300 Class 100,000

ISO 9 35,200,000 8,320,000 293,000 Room air

11


Insufficiently clean environment reduces the yield dramatically

The Clean Room

12


Insufficiently clean environment reduces the yield dramatically

The Clean Room

Sin

gle

Lay

er

Particle causing short-

circuit

Particle causing open-

circuit

Particle causing current

restriction

Two Layer Short

13


To have an ultra precision clean room that is suitable for

semiconductor fabrication, many parameter must be controlled:

The Clean Room

Clean Room Controlled Parameters

Air Cleaning Temperature/Humidity

Pressure Air Flow

Electromagnetic Electrostatic

Noise Micro-Vibration

14


The Silicon Wafer

15


The production starts with the

Czochralski growth.

A silicon ingot is produced by

melting the sand is in a crucible

at 1425 degrees Celsius.

Dopant impurity atoms is added

to dope the silicon to produce p-

type or n-type silicon.

The Silicon Wafer

Wafer Production Steps

Czochralski growth

16


The second step is grinding and

slicing step.

The ingot is grounded to the

desired diameter. Then, an

orientation flat (or notch) is

added.

The ingot is cut into wafers.

The Silicon Wafer


Czochralski growth

Grinding and Slicing

17


The third step is Lapping and

Etching step.

The wafer is lapped on both

sides in between two counter-

rotating pads by slurry.

This step removes the damaged

surface silicon and thin the

wafer to the desired thickness.

The Silicon Wafer


Czochralski growth


Lapping and Etching

18


The wafer is then etched in

order to remove any remaining

damaged surface.

The Silicon Wafer


Czochralski growth


Lapping and Etching

19


The final step is Polishing and

Cleaning step.

Two pads with ultra fine slurry

are used to remove the remaining

roughness on the atomic scale

from the wafer surface.

This step results in a super flat,

mirrored surface.

The Silicon Wafer


Czochralski growth


Lapping and Etching

Polishing and Cleaning

20


The creation of the source and drain regions, well implant, and

the adjustments of the device threshold require changing the

dopant concentration of the material.

Diffusion and ion implantation are two techniques to change the

dopant concentration of the material.

In both techniques, the area to be doped is exposed, while the rest

of the wafer is coated with a layer of buffer material, typically

SiO2.

Fabrication Steps

Diffusion and Ion Implantation

21


In diffusion implantation, the wafers are placed in a quartz tube

embedded in a heated furnace. A gas containing the dopant is

introduced in the tube.

The high temperatures of the furnace, typically 900 to 1100 °C,

cause the dopants to diffuse into the exposed surface both

vertically and horizontally.

The final dopant concentration is the greatest at the surface and

decreases in a gaussian profile deeper in the material.

Fabrication Steps


22


In ion implantation, a beam of purified ions is directed over the

semiconductor surface.

The acceleration of the ions determines how deep they will

penetrate the material, while the beam current and the exposure

time determine the dosage.

The ion implantation method allows for an independent control

of depth and dosage. This is an advantage over the diffusion

implantation technique.

Fabrication Steps


23


The down side of the ion implantation technique is the lattice

damage.

Lattice damage happen due to the nuclear collisions that cause

the displacement of substrate atoms.

Lattice damage is resolved by applying a subsequent annealing

step, in which the wafer is heated to around 1000°C for 15 to 30

minutes, and then allowed to cool slowly. The heating step

thermally vibrates the atoms, which allows the bonds to reform.

Fabrication Steps


24


All the fabrication process requires the deposition of layers of a

material over the complete wafer, to either act as buffers for a

processing step, or as insulating or conducting layers.

Oxidation deposition forms a layer of SiO2 that is required for

photolithography step.

Polysilicon is deposited using a chemical deposition process,

which flows silane gas over the heated wafer coated with SiO2 at

a temperature of approximately 650°C.

Fabrication Steps

Deposition

25


The silicon nitride (Si3N4), which is a buffer material during the

formation of the field oxide, is deposited using a process called

chemical vapor deposition (CVD), which uses a gas-phase

reaction with energy supplied by heat at around 850°C.

The Aluminum interconnect layers are typically deployed using a

process known as sputtering.

Fabrication Steps

Deposition

26


Etching step is used to selectively form patterns such as wires

and contact holes.

Etching is classified into two groups, wet etching and dry etching.

The wet etching process makes use of acid or basic solutions. As

an example, hydrofluoric acid buffered with ammonium fluoride

is typically used to etch SiO2.

Fabrication Steps

Etching

27


In dry etching, a wafer is placed into the etch tool's processingchamber and given a negative electrical charge.

The chamber is heated to 100°C and brought to a vacuum level of7.5 Pa, then filled with a positively charged plasma (usually amix of nitrogen, chlorine and boron trichloride).

The opposing electrical charges cause the rapidly moving plasmamolecules to align themselves in a vertical direction, forming amicroscopic chemical and physical sandblasting action whichremoves the exposed material.

Fabrication Steps

Etching

28


Plasma etching has the advantage of offering a well-defined

directionality to the etching action, creating patterns with sharp

vertical contours.

Fabrication Steps

Etching

29


Planarization is the process through which the surface of a layer

is made approximately flat before depositing a new layer onto it.

Chemical mechanical planarization (CMP) step is usually

included before the deposition of an extra metal layer on top of

the insulating SiO2 layer.

CMP uses a slurry (a liquid carrier with aluminum oxide or

silica) compound to microscopically plane a device layer.

Fabrication Steps

Planarization

30


The fabrication process includes wide range of tasks like

oxidation, etching, metal and polysilicon deposition, and ion

implantation.

Fabrication Steps

Photolithography

Photolithography is the technique

through which a certain area on the

chip is masked out using an

appropriate optical mask so that a

desired processing step can be

selectively applied to the remaining

regions.

31


This step deposits a thin layer of

SiO2 over the complete wafer

The oxidation is done by

exposing it to a mixture of high-

purity oxygen and hydrogen at

approximately 1000°C.

The oxide is used as an

insulation layer and also forms

Photolithography (Operations)

Oxidation Layering

transistor gates.

32


Photoresist is a light sensitive

polymer that is applied to the

wafer to a thickness of

approximately 1 mm.

The polymer is called negative

if it is originally soluble in an

organic solvent, but has the

property that the polymers

cross link when exposed to


Photoresist Coating

property that the polymers cross link when exposed to light,

making the affected regions insoluble.

33


The polymer is called positive

if it is originally insoluble, but

soluble after light exposure.


Photoresist Coating

34


The pattern that is required to

be transferred to the silicon is

printed on a glass mask.

The mask is opaque in the

regions that we want to

process, and transparent in the

others (assuming a negative

photoresist).


Stepper Exposure

35


The combination of glass mask

and wafer is exposed to ultra-

violet light. The photoresist

becomes insoluble at the area

where the mask is transparent.


Stepper Exposure

36


The wafers are developed in

either an acid or base solution

to remove the soluble areas of

photoresist.

Once the exposed photoresist is

removed, the wafer is soft-

baked at a low temperature to

harden the remaining

photoresist.


Photoresist Development and Baking

37


The Layer under process is

etched by remove the material

from areas of the wafer that are

not covered by photoresist.

This etching process is

accomplished through the use of

different types of acid that

suites the material that is to be

removed.


Acid Etching

38


The wafer is cleaned with

deionized water and dries it

with nitrogen.


Spin, Rinse, and Dry

39


The exposed area are subjected

to a wide range of process steps,

such as ion implantation,

plasma etching, or metal

deposition.


Various Process Steps

40


A high-temperature plasma is

used to selectively remove the

remaining photoresist without

damaging device layers.


Photoresist Removal (Ashing)

41


Due to technology scaling, the minimum feature sizes in

integrated circuits makes the photolithography difficult.

Photolithography

Techniques such as optical-mask

correction (OPC) is applied to the

drawn patterns to account for the

diffraction phenomena, encountered

when printing close to the limits of

optical lithography.

42


The process starts with the

definition of the active regions

where transistors will be

constructed.

All other areas of the die is

covered with a thick layer of

SiO2 (field oxide).

The field oxide acts as the

insulator between neighboring

devices

Poly-Gate NMOS Process Sequence

Define active areas

Etch and fill trenches

43


For PMOS, slightly doped n-

wells are formed through ion

implantation.

A thin layer of SiO2 (gate

oxide) separates the region

between the source and drain.

The gate oxide is covered by

conductive polysilicon to form

the gate of the transistor.


Define active areas


Implant well regions

Deposit and pattern polysilicon

layer

44


To construct an NMOS

transistor, heavily doped n-type

source and drain regions are

implanted into the p-type

substrate.

To construct an PMOS

transistor, heavily doped p-type

source and drain regions are

implanted into the slightly

doped n-wells.


Define active areas




layer

Implant source and drain regions

and substrate contacts

45


Multiple insulated layers of

metallic wires are deposited on

top of these devices to provide

the necessary interconnections

between the transistors.


Define active areas




layer

Implant source and drain regions

and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

46



Wafer clean

Grow field oxide

Mask 1 (Active Area)

Etch oxide

Strip photoresist/Clean

Grow gate oxide

Deposit polysilicon

Initial Setup

47

Mask 2 (Gate)

Etch polysilicon


S/D and poly dope implant

Anneal



Deposit oxide

48

Mask 3 (Contact)

Etch contact cuts


Al deposition



Mask 4 (Metal)

Etch Aluminum


Metal anneal

49

Lecture 2- CMOS Fabrication Process · CMOS Fabrication Process The CMOS process requires that both...

Documents

Transcript of Lecture 2- CMOS Fabrication Process · CMOS Fabrication Process The CMOS process requires that both...