CMOS Fundamentalsand

Fabrication Steps

CMOS LAYOUT DESIGN

C omplementaryM etalO xideS emiconductor

CMOS Fundamentals

p+ substrate

n+ n+

Gate

DrainSource

• For Channel to be formed:VGS > 0If this is not followed, channel will notbe formed.

• If Vsource = Logic HI and Gate is made logic HIabove condition is not met and channel is notformed prominantly.It appears like this:

Source Drain

Very high resistance

n+ substrate

p+ p+

Gate

DrainSource

• For Channel to be formed:VGS < 0If this is not followed, channel will notbe formed.

• If Vsource = Logic LO and Gate is made logic LOabove condition is not met and channel is notformed prominantly.It appears like this:

Source Drain

Very high resistance

CMOS FundamentalsStrong - '0'

CMOS FundamentalsWeak - '1'

CMOS FundamentalsWeak - '0'

CMOS FundamentalsStrong - '1'

• For a good Layout Engineer it is important to know the Principlesof Electronic Circuits.

• One has to realize that five types of parasitics could get createdwith every layout. These are: Diodes, junction transistors, SCRs,capacitors and resistors.

• The parasitics can affect the response time of the circuit and evenits reliability.

• It is the job of the CMOS Layout Engineer to: minimize the effects of these devices in a circuit.

Many microchips have failed because of a parasiticdevice.

CMOS Fundamentals

• An Integrated Circuit (IC) is an electronic network that hasbeen fabricated on a single piece of semiconductor materialsuch as Silicon.

• The basic building block of an IC is a transistor.

• Passive elements, such as resistors and capacitors are notalways included as elements in the circuits, but arise asparasitic due to electrical properties of the materials.

• The wiring among the devices is achieved using“Interconnects”.

CMOS Fundamentals

The primary switching devices in High Density Integrated Circuitsare MOSFETs (Metal Oxide Semiconductor Field Effect Transistor)for the following reasons:

!They are extremely small.

!The "drain" and "source" terminals are interchangeable.

!The device structures are very simple.

CMOS Fundamentals

• The process used to transfer the pattern to the semiconductoris called LITHOGRAPHY .

• The lithographic sequence has the following major steps:

AN INTEGRATED CIRCUIT IS A SET OF PATTERNED LAYERS

! Drawing the patterns using a Layout Editor.! Preparing each pattern for physical transfer to the wafer.! Transferring the pattern on the wafer (called printing).! Using processing techniques to physically pattern each layer.

CMOS Fundamentals

Initial Layering

Photo-resist Coating

Exposure

Development

Etching

Layer Specific Processeg. Ion Implantation,CVD formation, Poly-Silicon formation etc.

CMOS FundamentalsBasic Fabrication Steps

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

• A p-type Epitaxial layer is grown on the starting material which is p+ type substrate.• It is used as the base layer on which the devices will be formed.• Provides protection against Latchup condition by decreasing the transistor betas.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

Resist

• Resists are acid-resistant coatings of a photosensitive organic material.• This material gets polymerized by UV rays.• Resists are of two types: Positive Photoresists and Negative Photoresists• When polymerized photoresist becomes susceptible to removal, it is called "positive photoresist".• When non-polymerized photoresist becomes susceptible to removal, it is called "negativephotoresist".

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

UV RaysUV Rays are made incidenton the wafer through a "mask".

Polymerization takes placehere.

This area remainsnon-polymerized.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

Since this area is non-polymerizedit gets dissolved in an organicsolvent.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

Arsenic Ions for forming the n well. This process is called ion implantation.Doping (Diffusion)

n-well

Resist The depth is governed by the temperatureof wafer at the time of diffusion andimpinging energy of the ions.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Location of p-MOS deviceLocation of n-MOS device

• Wherever the mask is opaque, the material under it is not exposed to UV rays.• Wherever the mask is transparent, the material under it is exposed to UV rays.• Wherever exposed, the photo-resist becomes susceptible to removal and is removed using anorganic solvent.• Subsequently, all the material under it is etched away chemically.• After this, the photo-resist elsewhere is also removed.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Thin Oxide

• A thin layer of oxide is grown on the wafer.• This layer is to provide isolation for the next process of growing thick oxide.• It also acts as a "stress relieving" layer.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

Thin Oxide Silicon Nitride

n-well

• Silicon Nitride layer is used to prevent oxidation from happening in the region being definedas "active region" (where the active devices would be formed).• The "thin oxide" layer under the Silicon Nitride is called "stress relief" oxide layer and is usedas a mechanical buffer between the nitride and substrate.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Thin Oxide Silicon NitridePhotoresist

• Preparation of one more step of Photolithography by way of depositing one more layer ofphotoresist.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

UV RaysUV Rays are made incidenton the wafer through a "mask".

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

• Wherever the mask is opaque, the material under it is not exposed to UV rays.• Wherever the mask is transparent, the material under it is exposed to UV rays.• Wherever exposed, the photo-resist becomes susceptible to removal and is removed using anorganic solvent.• Subsequently, all the material under it is etched away chemically.• After this, the photo-resist elsewhere is also removed.

n-well

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

• The nitride and the thin oxide layers are selectively etched away (chemically) and waferis prepared for deposition of thick oxide layer.

Area where thick oxide will be formed.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

Thick Oxide layer

n-well

• The thick oxide layer prevents the lateral diffusion of active devices as well as preventsunnecessary device currents from flowing.• When the oxide is formed on the wafer, it grows vertically and horizontally in both the directions.This is because of its chemical properties.

Vertical and Lateral Growth of Oxide

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

• The nitride and the stress relief oxide layers are removed and the substrate is now exposed.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

Gate Oxide

n-well

• A thin layer of oxide, which would be used as the "gate oxide" is formed.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

• Preparation for depositing the Poly-Silicon. This forms the gate of the transistor.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

• UV rays are made incident on the wafer through the mask. Areas of photoresist that are exposedto UV rays get polymerized and can be removed.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Gate Oxide

• Polymerized resist areas are removed and this is where the polysilicon would be deposited.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Gate OxidePoly-Silicon

• Polysilicon is deposited wherever resist is not present. The thickness of the gate is controlled.However, the length of polysilicon is what matters.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

• The photoresist layer is removed by dissolving it in organic solvents.• Extra thin oxide layer has to be removed so that the die is ready for forming the diffusion areas.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

• Now die is ready for forming the diffusion areas.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Resist

• Areas except where the Arsenic ions are to be diffused are covered by photoresist.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+

Arsenic Ions for forming the n+ diffusion layerDoping (Diffusion)

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+

Resist

• Areas except where the Boron ions are to be diffused are covered by photoresist.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

Boron Ions for forming the p+ diffusion layer

n+ n+ p+ p+

Doping (Diffusion)

p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+p+

• The formation of active devices is completed and now the steps are to be taken to build contacts for the active regions and the gate. Contacts that are provided for active devices are called"active contacts" while those provided for gate are called "gate contacts".

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CVD/ LTO Oxide - Chemical Vapour Deposition Oxide/ Low Temperature Oxide

CVD Oxide/ LTO is used so that underlying doped regions do not undergo any diffusion spreading.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

• Preparation for building contacts.

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

Metal1

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

VIA Cut

CMOS Fabrication Steps

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

Metal2Via12

CMOS Schematic, Stick Plan and Layout

THREE BASIC LOGIC FUNCTIONS:

"INVERTER

"NAND

"NOR

INVERTER NAND

NOR

CMOS Layout Design

INPUT SYMBOLS OUTPUT SYMBOLS

SOURCE (GROUND)

-V

+V

A

A

A

POWER

CONNECTION

A

B

A

“SHORT”MOSFET

N TYPE P TYPE

CMOS Layout DesignSymbols Used in the Design

CMOS Layout DesignLogic Gates and their Boolean Equivalents

AND-OR-INVERT

OR-AND-INVERT

CMOS Layout DesignLogic Gates and their Boolean Equivalents

W/L = 10/0.2

W/L = 10/0.2

Size for PMOS

Size for NMOS

Sizes can also be different for PMOS and NMOS

Specification of gate dimensions

Specified as W(width)/L(length) ratio

Length(L)

Diffusion

Polysilicon

Illustration of gate dimensions

Wid

th(W

)

Layout and Stick Plan• Stick Plan : Representation of device layout using lines(sticks)

• Layout : Physical structure of the device

x x

Stick Plan

Contact

Poly

xDiffusion

Layout Poly

Contact

Diffusion

Symbol

Transistor is formed here

Transistors in series

A B C

X Y

A B C

X Y

A X YB C

Diffusion sharing

Layout

Stick plan

Diffusion sharing

A X YB A

A B A

X YStick plan

Transistors in parallelLayout

A ABA

B

X Y

X Y

A B

Logic Symbol

Schematic

B = AA B0 11 0

Truth Table

Layout

A

B

C

Schematic

Layout

A BC

Layout

+V

B

+V

A

-V-V

AB

C

I/PI/P

A C B

I/P I/P

Schematic

CMOS Layout DesignLogic Functions

ANDOperation

OROperation

I/P I/P

A

BC

Logic Symbol

Schematic

___C = A••••B

A B C0 0 10 1 11 0 11 1 0

Truth Table

A

BC

Logic Symbol

___ C = A+B

A B C0 0 10 1 01 0 01 1 0

Truth Table

A

B

C

A

C

B

Layout

-V

+V+V

-V

C

Layout

+V+V

-V -V

A B

C

C

SchematicC

A

B

CMOS Layout DesignLogic Functions

CMOS Layout DesignLogic Functions to Schematic - Euler's Method

Schematic

A

B

C

Schematic

C

A

B

+V +V1

2

3

0

1

2

3

0

B

ACan beswapped

+V

-V

P+

N+

XX X1 A 2 B 1

A B

XX X30 2

C

XX X1 A 2 B 3

A B

XX X30 0

C

A B

-V -V

Stick Plan Stick Plan

CMOS Layout DesignLogic Functions with Complex Gates - Steps for Construction of Schematic

A

B

C

D

Y

VDD

Step - 2: Draw the schematic of the simple device as shown

Step - 3: Put down the basic AND gate series structure with Nmos transistors in the bottom arm bubbles

A

B

C

D

Y

Simple DeviceNOR: 2 Nmos in parallel 2 Pmos in series

Step - 1: Identify the Simple Device

Step - 4: Put the parallel equivalents of the series structure of step3 and put Pmos transistors in the top arm bubbles

Example: AND - OR - INVERT Logic Function

VDD

A

B

C

D

A

C

B

D

Basic AND GateStructure

Whatever is in series in the bottomarm, should be connected inparallel in the top arm and theNmos should be replaced by Pmos

CMOS Layout DesignLogic Functions with Complex Gates - Schematic Diagram

Y

A

B

C

D

Y

1

2

3

4 5

0

XX X1A 2 B1

A B

3

0

2

C

Stick Plan

X X XD

2

X X X X XC D4 3 5 0

Diffusion has to be cutto prevent shorting

A

B

C

D

Y

CMOS Layout DesignLogic Functions with Complex Gates

Example: OR - AND - INVERT Logic Function

VDD

A

B

C

D

A

C

B

D

Y

Basic OR GateStructure

Whatever is in parallel in the bottomarm, should be connected inseries in the top arm and theNmos should be replaced by Pmos

Stick Plan

1

2

3

4

5

0

X X X

X X

X

X X X X

1 A 2 B C D

A B

C D

3 4X

0 5 0 5 3 5

Diffusion has to becut to prevent shorting

A

C

D

E

Y

CMOS Layout DesignLogic Functions with Complex Gates

B A

B

C

D

E

D E

A CB

+V

-V

+V

-V

A

B

C

E

D

AB C

DE

1

2

3

4

5

6

0

X X X X XX

X XX X X X

1 A 2 B C D E

A B C

D E

3 4 5

0 6 0 6 4 6

Logic Diagram

Stick Plan

Schematic

1

CMOS Layout DesignLogic Functions with Complex Gates

ABC

D

E

F

YA

B

C

D E

F'

D

E

F'

A B C

-V

+V

-V

+V

A B C

D

EF'

A

B

C

F'

YY

-V

+V

F F'

1

2

3

4

5

6

7

0

X X X X X X X

X X

X X

X X X X X X X

A B C D E F'

A B C

D E F'

F

F

X

1 2 3 4 5 4 5 1

1

0

F'

070 0 7 6 4 7

Logic Diagram

SchematicStick Plan

D E

CMOS Layout DesignTransmission Gates

Symbols:

P

• Transmission Gates are also called Pass Gates.• PMOS and NMOS transistors are arranged so that gate passes both Good-0 and Good-1

CMOS Layout DesignTransmission Gates

G1

G2

A BX

X

X

X

A G1 B

BG2A

Logic DiagramStick Plan

CMOS: Design Rules

What is the logic circuit/ device whose layout isshown below?

CMOS: Design Rules

N Well

N Well Taps

P+

Poly

N+

Active Contact

Substrate Taps

Active Contact

N-Well Enclosure of P typediffusion

N-Well Spacing to N typeactive

Polysilicon Endcap length

Metal Enclosure of contact

Metal width

CMOS: General Design Rules

Sr. No. Description Dimensions in microns

1 a) Minimum N-Well enclosure of P type active 0.6 b) Minimum N-Well enclosure of N type active 0.15 c) Minimum N-Well space to P type active 0.15 d) Minimum N-Well space to N type active 0.6 e) Minimum N-Well width 1.2 f) Minimum N-Well space to N-Well 0.62 a) Minimum P+ width 0.4 b) Minimum P+ space to same type active 0.4 c) Minimum P+ space to opposite type active 0.43 a) Minimum N+ width 0.4 b) Minimum N+ space to same type active 0.4 c) Minimum N+ space to opposite type active 0.44 a) Minimum polysilicon width 0.24 b) Minimum polysilicon space to polysilicon 0.36 c) Minimum polysilicon space to active 0.4 d) Minimum gate space to gate 0.36 e) Minimum polysilicon endcap length 0.45 a) Minimum contact width 0.3 b) Maximum contact width 0.3 c) Minimum contact space to contact 0.3 d) Minimum active enclosure of contact 0.14 e) Minimum polysilicon enclosure of contact 0.14 f) Minimum polysilicon contact space to active 0.28 g) Minimum active contact space to polysilicon 0.226 a) Minimum metal1 width 0.32 b) Minimum metal1 space to metal1 0.32 c) Minimum metal1 enclosure of contact 0.01

CMOS: General Design Rules

CMOS: Design Rules2 Input NAND Gate

1a1a

1b

1 d)

1 e)

1 f)

2 a)

2 c)

3 a)5 a)5 c)

3 c)

6 a)

5 c)

5 d)

6 b)

4 d)

4 a)

4 e)

4 b)4 c)

CMOS: Parasitic Components

CMOS: Parasitic Components

• DIODES (P-N JUNCTIONS)

• RESISTORS

• CAPACITORS

• TRANSISTORS

• THYRISTORS

CMOS: Parasitic Components

p type Epitaxial Layer

p+ type Substrate

n-well

n+ n+ p+ p+

Metal2Via12

p-n junctions

CMOS: Parasitic Components - Latchup Condition

p+ n+ n+ p+ p+ n+

INOUT

p type Substrate

n-well

Rwell

Rsubstrate

VDDVSS

Q1Q2

Q2

VDD

VSS

Rsubstrate

Q1

Rwell

• Slight noise or surge could cause Q1 or Q2 to get active.• If Q1 goes active, its collector current causes a drop in Rwell and thispushes Q2 towards active - saturation.• This in turn would push Q1 towards saturation.• Ultimately, both Q1 and Q2 would saturate causing a heavy currentto flow between VDD and VSS.• IT’S A SHORT CIRCUIT!!! This is called "latch-up".

Can be prevented by:• Reducing Rwell and Rsubstrate.• Reducing the Betas (gains) of the transistors.

CMOS: Process Related Effects

CMOS: Process Related Effect

• Process Antenna Effect• Hot Carrier Effect• Electromigration

CMOS: Finger Gates and Bent Gates

FINGER GATES AND BENT GATES

MAIN OBJECTIVES

❁ IMPORTANCE

❁ FINGER GATES APPROACH 1 . FINGERGATES IN SERIES 2 . FINGER GATES IN PARALLEL 3 . EXAMPLES

❁ BENT GATES

IMPORTANCE

IN FABRICATION FOUNDRY, THE SIZE OF THE GATE ISRESTRICTED, i.e. FOR EXAMPLE , IF THEFABRICATION SUPPORTS MAXIMUM OF 50µm OFGATE SIZE ,THEN HOW TO ACHIEVE A GATE SIZE OF100µm/ 150 µm/ 200 µm etc .

TO SOLVE THE ABOVE PROBLEM THE FOLLOWINGTWO APPROACHES ARE USED

1. FINGER GATES APPROACH

2. BENT GATES APPROACH

FINGER GATES APPROACH

Suppose the required GATE SIZE =W/L = 30 µm/ 2 µmMaximum Gate Size restriction from foundry = 10 µm / 2 µm

To obtain a gate size of 30 µm /2 µm with the existing10 µm /2 µm gate size facility,the diffusion width is dividedinto three portions (10 µm /2 µm) as shown in figure.

EXAMPLE

A

A

A B

B

B

A A BB

A

B

G 30 µm/2 µm

Required gate size = 30 µm/2 µmActual gate size = 10 µm/2 µm (each leg)

G

10µ/2µ

10µ/2µ

10µ/2µ

B A

RESULTANT VIEW

A B B A A B

LAYOUT

SCHEMATICA

B

G

GGG

B

A

G G G

By sharing the diffusion, the threegates of size 10 µm /2 µm inparallel, are controlled by samesignal.The structure looks likefinger structure, hence it is calledfinger gates.

LIKE WISE , A GATE WIDTH OF 15 µm /2 µm CAN BE OBTAINED BY 10 µm /2 µm PLUS 5 µm /2 µm .

15 µm /2 µm = 10 µm /2 µm + 5 µm /2 µm

A

B

G

15 µm/2 µm

15 µ

m /2

µm

10 µ

m /2

µm

5 µm

/2 µ

m

BA

G 10 µm /2 µm 5 µm /2 µm

B

AG

A

B

G

BEFORE SHARING

AFTER SHARING

A AB

G

LAYOUT SCHEMATIC

G

A

B

FINGER GATES IN SERIES

EXAMPLE : CONSTRUCT ION OF GIVEN CIRCUIT USING FINGER GATES WITH EACH FINGER HAVING THE SIZE OF 10 µm /2 µm

Y

Z

A

B

X30 µm /2 µm

20 µm /2 µm

SCHEMATICA

X

Y

Z

B

10µ/2µ10µ/2µ 10µ/2µ

10µ/2µ 10µ/2µ

Y Z

A BA

XXX

STICK PLAN

FINGER GATES IN PARALLEL

EXAMPLE : CONSTRUCT ION OF GIVEN CIRCUIT USING FINGER GATES WITH EACH FINGER HAVING THE SIZE OF 10 µm /2 µm

B

20µ/2µ 20µ/2µ

A

X10µ/2µ

A

B

10µ/2µ

X Y

Y

. .

. . Y

Z

B

X

STICK PLAN

B

AA A

SCHEMATIC

EXAMPLE : CONSTRUCT ION OF AN INVERTER USING FINGER GATES WITH EACH FINGER HAVING THE SIZE OF 15 µm /2 µm

A

X

30 µm /2 µm

15 µm /2 µm

A A A

30 µm /2 µm

15 µm /2 µm

VCC

VSS

A.

STICK PLANSCHEMATIC

A

VCC

VSS

AA

A

VCC

VSS

BENT GATES

IN THIS METHOD , THE GATE IS BENT INSIDE THE DIFFUSIONAREA TO ACHIEVE THE REQUIRED GATE SIZE. THIS METHOD ISNOT PREFERED BECAUSE DURING THE FABRICATION PROCESS ,TO MAINTAIN THE SAME WIDTH AND LENGTH OF GATE IS NOTPOSSIBLE DUE TO THE BENDING .HENCE FINGER GATESAPPROACH IS PREFERED.

EXAMPLEA

B

GA

BG

B

A

CMOS: Reverse Engineering

Reverse Engineering

Main objectives :

• What is reverse engineering

• Why it is required

• Steps required for layout to schematic conversion

• Examples

WHAT IS REVERSE ENGINEERING

Reverse Engineering

Layout Schematic/Logic circuit

Reverse Engineering is the process of converting layoutinto schematic /logic circuit.

WHY REVERSE ENGINEERING

P&RTool

Netlist Layout

Verify the compliance of netlist withlayout

STEPS FOR REVERSEENGINEERING A GIVEN PIECE

OF LAYOUT

• Identify VCC and VSS lines

• Identify sharing of diffusion

• Identify finger gates

• Identify OR and AND structures

• Conversion of layout to schematic

• Conversion of schematic to logic

INVERTER

A

VCC

VSS

A A

VCC

VSS

STICK PLAN SCHEMATIC LOGIC

A AA

A

B

VCC

VSS

A BA B

VCC

VSS

INVERTER USING FINGER GATES

STICK PLAN SCHEMATIC LOGIC