Cmos fabrication video Tirumala engineering college

1Lecture 5: IC Fabrication

The Transistor Revolution

First transistorBell Labs, 1948

© Rabaey: Digital Integrated Circuits2nd


The First Integrated Circuits

Bipolar logic1960’s

ECL 3-input GateMotorola 1966



Intel 4004 Micro-Processor

19711000 transistors1 MHz operation



Moore’s Law

161514131211109876543210

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F T

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ON

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Electronics, April 19, 1965.© Rabaey: Digital Integrated Circuits2nd


Silicon IC processing

Similar to photographic printing Expose the silicon wafer through a mask Process the silicon wafer Repeat sequentially to pattern all the layers

Layout: A set of masks that tell a fabricator what to pattern For each layer in your circuit Layers are metal, drain/source implants, gate, etc. You draw the layers

Subject to vendor-supplied spacing rules


The wafer

Czochralski process Melt silicon at 1425 °C Add impurities (dopants) Spin and pull crystal

Slice into wafers 0.25mm to 1.0mm thick

Polish one side


Crystal and wafer

Wand(a finished 250lb crystal)

A polished wafer


4X reticle

Wafer

The mask

Illuminate reticle on wafer Typically 4× reduction

Typical image is 25×25mm Limited by focus

Step-and repeat across wafer Limited by mechanical

alignment

10Lecture 5: IC Fabrication Reference: FULLMAN KINETICS

Lithography

Patterning is done by exposing photoresist with light

Requires many steps per “layer”

Example: Implant layer


Grow Oxide Layer

Reference: FULLMAN KINETICS


Add Photoresist


Mask


Animation

19Lecture 5: IC Fabrication9/03 IEEE spectrum


Patterning

How we pattern and expose the resist To make the

patterns we want on the silicon

IEEE Spectrum, 7/99, p. 41

21Lecture 5: IC Fabrication 9/03 IEEE spectrum


Detailed process sequence

1. Grow epi layer Ultra-pure single-

crystal silicon

2. Implant n-well


Detailed process sequence (con’t)

3. Define active area

4. Grow field oxide For isolation



5. Grow gate oxide

6. Pattern polysilicon



7. Form pFETs

8. Form nFETs



9. Deposit LTO by CVD LTO is low-temperature

oxide CVD is chemical vapor

deposition

10. Deposit Metal1 Usually aluminum



11. Via definition Deposit LTO Make via cuts

12. Deposit Metal2 Usually aluminum

13. Overglass (not shown) Coat entire chip with Si3N4

Make pad openings in Si3N4


An inverter


Figure courtesy Yan Borodovsky,

Intel

A Pentium cutaway


National 0.18µm process cutaway


Advanced Metallization - Copper

Copper versus Aluminum ~ 40% lower resistivity ~ 10× less electromigration


Interconnect Impact on Chip


10 100 1,000 10,000 100,000

Length (u)

No

of

ne

ts(L

og

Sc

ale

)

Pentium Pro (R)

Pentium(R) II

Pentium (MMX)

Pentium (R)

Pentium (R) II

Nature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

So

urc

e:

Inte

l


Permittivity


Projections

Simulated distribution of dopant atoms in a 0.05m nFET

red: acceptor atomblue: donor atom

All figures from IEEE Spectrum, 7/99


An AMD 50nm transistor


Frequency

P6Pentium ® proc

486386

28680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel© Rabaey: Digital Integrated Circuits2nd


Power Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase



Power density

400480088080

8085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp



Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

200

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1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty

Courtesy, ITRS Roadmap© Rabaey: Digital Integrated Circuits2nd


Cost of Integrated Circuits

NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor

Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area


NRE Cost is Increasing



Die Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)


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