Lecture 06,07 cmos fabrication

Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

ICE 4010: MICRO ELECTRO MECHANICAL SYSTEMS (MEMS)

Lecture #06, 07

CMOS Fabrication

Dr. S. Meenatchi SundaramEmail: [email protected]

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Inverter Cross-section with Well and Substrate taps

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• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors

• Substrate must be tied to GND and n-well to VDD

• Metal to lightly-doped semiconductor forms poorconnection

• Use heavily doped well and substrate contacts / taps

Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tap well tap

n+ p+

VDD

A=0 Y=1

GND

OFF

ON

Flow Diagram

3Dr S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

Create n-Well regions and Channel Stops region

Grow Field Oxide and Gate Oxide

Deposit and pattern Polysilicon Layer

Implant sources, drain regions and substrate contacts

Create contact Windows, deposit and pattern metal layer

Fabrication Procedure – Basic Steps

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• Masks: Each processing steps in the fabrication procedure requiresto define certain area on the chip. This is known as Masks.

• Chips are specified with set of masks

• Minimum dimensions of masks determine transistor size (and hencespeed, cost, and power)

• Feature size f = distance between source and drain

– Set by minimum width of polysilicon

• Feature size improves 30% every 3 years or so

• Normalize for feature size when describing design rules

• The ICs are viewed as a set of pattern layers of doped Silicon,Polysilicon, Metal and Insulating Silicon Dioxide.

• A layer must be Patterned before the next layer of material isapplied on the chip.


Inverter Mask Set

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• Transistors and wires are defined by masks

• Cross-section taken along dashed line


GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor

Detailed Mask Views

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• Six masks

– n-well

– Polysilicon

– n+ diffusion

– p+ diffusion

– Contact

– Metal


Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

Fabrication Steps

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• Start with blank wafer

• Build inverter from the bottom up

• First step will be to form the n-well

– Cover wafer with protective layer of SiO2 (oxide)

– Remove layer where n-well should be built

– Implant or diffuse n dopants into exposed wafer

– Strip off SiO2


p substrate

Oxidation

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• Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace


p substrate

SiO2

Photoresist

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• Used for lithography.

• Lithography is a process used to transfer a pattern to layer onthe chip. Similar to printing process.

• Spin on photoresist (about 1 mm thickness)

– Photoresist is a light-sensitive organic polymer

– Positive Photoresist: Softens where exposed to light

– Negative Photoresist: Harden where exposed to light, Notused in practice generally.


p substrate

SiO2

Photoresist

Lithography

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• Expose photoresist through n-well mask

• Strip off exposed photoresist


p substrate

SiO2

Photoresist

Etch

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• Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!!

• Only attacks oxide where resist has been exposed


p substrate

SiO2

Photoresist

Strip Photoresist

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• Strip off remaining photoresist

– Use mixture of acids called piranah etch

• Necessary so resist doesn’t melt in next step


p substrate

SiO2

Inverter Cross-section

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• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors


n+

p substrate

p+

n well

A

YGND V

DD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

Fabrication Procedure

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• Well

– Requires to build both pMOS and nMOS on single wafer.

– To accommodate both pMOS and nMOS devices, special

regions must be created in which the semiconductor type

is opposite of the substrate type.

– Also Known as Tubs.

– Twin-tubs


n Well

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• n-well is formed with diffusion or ion implantation

• Diffusion

– Place wafer in furnace with arsenic gas

– Heat until As atoms diffuse into exposed Si

• Ion Implantation

– Blast wafer with beam of As ions

– Ions blocked by SiO2, only enter exposed Si


n well

SiO2

Strip Oxide

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• Strip off the remaining oxide using HF

• Back to bare wafer with n-well

• Subsequent steps involve similar series of steps


p substrate

n well

Polysilicon

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• Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers)

• Chemical Vapor Deposition (CVD) of silicon layer

– Place wafer in furnace with Silane gas (SiH4)

– Forms many small crystals called polysilicon

– Heavily doped to be good conductor


Thin gate oxide

Polysilicon

p substraten well

Polysilicon Patterning

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• Use same lithography process to pattern polysilicon


Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well

n Diffusion

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• Use oxide and masking to expose where n+ dopants should be diffused or implanted

• N-diffusion forms nMOS source, drain, and n-well contact


p substraten well

n Diffusion

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• Pattern oxide and form n+ regions

• Self-aligned process where gate blocks diffusion

• Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing


n+ Diffusion

p substraten well

n Diffusion

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• Historically dopants were diffused

• Usually ion implantation today

• But regions are still called diffusion


n wellp substrate

n+n+ n+

n Diffusion

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• Strip off oxide to complete patterning step


n wellp substrate

n+n+ n+

p Diffusion

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• Similar set of steps form p+ diffusion regions for pMOSsource and drain and substrate contact


p+ Diffusion

p substraten well

n+n+ n+p+p+p+

Contacts

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• Now we need to wire together the devices

• Cover chip with thick field oxide

• Etch oxide where contact cuts are needed


Contact

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Metalization

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• Sputter on aluminium over whole wafer

• Pattern to remove excess metal, leaving wires


M etal

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

3D and 2D View


Testing


Defective IC

Individual integrated circuits are tested to distinguish good die

from bad ones.

Die cut and assembly


Good chips are attached to a lead frame package.

Die Attach and Wire Bonding


lead frame gold wire

bonding pad

connecting pin

Final Test


Chips are electrically tested under varying environmental conditions.

Lecture 06,07 cmos fabrication

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Transcript of Lecture 06,07 cmos fabrication