Motorola Wafer Level Burn-in and Test · • Burn-in for KGD at wafer level requires less test...

Tutorial on “Motorola Wafer Level Burn In and Test”2002 Southwest Test Workshop; Long Beach, CATeresa McKenzie; June 9, 2002

MotorolaWafer Level Burn-in and Test

2002 Southwest Test Workshop

Teresa McKenzie, Wafer Level Burn In EngineerMotorola ([email protected])

6501 William Cannon Drive West; Austin, Texas 78735; 512-895-4826


Agenda / Outline

• Motorola Wafer Level Burn In and Test- Direct Contact- Sacrificial Metal

• Sacrificial Metal Wafer Level Burn-in and Test Methodology

• History of Sacrificial Metal Wafer Level Burn-in and Test

• Challenges (Resolved and Present)


Direct Contact Key Milestones-Qualified process for C4-FCCBGA for PowerPC June 2001product (using Goremate)

-Demonstrated test capability for NCSG DSP March 2002product and TSPG 32bit MCU

-Working to qualify multi-use Goremate replacement August 2002

-Working to qualify 120um pitch Al wirebond August 2002full wafer contactor

-Entering product qualification phase for NSCG August 2002DSP product and TSPG 32bit MCU

-Working to qualify FC contact on eutectic, high Pb, End of 2002and no PB electroplate PBGA packages


TEL WLBT system installed in Motorola’s Final Manufacturing Factory in Austin


Target WLBT FlowCurrent Package Flow

Wafer Fab

Bump

Sort#1 Unit Probe

Memory Repair

Post Repair Unit Probe

Package BI

Post-BI Test

Pre-BI Test

Package Assembly

Wafer Fab

Bump

WLBT

Memory Repair

Unit Probe

Package Assembly

Final Test

Standard and WLBT Manufacturing flow for Power PC Devices


CTE matched core

GoreMateIITM

vacuum chuck

wafer

InfernoTM IC Board

expanded polytetrafluoroethylene(ePTFE) substrate

through platedconductor array

(Cu / Ni / Au)

multi-layer laminate

contact pad

Components of a Full Wafer Contact Solution for Bumped Die Products


WLBT PROCESS OVERVIEWWLBT PROCESS OVERVIEW

WLBT Probe & Wafer Assembly

WLBT Power/Test Module

Burn-in/Test Chambers

Aligner

System Control Module

Assembled WLBT Probe & Wafer

Align & Assemble Probe and Wafer

Load Probe+Wafer Assembly

into Test / Burn-in Chamber

Loader

Execute Test / Burn-in

Program

Unload Probe+Wafer

Disassemble Probe and Wafer

vacuum


KGD Sacrificial Metal WLBI- Definitions -

• Wafer Level Burn-In (WLBI) and Test– Parallel, dynamic, excitation of all devices on a wafer to screen for

marginal devices for infant mortality by dynamically stressing the integrated circuit at elevated temperature and voltage. Capable of non-volatile memory cycling, module exercising, and testing.

• Known Good Die (KGD)– Die having the same quality and reliability level as that of an

equivalent packaged part.

• Sacrificial Metal (SM)– Metal which is temporarily deposited on the wafer to provide

electrical signal paths to a die during wafer level burn-in and test. The sacrificial metal is etched away after burn-in and test is complete.


Why the need for WLBI?• Smaller form factor requirements in personal

communication, computer and automotive markets have increased demand for KGD.

• Burn-in for KGD at wafer level requires less test insertions and reduces cycle time than with die level burn-in. Similar cycle time reductions can also be realized for wirebond devices by screening out early life failures before assembly.

• WLBI provides quicker feedback to wafer manufacturing, which improves responsiveness to provide more effective process control.


WLBI Technology PartnersThe following cooperative effort is currently the only effective WLBI technology in production in the world:

• Motorola Semiconductor Products Sector– Transportation & Standard Products Group (TSPG) – Austin, TX

» Design and product engineering support for WLBI– Strategic Manufacturing Deployment (SMD) – Chandler, AZ / Austin, TX

» WLBI circuit definition» Production burn-in and data retention bake process» Post-WLBI data processing» WLBI circuit removal» Bump process» Saw, tape and reel

– MOS 12 Fab – Chandler, AZ» Wafer manufacturing» Probe support

• Delta V Instruments – Richardson, TX– Design and maintenance of WLBI systems– Assembly and repair of WLBI fixtures– WLBI software support


Wafer Level Burn-in MethodologyPackage Burn-in / Die-Level Burn-in Sacrificial Metal Wafer Level Burn-in

B

Wafer Probe

Carrier Load

Assembly

Dicing

Package Burn-in

Carrier Burn-in

Test

Test

Carrier Unload

Packaged Units KGD

WLBI and Dynamic Test

Wafer Probe (Reduced Time)

Dicing

Assembly

Test

Packaged Units KGD


5 inch Wafer Level Burn-In Methodology

Scribe Grid Edge

Polysilicon Resistor

Cu MiniBum p

M2 Main Bus Line "Ti-W-Cu"

M1/M2

Interconnec t

Field

Oxide

M2 Main Bus Line "Ti-W-Cu"

S

C

R

I

B

E

G

R

I

D

VSS

VDD

RECEIVE

RESET

CLOCK

Scribe Grid Structure

•Resistor in series with pad•Cross overs / cross unders for balanced power distribution•Bridge pass over die edge oxide moat

•Contact pogo pads placed at the edge of the wafer


5 inch Wafer Level Burn-In Methodology

Post wafer fab process (with polyimide)• Deposit, pattern and etch sacrificial metal

• Parallel electrical bussing of all die per quadrant• Photo define burn in contact pads• Contact current limiting resistors• Contact scribe grid cross-unders

• Burn-In and Data Retention Bake (DRB) test for NVM devices• Remove sacrificial metal• Die sales, bump or package


8” WLBI Methodology

12

8

1

2

11

3

4

5

7

9

10

13

14

N

E N D

G NB C A N

NADCENBN

G B N N G N N

CNENADCEN

B N N N B G D A N

A DNENADCEGN

N G B D N N G B C N N

E C N N A N G C D N N

ANBENNC EGN

B D N A G B N D A

NNCENNADBGN

E C N N E N C D

NANGBGENB

C D N A N N N

N G E C D N N

A

2

2

2

2 2

22

2 2

22

2 2

2 2

22

2 2

22

2 2

22

2

2

2NB

1

1

11

1 1

11

1 1

11

1 1

1 1

1 11

1 1 1 1

11

1 1 1

11

1 1 1

1

1

6

Cluster Arrangement - Viewed Looking at the Wafer Face


8 inch WLBI Methodology

Post wafer fab process (with polyimide)• Deposit, pattern and etch sacrificial metal

• Parallel electrical bussing of all die in a cluster• Wafer level burn in (6 to 24 hours @ 125 °C)• Data Retention Bake (2 to 24 hours @ 270 °C)• Remove sacrificial metal• Bump (flip chip only)• Wafer probe• Visual, dice, tape and reel• Ship to customer


History of Sacrificial Metal Wafer Level Burn-in

5 inch Wafer Program

• Development began in 1992• Eighteen wafer capacity system built in 1994• Production started in 1995• Full lot capacity production system built in 1997• Over 2 million KGD delivered since 1995 with no documented non-volatile memory (NVM) field failures


History of Sacrificial Metal Wafer Level Burn-in

8 inch Wafer Program

• Single wafer engineering system built in 1997

• Successful 8 inch WLBI in 1997

• Prototype Production System Built in 1998

• Production System Built in 1999


Resolved Challenges

Sacrificial Metal Criteria:

Poor sacrificial metal adhesion

•Good adhesion to polyimide•Proper conductivity to carry signals and voltages•Ease of sacrificial metal removal after WLBI and test•Maintain die pad integrity after sacrificial metal processing•Toughness to survive contactor and test conditions


Resolved ChallengesSacrificial Metal Design: S1 S2 S3 S4 S5

Power

Ground

R(scribe)

R(die)

R(die)= total conductor resistance from one die node to the next

R(scribe)= total resistance between two main burn-in conductor within sc

R(limit)= total resistance of the Current limiting resistor circuit

Burn-in test pad

Cross-section of node (die) contact

This repeats for every die

Each die is simulated as a

current source to ground

R(limit)

Wafer Flat

Cluster Scheme Die Scheme

•Adequate thickness and width to carry the necessary signals and voltages and maintain balanced power distribution.


Resolved Challenges

Polyimide Criteria:

Blistering sacrificial metal

• Proper adhesion to sacrificial metal and wafer during test conditions• Good definition for adequate step coverage• Sufficient cure to survive sacrificial metal processing and test conditions


Resolved Challenges

Contactor (Pogo Pin) Criteria:

QuickTime™ and aTIFF decompressor

are needed to see this picture.

Melted Heater Pin AreaVarious pogo pin head shapes

•Custom design spring force, travel distance, head shape, materials•Mechanically robust at elevated temperature and 1000s of cycles•Ability to integrate the pogo pins into the WLBI fixture


Resolved Challenges

Pogo Block Material Criteria:

Material A CTE 20 ppm/ºC

Material B CTE 2.5 ppm/ºC

•Cost•Material availability•Manufacturability and machinability•Durability during WLBI and test at elevated temperature•Maintaining planarity and adequate pogo pin compressionduring WLBI and test


Resolved Challenges

Yield Improvement Through Enhanced System Communication

Previous- Recognized Good / Bad Clusters Only- Final Test Results at Probe

Current- Recognize Individual Die- Generates Wafer Map Pass / Fail Codes Per Die

NC G G G G G G G

PE NC G G G G G G G G G G

PE G G G G G G G G G PE G G G

G G G G G G G G G G G G G G G G

G G G G G G G G G G G G G G G G G PE

G G G PE G G G G G G G G G PE G G NC PE G G

G G G G G G G G G G G G G G G G PE G G G

G G G G G G NC NS G G PE G G PE G G G G NC G

G G G G G G G G G G PE G G G G G G G G G G G

G PE PE G PE G G G G G G G G G G G G G G PE G G

NC G G G NC PE G G G G G PE G G G G G G NC G G G

NC G G G G G G G G G G G G G G G G G G G G G

G G NC G G PE G PE G G G G G G G PE G G G NC G G

G NC G G G G G G G PE G G G G G G G NC G G

PE G G G G G G PE G NS G G G G G G G G G G

G G G G NC G G G G G G G PE G G G G G

G G G G G G G G G G PE G G G G G G NC

NC G G NC G PE G NS G NC G NC G G G G

G G G G G G G G G G G G G G

G G G G G G G G G G

G PE G G G PE


Present Challenges

• High Contact Count (HCC)

Current HCC

# Pogo Pins About 600 About 3000

• WLBI Cold Temperature Test (-40 C)


Summary

Sacrificial Metal Wafer Level Burn-in and Test

• Sacrificial metal wafer level burn-in is a low cost test solution to achieving known good die.

• Motorola has been in production utilizing this technology since 1995.


Acknowledgments

This speaker would like to acknowledge the teamwork from various Motorola SPS groups,

Delta V Instruments, and Despatch Industries that contributed to the development and continuous

improvement of this Sacrificial Metal Wafer Level Burn-in and Test program.


Reference Articles• W. Ballouli and T. McKenzie, “Design For Sacrificial Metal Wafer-Level Burn-In”, 2001 EtroniX (Advanced Packaging) Conference, February 2001 (articles on CDROM).

•W. Ballouli, T. McKenzie, and N. Alizy, “Known Good Die Achieved Through Wafer-Level Burn-In and Test”, 26th IEEE/CPMT IEMT Symposium, October 2000, pp. 153-159.

• W. Ballouli, C. Beddingfield, F. Carney, and R. Nair, “Wafer-Level KGD Technology for DCA Applications”, Advanced Packaging, September 1999, pp. 26-30.

• T. McKenzie, “Wafer Level Burn-in (WLBI) Workshop”, Motorola Internal Publication, November 5, 1997.

• W. Ballouli, J. Stroupe, “TSM Approach to Wafer Level Burn-in”, Motorola Internal Publication, Motorola AMT Symposium, January 25, 1995.

Motorola Wafer Level Burn-in and Test · • Burn-in for KGD at wafer level requires less test...

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