A Reliable Wafer-Level Chip Scale Package (WLCSP) Technology
Probe Testing of Wafer Level Chip Scale Packaging · Probe Testing of Wafer Level Chip Scale...
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52 High Frequency Electronics High Frequency Design WAFER PROBE TESTING Probe Testing of Wafer Level Chip Scale Packaging By John Whittaker Teradyne W afer Level Chip Scale Packaging (WLCSP) has enabled smaller and thin- ner semiconductor devices with greater functionality to be used in consumer mobile applications such as smart phones, tablets and hand held GPS track- ing devices. There is an accelerating trend toward wafer level chip scale packaging, with estimates placing growth at 26% CAGR for 2011 (Yole Marketing, 2011). WLCSP has lead the way to reduced cost of complex semiconduc- tor devices through simplified packaging and a reduction in the number of touches in the semi- conductor test process. Paradoxically, simplified WLCSP packaging demands have increased the demands on the test cell, including the test system, wafer prober and the interface to the device under test. One of the more significant impacts is the signal performance requirements that were required at final package test are now shifted to the wafer probe environment, where pad-to- pad and ball-to-ball dimensions and toler- ances are much smaller than those at final test and continue to shrink. This is most clear- ly seen in the device contacting requirements. At final test of a packaged device, alignment of the device under test (DUT) to its test socket and contacts is independent of the number of parallel test sites (multi-site test), and each Eliminating the”probe tower” in automated wafer probe systems reduces the size and complexity of the test system, improves test accuracy, but requires more precise mechanical interface tolerances Figure 1 · Comparison of test procedures with, and without, a probe tower.
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Transcript of Probe Testing of Wafer Level Chip Scale Packaging · Probe Testing of Wafer Level Chip Scale...
52 High Frequency Electronics
High Frequency Design
WAFER PROBE TESTING
Probe Testing of Wafer LevelChip Scale Packaging
By John WhittakerTeradyne
Wafer Level ChipScale Packaging(WLCSP) has
enabled smaller and thin-ner semiconductor deviceswith greater functionalityto be used in consumermobile applications suchas smart phones, tabletsand hand held GPS track-
ing devices. There is an accelerating trendtoward wafer level chip scale packaging, withestimates placing growth at 26% CAGR for2011 (Yole Marketing, 2011). WLCSP has leadthe way to reduced cost of complex semiconduc-tor devices through simplified packaging and areduction in the number of touches in the semi-
conductor test process. Paradoxically, simplifiedWLCSP packaging demands have increasedthe demands on the test cell, including the testsystem, wafer prober and the interface to thedevice under test.
One of the more significant impacts is thesignal performance requirements that wererequired at final package test are now shiftedto the wafer probe environment, where pad-to-pad and ball-to-ball dimensions and toler-ances are much smaller than those at finaltest and continue to shrink. This is most clear-ly seen in the device contacting requirements.At final test of a packaged device, alignment ofthe device under test (DUT) to its test socketand contacts is independent of the number ofparallel test sites (multi-site test), and each
Eliminating the”probetower” in automated waferprobe systems reduces thesize and complexity of thetest system, improves test
accuracy, but requiresmore precise mechanical
interface tolerances
Figure 1 · Comparison of test procedures with, and without, a probe tower.
54 High Frequency Electronics
High Frequency Design
WAFER PROBE TESTING
test site has alignment features inthe socket that positions the pack-aged device with respect to the con-tacts. With wafer chip scale packingparallel test sites are no longer phys-ically decoupled because they are allon the common wafer. Planarity andalignment errors become cumulative.
Multi-site test is essential toobtaining optimal test economics.While multi-site probe has long beena solution for testing pure digital andmemory devices, complex analog andmixed-signal SOC devices add com-plexity to test floor managementbecause these devices tend to be oflower volume and a greater variety.This leads to a higher frequency ofreconfiguring the test cell to accom-modate the changing mix of devicetypes. In order to obtain the efficien-cies of multi-site test in the face ofthese challenges it is important tofocus on these essential requirementsof the test cell:
1. Provide for minimal signal pathfrom instrument to DUT.
2. Provide highly accurate andrepeatable planarity alignmentto support the requirements ofmembrane and fine-pitch, high-performance probe technology.
3. Provide for rapid changeoverand setup of probe cards to min-imize down time in high mix,low volume production environ-ments.
It has been demonstrated thattest cells can meet each of theserequirements resulting inchangeover of probe cards, performedby an operator in a production envi-ronment, meeting the required pla-narity, all in a matter of minutes.Let’s consider each of these require-ments.
Signal PathIn the past, wafer probe test inter-
faces have been based on the use of aprobe tower to provide flexible solu-tions to meet low-to-medium perfor-
mance requirements. These solutionsconsist of a probe interface board(PIB) that resides on the tester signalinterface and a probe tower thatextends test signals from the PIBinto the prober to a probe card, whichprovides the needles to make contactwith the wafer. These are lower costsolutions where only the probe cardneeds to be changed over to accom-modate a different device. It alsorequires only reasonable mechanicalaccuracy for positioning the testerinterface to the plane of the wafer.The layer of mechanical decouplingprovided by the probe tower comes atthe price of extending signal pathlength between the tester instrumen-tation to the probe needles andadding interconnects, both of whichcan degrade electrical signal perfor-mance due to impedance discontinu-ities.
Even though there is signaldegradation, many analog signalscan be addressed with calibration orerror de-embedding techniques as isdone with RF (radio frequency) sig-
nals. In comparison, digital signalscan be sensitive to overall round-tripdelay and are impacted by reflectionsat multiple interconnect boundaries.Reflections at high data rates lead tointer-symbol interference and datadependent jitter of signal edges.These effects are much more difficultor impossible to remove and can onlybe controlled by reducing the overallpath length and eliminating inter-connects. As high performance func-tional test moves to the probe envi-ronment and digital speeds continueto increase, the path effects becomean unavoidable obstacle and a keylimiter to signal performance.Towerless solutions minimize theseeffects and come closest to the origi-nal design intent of the tester’s signaldelivery system.
Figure 2 · Close-up photo of con-tacts on a test probe fromMicroprobe Inc.
Figure 3 · Dies are accessed alonga diagonal pattern.
Figure 4 · Summary of planarity requirements for three types of probes.
High Frequency Design
WAFER PROBE TESTING
PlanarityHigh performance function test
wafer probe requires a solution thatovercomes issues of interconnectsand extended signal path lengths. Forhighest performance into the giga-hertz region, membrane probes have
proven to provide the best environ-ment for controlling impedance towithin 10s of µm of the die pad or sol-der ball. Other technologies such aspogo pins, cobra probes or bucklingcolumn probes also can maintainvery short lengths to minimize induc-
tance and achieve best performance.In all cases the z-axis compliance ofthese short probes is limited, requir-ing the probe interface solution tohave very high z-axis accuracy to staywithin the probes compliance range.
Additionally, with increasingmulti-site counts, access of the probesto the dies on the wafer dictates fea-sible probe patterns. It is optimal toarrange the probes such that dies areaccessed along a diagonal pattern(see Fig. 1). While this maximizes theprobe connection access, it spreadsthe test sites over a distance that isincreased by the √2 or 40% than if thesites were arranged in a direct row.However, a direct row arrangementseverely limits probe access to thedie. The z-axis planarity between thewafer (probe chuck) and the probecard must minimize angular z-errorsto accommodate the z-axis compli-ance of the probes themselves. Theprobe card alignment system mustprovide accurate, repeatable align-ment as probe cards are routinelyswapped out. The alignment systemmust assure rapid, consistentchangeover in the production envi-ronment.
It is also essential for the probecard and supporting mechanicalstructure to absorb the forces intro-duced by the increasing probe count.
Figure 5 · Photo of the wafer probe system hardware. Figure 6 · This diagram illustrates the reduction in com-plexity of the new prober system.
58 High Frequency Electronics
High Frequency Design
WAFER PROBE TESTING
If it is insufficient, deflection willoccur when probes are compressedwhen making contact with the wafer.It is important that the supportstructure is both rigid and accurateso that proper contact force is madebetween the probes and the wafer.This force needs to be great enough toobtain the proper scrubbing action tobreak through oxides on the contactsurface. It is also important thatexcess contact force is not required toovercome planarity errors as theexcess force may damage structureson the die beneath the pads or canexcessively deform solder balls.
By minimizing the tolerance loopfrom tester to wafer, z-errors can bemaintained to 0.029 degrees, which isa factor of 2 better than what isrequired by multisite membraneprobe solutions spanning up to 8 dieof 8 × 8 mm, and even better for pogobased solutions.
Rapid ChangeoverIn routine production, downtime
is expensive, and unpredictabledowntime is disruptive. Routinechangeover of probe cards for a dif-ferent device or for maintenance orrepair must be quick to minimizedowntime. Thus, minimizing the tol-erance loop from probe tips to accura-cy alignment features is essential toprovide repeatable changeovers.
To address this, the process ofchanging the probe card should allowthe test system interface to remainconnected and aligned to the prober.A bottom-loading scheme is used tomanipulate the probe card into placeand align using unique alignmentfeatures in the design.
A modified bottom load probe cardchanger can achieve this. The produc-tion floor operator can remove andreplace probe cards in the changer’sloading tray. From there the loadingoperation is completely automated.The time required to place the probecard in the loader and have it pla-narized and locked in place is lessthan 5 minutes.
SummaryIn summary, the cost and perfor-
mance requirements of semiconductordevices used in consumer mobile elec-tronics and other applications demandgreater functional density and lowercost devices. These requirements areaddressed with wafer level chip scalepackaging.This in turn drives the needfor full functional test at probe sincetraditional package and final test iseliminated from the manufacturingprocess.The physical constraints intro-duced by multi-site wafer level chipscale testing has presented challengesto traditional techniques used forinterfacing the test system to thewafer prober. Innovative solutions thatfocus on reducing error sources andsimplify tolerance loops can reliablyand economically meet today’s chal-lenges at the performance levelsrequired to test today’s and tomorrow’scomplex semiconductor devices.
Author InformationJohn Whittaker, Interface Products
Marketing Manager, Global ServicesOrganization at Teradyne. The 20-year
veteran of the ATE industry has abackground in memory and digitaltest, statistical analysis software, andis currently focused on SOC signaldelivery. Mr. Whittaker graduatedfrom Worcester Polytechnic Institutewith a B.S.E.E. Teradyne, Inc., 600Riverpark Drive, North Reading, MA,01864, email: [email protected].
Other contributors to the articleinclude Roger Burns, previouslyMarketing Applications Manager,Teradyne; Dan Watson, MechanicalEngineer, Global Services Organiza-tion, Teradyne. He has created innova-tive mechanical, electrical, and signaldelivery interface solutions for manyof Teradyne’s semiconductor testingproducts; Kirk Pitta, ApplicationsEngineer, Global Services Organi-zation, Test Cell Group at Teradyne.He has worked in design engineering,Japan field applications and factoryapplications roles for the Test CellGroup. Mr. Pitta holds a B.S. inMechanical Engineering and a M.S. inMechanical Engineering fromNortheastern University.
Figure 7 · Diagram comparing the old and new probe systems.
