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EECS240 – Spring 2013

Lecture 2: CMOS Technology and Passive Devices

Lingkai Kong EECS

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Today’s Lecture •  EE240 CMOS Technology

•  Passive devices •  Motivation •  Resistors •  Capacitors •  (Inductors)

•  Next time: MOS transistor modeling

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EE240 Process •  45nm 1P9M CMOS

•  Minimum channel length: 50nm •  1 level of polysilicon •  9 levels of metal (Cu) •  1V supply •  Models for this process not “real”

•  Other processes you might see •  Shorter channel length (28nm / 1V, 20nm / 1V) •  Bipolar, SiGe HBT •  SOI •  FinFET

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Process Options •  Available for many processes

•  Add features to “baseline process”

•  E.g. •  Silicide block option •  “High voltage” devices (2.5V & 3.3V, >10V) •  Low VTH devices •  Capacitor option (2 level poly, MIM) •  …

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CMOS Cross Section

Metal

Poly

p- substrate

n- well

p+ diffusion

n+ diffusion

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Dimensions

700mm

1.4nm³ 90nm

0.6mm

50nm

Drawing is not to scale!"

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CMOS Process Overview

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Why Talk About Passives?

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Resistors

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What are the Options in CMOS? Metal

Poly

p- substrate

n- well

p+ diffusion

n+ diffusion

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Resistors: Options •  Poly resistors •  Diffusion resistors •  N-Well resistors •  Metal resistors •  Transistor as resistors •  …

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N-Well Resistor

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N-Well Resistor? •  How much does N-well resistor vary?

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Silicide Block Option

•  Non-silicided layers have significantly larger sheet resistance

Type Silicided Non-Silicided N+ Poly ~5Ω ~100Ω P+ Poly ~5Ω ~180Ω

N+ Diffusion ~5Ω ~50Ω P+ Diffusion ~5Ω ~100Ω

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Poly Resistor

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Diffusion Resistor

•  Applied voltage modulates depletion width (cross-section of conductive channel)

•  Well acts as a shield

p- substrate

n- well

p+ diffusion

n+ diffusion

R

V1 V2 VB

( ) ( ) ⎥⎦

⎤⎢⎣

⎡⎟⎠

⎞⎜⎝

⎛ −+

+−+−+≈

−=

BCCo

Co VVVBVVVTTR

IVVR

2251 21

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Temperature and Voltage Coefficient

Layer R/☐ [Ω/☐] TC [ppm/oC] @ T = 25 oC

VC [ppm/V] BC [ppm/V]

N+ poly P+ poly N+ diffusion P+ diffusion N-well

100 180

50 100

1000

-800 200

1500 1600

-1500

50 50

500 500

20,000

50 50

-500 -500

30,000

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Compensation

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Resistors: Specs •  Resistivity – sheet resistance •  Linearity (Voltage Dependency) •  Temperature Coefficient •  Parasitic •  Variability and Matching •  Stress •  Electromigration (EM) •  …

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Systematic Variations from Layout •  Example:

•  Use unit element instead:

R

2R

?

2R

R

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Better Unit Element

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Common Centroid and Dummies Example: R1 : R2 = 1 : 2" gradient"

R1"

0.5 * R2 - ΔR"

0.5 * R2 + ΔR"

Dummy à"

Dummy à"

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Resistor Layout (cont.) Serpentine layout for large values:"

Better layout (mitigates offset due to thermoelectric effects):"

See Hastings, “The art of analog layout,” Prentice Hall, 2001."

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MOSFETs as Resistors

•  Triode region (“square law”):

•  Small signal resistance:

•  Voltage coefficient:

DSTHGSDSC VVVV

RR

V−−

=∂

∂=

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DSTHGSDSDS

THGSoxD VVVVVVVLWCI >−⎟

⎠

⎞⎜⎝

⎛ −−= for 2

µ

( )

( )DSTHGS

THGSox

DSTHGSoxDS

D

VVVVV

LWC

R

VVVLWC

VI

R

>>−−

≈

−−=∂

∂=

for 1

1

µ

µ

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MOS Resistors Example: R = 1 MΩ •  Large R-values realizable in

small area •  Very large voltage

coefficient •  Applications:

•  MOSFET-C filters: (linearization) Ref: Tsividis et al, “Continuous-Time MOSFET-C Filters in VLSI,” JSSC, pp. 15-30, Feb. 1986.

•  Biasing: (>1GΩ) Ref: Geen et al, “Single-Chip Surface-Micromachined Integrated Gyroscope with 50o/hour Root Allen Variance,” ISSCC, pp. 426-7, Feb. 2002.

( )

( )

1

0

2

V5.0V21

1

2001

V2MΩ1VµA100

1

1

1

−

=

==

−=

=××

=

−=

−≈

THGSVVC

THGSox

THGSox

VVV

VVRCLW

VVLWC

R

DS

µ

µ

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Resistor Summary •  No or limited support in standard CMOS

•  Costly: large area (compared to FETs) •  Nonidealities:

•  Large run-to-run variations •  Temperature coefficient •  Voltage coefficients (nonlinear)

•  Avoid them when you can •  Especially in critical areas, e.g.

•  Amplifier feedback networks •  Electronic filters •  A/D converters

•  We will get back to this point

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Capacitors

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Capacitors •  Simplest capacitor:

substrate"

•  What’s the problem with this?

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Capacitors •  “Improved” capacitor:

substrate"

•  Is this only 1 capacitor?

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Capacitor Options

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Capacitor Options Type C [aF/µm2] VC [ppm/V] TC [ppm/

oC]

Gate 10,000 Huge Big

Poly-poly (option)

1000 10 25

Metal-metal 50 20 30

Metal-substrate 30

Metal-poly 50

Poly-substrate 120

Junction caps ~ 1000 Big Big

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MOS Capacitor

•  High non-linearity, temperature coefficient

•  But, still useful in many applications, e.g.: •  (Miller)

compensation capacitor

•  Bypass capacitor (supply, bias)

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Capacitor Layout

•  Unit elements"•  Shields:"

•  Etching"•  Fringing fields"

•  “Common-centroid”"•  Wiring and interconnect

parasitics"

Ref.: Y. Tsividis, “Mixed Analog-Digital VLSI Design and Technology,” McGraw-Hill, 1996."

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MIM Capacitors •  Some processes have MIM cap as add-on

option •  Separation between metals is much thinner •  Higher density

•  Used to be fairly popular •  But not as popular now that have many metal layers

anyways

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Capacitor Geometries •  Horizontal parallel plate •  Vertical parallel plate •  Combinations

Ref: R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors,” JSSC March 2002, pp. 384-393.

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“MOM” Capacitors

•  Metal-Oxide-Metal capacitor. Free with modern CMOS. •  Use lateral flux (~Lmin) and multiple metal layers to realize

high capacitance values

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MOM Capacitor Cross Section

•  Use a wall of metal and vias to realize high density

•  More layers – higher density •  May want to chop off lower

layers to reduce Cbot

•  Reasonably good matching and accuracy

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Distributed Effects •  Can model IC resistors

as distributed RC circuits.

•  Could use transmission line analysis to find equivalent 2-port parameters.

•  Inductance negligible for small IC structures up to ~10GHz.

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Effective Resistance

•  High frequency resistance depends on W, e.g.: •  W=1µ 10kΩ resistor works fine at 1GHz •  W=5µ 10kΩ resistor drops to 5kΩ at 1 GHz

•  May need distributed model for accurate freq response

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Capacitor Q

•  Current density drops as you go farther from contact edge…

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Double Contact Strucutre

•  If contact on both edges, •  R drops 4X •  Can be a good idea even if not hitting distributed

effects

Inductors

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Passives: Inductors

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What About Inductors?

•  Mostly not used in analog/mixed-signal design •  Usually too big •  More of a pain to model than R’s and C’s •  But they do occasionally get used

•  Example inductor app.: shunt peaking •  Can boost bandwidth by up to 85%! •  Q not that important (L in series with R) •  But frequency response may not be flat

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Spiral Inductors

•  Used widely in RF circuits for small L (~1-10nH).

•  Use top metal for Q and high self resonance frequencies. •  Very good matching and accuracy – if you model

them right