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EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 7: Timing Variability

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Outline

Last lectureCapacitance models

Delay models

Standard cells

This lectureStatic timing

Variability in design

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F. Static Timing

4C. Visweswariah, ICCAD’07 tutorial

Setup Timing

LF1 LF2 CFLF3 Comb.

Comb.

Comb.

early clock

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5

Hold Tests

LF1 LF2 CFLF3 Comb.

Comb.

Comb.

early data

late clock

C. Visweswariah, ICCAD’07 tutorial

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Static Timing Analysis

clk

Combinationallogic

clk

Combinationallogic

clk

Combinationallogic

original circuit

extracted block

Combinationallogic

K. Keutzer, EE244

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Each Combinational Block

Arrival time in green A

C

B

f

2

2

2

1

0

1

0

.20.20

.20

.10

X

YZ

W

.15

.05

.05

.05

Interconnect delay in red

Gate delay in blue

What’s the right mathematical object to use to represent this physical object?

K. Keutzer, EE244

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Problem formulation - 1

C

B

f

X

Y

W

0

.05.1

1

.2

0

0

1

A

.15.20

.20

A

C

B

f

2

2

2

1

0

1

0

.20.20

.20

.10

X

YZ

W

.15

.05

.05

.05

12

2

2

Z

Use a labeled directed graph

G = <V,E>

Vertices represent gates, primary inputs and primary outputs

Edges represent wires

Labels represent delays

Now what do we do with this?

K. Keutzer, EE244

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Problem formulation - Arrival Time

Arrival time A(v) for a node v is time when signal arrives at node v

uu

A( ) max (A(u) d )

FI( )

X

Y

A(Z)

Z

x zd

Y zd

A(X)

A(Y)

where d is delay from to andu u, {X,Y}, {Z}. FI(υ) = =

K. Keutzer, EE244

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Static Timing Analysis

Computing critical (longest) and shortest path delayLongest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 1966]

Used in most ASIC designs today

LimitationsFalse paths

Simultaneous arrival times

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False Paths

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Signal Arrival Times

NAND gate:

1

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Signal Arrival Times

NAND gate:

1

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Simultaneous Arrival Times

NAND gate:

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Impact of Arrival Times

A

B

Delay

0 tB - tA

A arrives early B arrives early

Up to 25%

G. Design Variability

Sources and Impact on Design

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Roadmap Acknowledges VariabilityInternational Technology Roadmap for Semiconductors2005 data

Node year 2007 2010 2013 2016 2019

DRAM ½ pitch [nm] 65 45 32 22 16

Total gate CD 3 [nm] 2.6 1.9 1.4 0.9 0.6

Lithography 3 [nm] 2 1.4 1 0.7 0.5

LER 3 [nm] 2 1.4 1 0.7 0.5

http://www.itrs.net/Common/2005ITRS/Home2005.htm

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Chip Performance Varies

Variations: D2D

NMOS VTh*

PMOSVTh

*

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Chip Performance Varies

Variations: D2D, W2W, L2L

Too slow

Fast, but power/leakage

too high

NMOS VTh*

PMOSVTh

*

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Variability Classification

Nature of process variabilityWithin-die (WID), Die-to-die (D2D), Wafer-to-wafer (W2W), Lot-to-lot (L2L)

Systematic vs. random

Correlated vs. non-correlated

Spatial variability/correlationDevice parameters (CD, tox, …)

Supply voltage, temperature

Temporal variability/correlationWithin-node scaling, Electromigration, Hot-electron effect, NBTI, self-heating, temperature, SOI history effect, supply voltage, crosstalk [Bernstein, IBM J. R&D, July/Sept 2006]

Known vs. unknown

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Sources of Variability

TechnologyFront-end (Devices)

Systematic and random variations in Ion, Ioff, C, …

Back-end (Interconnect)

Systematic and random variations in R, C

EnvironmentSupply (IR drop, noise)

Temperature

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Spatial Variability

Fab to fab

Deployed environment

Lot to lot

106 103 100 10-3 10-6 10-9

Across wafer

Across reticle

Across chip

Across blockAfter RohrerISSCC’06 tutorial

Temperature

Metal polishing

Transistor Ion, Ioff

Line-edge roughness

Dopant fluctuation

Film thickness

Global Local

Spatial range [m]

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Temporal Variability

Tech. node scaling

Within-node scaling

Electromigration

1012 103 100 10-3 10-6 10-12

NBTI

Hot carrier effect

Tooling changes

Lot-to-lotAfter RohrerISSCC’06 tutorial

Temperature

Data stream

SOI history effect

Self heating

Supply noise

Coupling

Technology Environment

Temporal range [s]10-9109 106

Charge

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Systematic vs. Random Variations

SystematicA systematic pattern can be traced down to lot-to-lot, wafer-to-wafer, within reticle, within die, from layout to layout,…

Within-die: usually spatially correlated

RandomRandom mismatch (dopant fluctuations, line edge roughness,…)

Things that are systematic, but e.g. change with a very short time constant (for us to do anything about it). Or we don’t unedrstand it well enough to model it as systematic. Or we don’t know it in advance (“How random is a coin toss?”).

Unknown

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Systematic and Random Device Variations

Parameter Random Systematic

Channel Dopant Concentration Nch

Affects ϭVT [1] Non uniformity in the process of

dopant implantation, dosage, diffusion

Gate Oxide Thickness Tox

Si/SiO2 & SiO2/Poly-Si interface roughness[2]

Non uniformity in the process of oxide growth

Threshold Voltage VT

(non Nch related)Random anneal temperature and strain effects

Non-uniform annealing temperature[5]

(metal coverage over gate)

Biaxial strain

Mobility μ Random strain distributions Systematic variation of strain in the Si due to STI, S/D area, contacts, gate density, etc

Gate Length L Line edge roughness (LER)[3] Lithography and etching:

Proximity effects, orientation[4]

[1] D. Frank et al, VLSI Symposium, Jun. 1999 .[2] A. Asenov et al, IEEE Trans on Electron Devices, Jan. 2002.[3] P. Oldiges et al, SISPAD 2000, Sept. 2000.[4] M. Orshansky et al, IEEE Trans on CAD, May 2002.[5] Tuinhout et al, IEDM, Dec 1996

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Corners

TypicalSlow Fast

Within wafer

Within die

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Corner Models

Margin: Minimum distance from failure

TT

FF

SS

SF

FS

NMOS VTh*

PMOSVTh

*

Design

Margin

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Dealing with Systematic Variations

Model-to-hardware correlation classifies unknown

Systematic effect

Improve process Tighten a design rule

Model/Design-inLimited options Density loss

Extraction/Compact modeling/Design techniques

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Systematic (?) Temporal Variability

Metal 3 resistance over 3 months

P. Habitz, DAC’06 tutorial