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UNIVERSITY OF CALIFORNIA College of Engineering

Department of Electrical Engineering and Computer Sciences

E. Alon Final EECS 240 Wednesday, May 9, 2012 SPRING 2012 You should write your results on the exam sheets only. Partial credit will be given only if you show your work and reasoning clearly. Throughout the exam, you can ignore the ro of any transistors and all capacitors except those explicitly drawn in the diagrams unless the problem states otherwise. Name: _________________________________________ SID: _________________________________________

Problem 1 ______/ 16 Problem 2 ______/ 18 Problem 3 ______/ 24 Problem 4 ______/ 12 Total ______/ 70

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Problem 1 (16 points) Source-Degenerated Amplifier In this problem we will be examining the source-degenerated amplifier shown below.

Vi+

RL

Ib/2

RLVo+Vo-

Vi-M1 M2

VDD VDD

CLCLRS

Ib/2

a) (4 pts) Assume that this amplifier must achieve a given target DC gain Av and bandwidth ωbw. As a function of Av, ωbw, CL, RS, and the V* of the input transistors (M1 and M2), what is the required Ib for this amplifier?

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b) (8 pts) What is the total variance (σ2) of the differential voltage noise at the output of this amplifier? You should provide your answer in terms of k, T, CL, γ, gm (the transconductance of the input devices), RL, and RS.

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c) (4 pts) Now let’s consider the linearity of this source-degenerated amplifier. We will assume a simple piecewise linear model where the gm of a typical differential pair of transistors (i.e., with no source generation) remains constant until a differential input of +/-V* is applied, after which the tail bias current is fully steered to one side or the other of the diff. pair. Using this model, what is the maximum input voltage one can apply before fully steering the bias current in the source degenerated amplifier (repeated below for convenience)?

Vi+

RL

Ib/2

RLVo+Vo-

Vi-M1 M2

VDD VDD

RS

Ib/2

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d) (BONUS) One may argue that the behavior of this source-degenerated amplifier with the input transistors biased at a given V* is very similar (or even equivalent) to a standard amplifier with the input transistors biased at an appropriately higher V*. Assuming that one were to make the linearity, gain, and bandwidth of these two types of amplifiers the same, what might cause you choose the source-degenerated amplifier over the standard amplifier with a larger V*?

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Problem 2 (18 points) Offset Cancellation and Link Design

a) (6 pts) For this problem, we will assume that the offset of the amplifier shown below is set only by the threshold mismatch of M1 and M2, and that we would like to cancel up to 3σ of offset using Icancel. (Note that the figure shows Icancel on only one side of the amplifier, but you can assume that there is a similar Icancel on the other side to cancel offsets in either direction.) Further assuming that we will size the input devices to maintain a constant V*, for a given Itail, what is the total maximum power consumption of the amplifier? You can assume that the transistors have a length of Lmin, and that at the given V*, their current density is Inorm/Wnorm. You should provide your answer in terms of VDD, Itail, V*, AVth, Inorm, Wnorm, and Lmin.

Vi+

RL

Itail

RLVo+Vo-

Vi-M1 M2

VDD VDD

Icancel

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b) (4 pts) Now let’s use some actual numbers to put the benefits of the offset-cancelled design into perspective. Specifically, let’s assume that V* = 200mV, AVth = 4mV·µm, Inorm = 50µA, Wnorm = 1µm, and Lmin = 100nm. Under these conditions and assuming that a resistively-loaded amplifier without offset cancellation should achieve a gain Av of 2, a bandwidth ωbw of 2π·2GHz, and a 3σ input-referred offset of less than 6mV, how large of a load capacitance CL would the amplifier have to be driving in order for its power consumption to not be limited by the offset requirement (rather than by driving the load capacitance)?

clk

do+-+

-

RT

Channeldidi_b

VDD

VDD VDD

Av VRX

ITX

RT

VDD

VTX+-

+-

RT RT

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c) (8 pts) Now let’s look at optimizing the simple link shown above. For this problem we will ignore all thermal noise, and we will assume that the channel is ideal, that the receiver’s amplifier is a resistively-loaded differential pair with a fixed V*, no offset, and a bandwidth of ωbw that is high enough to guarantee complete settling (i.e., no ISI). Furthermore, we will assume that the comparator presents a capacitance of Ccomp to each of its inputs, and that the comparator must receive a differential input signal of at least Vmin (i.e., the differential amplitude of VRX must be > Vmin) in order to meet our BER requirements. Under these conditions and ignoring the power consumption of the comparator itself, what is the optimum ITX that minimizes the total power consumption of the link (i.e., TX power plus RX power)? You should provide your answer in terms of ωbw, Vmin, V*, Ccomp, and RT.

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Problem 3 (24 points) Comparator Design In this problem we will be looking at the modified CML latch shown below, where c1, c2, and c3 are non-overlapping clocks each with a duty cycle of 1/3 (i.e., first c1 is high, then c2, then c3). All of the devices have minimum channel length; the widths of M1, M2, M3, and M4 (which are all identical) are chosen to achieve a fixed V* of 200mV. You can assume that M5 and M6 operate as ideal switches. M7 also operates as a switch, but has a finite on-resistance Ron7.

Vi+

RL

Ib

c2 c3

RLVo+Vo-

Vi-M1 M2 M3 M4

M5 M6

VDD VDD

c1

M7

Unless otherwise noted, you should use the following design and technology parameters:

• For M1, M2, M3, and M4, ωT ≈ gm/CGS = 2π·70GHz, γ = CDD/CGS = 1 • For M7, Ron,W = 2kΩ·µm, CDD,W = CSS,W = 1.5fF/µm

a) (6 pts) Including all of the capacitive parasitics from the drains of M1-M4, the

source/drain of M7, and the gates of M3/M4, and assuming that the gain from Vi to Vo when c2 is high (i.e., M5 is on) is Av, and that M7 is sized so that its on-resistance is Ns times smaller than RL, what is the total single-ended capacitance on each of Vo+/Vo-? You should provide your answer in terms of Av, Ron,W, Ns, CDD,W, ωT, γ, and gm,M1.

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b) (8 pts) Assuming that Av = 4, Ns = 2, and given your answer to part a), what is the time constant τ1 of the output network when c1 is high (i.e., M7 is on)? Similarly, what is the time constant τ2 when c2 is high? Finally, what is the regeneration time constant when c3 is high? You should provide numerical values for all three of these time constants.

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c) (6 pts) Under the same conditions as part b) and with the comparator operating at 13.33GHz (i.e., each clock is high for 25ps), and assuming that in the previous cycle the output of the comparator was a “1” (i.e., Vo,diff is at its maximum positive value), what is the remaining differential voltage at Vo due to this previous decision right before c3 goes high (i.e., right before regeneration begins)?

d) (4 pts) Under the same operating conditions as c), and assuming that a differential

input step Vi = 10mV is applied to the comparator right before c1 goes high, what

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is the differential output voltage Vo,diff due to this input step right before c3 goes high?

Problem 4 (12 points) Miscellaneous

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a) (6 pts) One of your colleagues has built the bias circuit shown below, but complains to you that the circuit does not seem to be functioning correctly – even after they added a start-up circuit. What behavior is your colleague most likely observing, and how can the circuit be fixed? (Hint: what is supposed to be setting the bias current in this circuit?)

Av

Rs

1 1

+ -­‐

10011

Iref

b) (6 pts) Assuming that gm,M1 = gm,M2 = 1mS, RL = 5kΩ, CL = 500fF, Cbig >> CL, and

that the frequency of the clock driving the (ideal) switches is 1GHz, what are the DC common-mode and differential-mode gains of the circuit shown below?

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Vi+

RL RL

Vo+ Vo-

Vi-M1 M2

VDD VDD

CLCL

clk

clk_b

CbigCbig