1

EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 9: SRAM Design

2

Announcements

Homework 2 posted this week

Quiz #1 on Monday

2

3

Outline

Last lectureFinished variability

This lectureSRAM operation

Part 3: SRAM

A. Basics

3

5

SRAM Topics

A. Basics and trends

B. Static margins

C. Dynamic margins

D. Assist techniques

E. Periphery, redundancy and error correction

F. Scaling options

6

700 600 500 400 300 200 10010090 80 70 60 50 40 30

0.1

1

10

ITRS Single Cell Reported Individual Cell Reported Cell in Array

SR

AM

Cel

l Siz

e (u

m2 )

Technology Node (nm)

SRAM Scaling Trends

Individual SRAM cell area able to track ITRS guideline

Array area deviates from ITRS guideline at 90nm

Memory design no longer sits on the 0.5x area scaling trend!

300 200 100 90 80 70 60 50 40 30

0.1

1

10

100

ITRS Effective Cell Reported Effective Cell

SR

AM

Cel

l Siz

e (

um

2)

Technology Node (nm)

0.5x effective cell area scaling difficult

4

7

6-T SRAM Cell

• Improve CD control by unidirectional poly• Relax critical layer patterning requirements• Optimizing design rules is key

8

SRAM Cell Design Trends

• Key enabling technology:

• Impact:

Cell in 90nm(1m2)

Cell in 32nm(0.171m2)

IEDM

’

02

VDD

GND

WL

BL BLB

5

9

More SRAM Trends

0.15m2 cell in 32nm from TSMC (IEDM’07)

0.1m2 cell in 22nm from IBM (IEDM’08)

10

SRAM Cell Trends (22nm)

0.092m2 cell in 22nm from Intel (IDF’09)

0.346m2 cell in 45nm from Intel (IEDM’07)

A little analysis using a ruler:• Aspect ratio 2.9• Height ~178nm, Width ~518nm• Gate ~ 45nm (Lg is smaller)

6

11

22nm SRAM

FinFET cell design

E. Karl, ISSCC’12

SRAM

B. Static Retention Margin

7

13

SRAM Cell/Array

Hold (retention) stability

Read stability

Write stability

Read current (access time)

WL

BL

VDD

M5 M6

M4

M1

M2

M3

BL

QQ

Access Transistor

Pull down Pull up

14

WL

BL

AXL

NPD

Access

‘1’ ‘0’

Load

AXR

NRNL

PRPL

BL

VDD

Data RetentionLeakage

Scaling trend:

Increased gate leakage + degraded ION/IOFF ratio

Lower VDD during standby

PMOS load devices must compensate for leakage

SRAM Design – Hold (Retention) Stability

8

15

Retention Stability

Would like to reduce supply in standby

WL

BL

AXL‘1’ ‘0’

AXR

NRNL

PRPL

BL

VDD

160 50 100 150 200 250 300

0

50

100

150

200

250

300

Simulated DRV of 1500 SRAM cells (mV)

His

togr

am o

f cel

l #

Monte-Carlo Simulation of DRV Distribution

Qin, ISQED’04

9

17

Vmin Distribution

Alternative to static margin characterization

Digital test under supply sweep

M Ball, IEDM’06

SRAM

C. Static Read/Write Margins

10

19H. Pilo, IEDM 2006

20

Read Stability – Static Noise Margin (SNM)

• Read SNM is the contention between the two sides of the cell under read stress.

AXR

NR

PR

VL VR

VDD

0 0.5 10

0.5

1

VL (V)

VR

(V

)

90nm simulation

Read SNM

E. Seevinck, JSSC 1987WLC

Vox

Th

1 Due to RDF

11

21

Read SNM - Measurements

WL

BL

AXL

NPD

Access

‘1’V>0

Load

AXR

NRNL

PRPL

BL

VDD

Read margin vs. retention margin

Bhavnagarwala, IEDM’05

Retention fluctuations

22

Read Stability – N-Curve

• A, B, and C correspond to the two stable points A and C and the meta-stable point B of the SNM curve

• When points A and B coincide, the cell is at the edge of stability and a destructive read can occur

Grossar, JSSC’06

12

23H. Pilo, IEDM 2006

24

Write Stability – Write Noise Margin (WNM)

• Writeability is becoming harder with scaling

• Optimizing read stability and writeability at the same time is difficult

AXR

NR

PR

VL VR

VDD

A. Bhavnagarwala, IEDM 2005