EE5342 – Semiconductor Device

Modeling and Characterization

Lecture 25April 19, 2010

Professor Ronald L. Carterronc@uta.edu

http://www.uta.edu/ronc/

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MOSFET equivalentcircuit elements

OxOxOxgdOxgs 'WLCC ,C31

C ,C32

C

Fig 10.51*

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n-channel enh.circuit model

G

D

B

SCgs

Cgd

Cgb

CbsCbd

RD

RG

RB

RB

RDS

IdrainDSS DSD

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MOS small-signal equivalent circuitFig 10.52*

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MOSFET circuitparameters

region ohmic ,VL

'CWg

saturation ,VVL

'CWg

V

Ig

cetancTranscondu

DSOxn

mL

TGSOxn

ms

VGS

Dm

DS

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MOSFET circuitparameters (cont)

ohmic ,VVVL

'CWg

saturation ,0g

VI

g

econductanc drain or Output

DSTGSOxn

dL

ds

VDS

Dd

GS

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Substrate bias effect on VT (body-effect)

pSBpOx

aSiSBT

SBTTa

SBpmaxd,

Ox

maxd,apFBST

T

2V2'C

Nq20VV

VVV so , qN

V22x

where , 'C

xNq2VVV

Source to relative be ncalculatio V Letting

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Body effect dataFig 9.9**

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Fully biased n-channel VT calc

0V ,

qN

VV22x

,xNqQ' ,0Nn

lnV

VV'C

'Q2VVV

VV :substratep

a

sBpmaxd,

maxd,amaxd,a

itp

FBOx

max,dpFBsT

Tthreshold at ,G

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Values for ms

with silicon gate

i

dt

g

d

Ct

d

CtSi

gSims

i

at

g2i

aCt

2i

aCtSiSims

nN

lnVq2

E

NN

lnV :Note

NN

lnVq

E :Si-n to poly p

nN

lnVq2

E

n

NNlnV :Note

n

NNlnV :Si-p to poly n

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Q’d,max and xd,max forbiased MOS capacitor

Fig 8.11**

xd

,max (

mic

ron

s)

|Q’ d

,max|/

q (

cm-2

)

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I-V relation for n-MOS

2TGSOxn

sat,D

sat,DSDS

Lys,sat,DS

sat,DSTGDS

2DSDSTG

OxnD

VVLW

2'C

I

VV for const is

curr. channel that assume

0n' ,V At

physical.-non is result

,VVVV

for Note .VVVV2LW

2'C

I

ID

VDSVDS,sat

ID,sat

ohmic

non-physical

saturated

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MOS channel-length modulationFig 11.5*

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Analysis of channellength modulation

DS2

TGSOxn

satD

satDSDSDSsatDSp

DSsatDSpa

Si

DD

V1VVLW

2C

I

VVV , V2

VV2qN2

L

ILL

LI so ,modulation length

channel the change DR the Assume

'

'

,

,,

,

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Channel length mod-ulated drain charFig 11.6*

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Associating theoutput conductance

ID

VDSVDS,sat

sat,D

DS

sat,Dsat,ds

VDS

Dd

DS2

TGSOxn

sat,D

I

V1

Ig

VI

g

V1VVLW

2'C

I

GS

sat,dsg

slopeID,sat

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MOSFET circuitparameters

region ohmic ,VL

'CWg

saturation ,VVL

'CWg

V

Ig

cetancTranscondu

DSOxn

mL

TGSOxn

ms

VGS

Dm

DS

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Estimating LAMBDA

0V,

qN

VV22x

,V

x

x1

VL

L1

is of tioninterpreta The

V1VVLW

2'C

I

SBa

SBDSp

maxd,

DS

max,d

max,dDS

DS2

TGSOxn

sat,D

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e-e- e- e- e- + + + + + + + + + +

+ +

n-channel enhancementMOSFET in ohmic region

0< VT< VG

VB < 0

EOx,x> 0

Acceptors

Depl Reg

VS = 0 0< VD< VDS,sat

n+ n+

p-substrate

Channel

e- channel ele + implant ion

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Subthreshold conduction• Below O.S.I., when the total band-

bending < 2|p|, the weakly inverted channel conducts by diffusion like a BJT.

• Since VGS>VDS, and below OSI, then Na>nS >nD, and electr diffuse S --> D

t

DS

t

GSsubthresh,D V

Vexp1

VV

expI

Electron concentration at Source

Concentration gradient driving diffusion

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Subthreshold current data

Figure 11.4*

Figure 10.1**

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Mobility variationdue to Edepl

Figures 11.7,8,9*

31

0

eff0eff E

E

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Velocity saturationeffects

L2v

f

vWCg

E as vv So

v

E1

vv limit" speed"

satT

satOxsat,m

sat

212

sat

eff

eff

thsat

Figure 11.10*

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SPICE mosfet Model Instance CARM*, Ch. 4, p. 290M MOSFET

General Form

M<name> <drain node> <gate node> <source node>+ <bulk/substrate node> <model name>+ [L=<value>] [W=<value>]+ [AD=<value>] [AS=<value>]+ [PD=<value>] [PS=<value>]+ [NRD=<value>] [NRS=<value>]+ [NRG=<value>] [NRB=<value>]+ [M=<value>]

Examples

M1 14 2 13 0 PNOM L=25u W=12uM13 15 3 0 0 PSTRONGM16 17 3 0 0 PSTRONG M=2M28 0 2 100 100 NWEAK L=33u W=12u+ AD=288p AS=288p PD=60u PS=60u NRD=14 NRS=24 NRG=10

L = Ch. L. [m]W = Ch. W. [m]AD = Drain A [m2]AS = Source A[m2]NRD, NRS = D and S diff in squares

M = device multiplier

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CARM*, Ch. 4, p. 99Model Forms

.MODEL <model name> NMOS [model parameters]

.MODEL <model name> PMOS [model parameters]

As shown in Figure 11, the MOSFET is modeled as an in tr insic MOSFET with ohmic resistances in series with the drain , source, gate, and bulk (substrate). There is also a shunt resistance (RDS) in parallel with the drain-source channel.

[L=<value>] [W=<value>] cannot be used in conjunction with Monte Carlo analysis .

The simulator provides four MOSFET device models, which differ in the formulation of the I-V characteristic. The LEVEL parameter selects between di fferent models :

LEVEL=1 is the Shichman-Hodges model (see reference [1])LEVEL=2 is a geometry-based, analytic model (see reference [2])LEVEL=3 is a semi-empirical, short-channel model (see reference [2])LEVEL=4 is the BSIM model (see reference [3])LEVEL=5 is the BSIM3 model (see reference [7] Version 1.0)LEVEL=6 is the BSIM3 model (see reference [7] Version 2.0)

L and W are the channel length and width, and are decreased to get the effective channel length and width. L and W can be specified in the device, model, or .OPTIONS statements. The value in the device statement supersedes the va lue in the model sta tement, which supersedes the value in the .OPTIONS statement.

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SPICE mosfet model levels• Level 1 is the Schichman-Hodges

model• Level 2 is a geometry-based,

analytical model• Level 3 is a semi-empirical, short-

channel model• Level 4 is the BSIM1 model• Level 5 is the BSIM2 model, etc.

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SPICE ParametersLevel 1 - 3 (Static)Par am. Parameter Description Def . Typ. Units

VTO Zero-bias Vthresh 1 1 V

KP Transconductance 2.E-05 3.E-05 A/ V 2̂

GAMMA Body-eff ect par. 0.0 0.35 V 1̂/ 2

PHI Surf ace inversion pot. 0.6 0.65 V

LAMBDA Channel-length mod. 0.0 0.02 1/ V

TOX Thin oxide thickness 1.E-07 1.E-07 m

NSUB Substrate doping 0.0 1.E+15 cm̂ -3

NSS Surf ace state density 0.0 1.E+10 cm̂ -2

LD Lateral diff usion 0.0 8.E-05 m

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Par am. Parameter Description Def . Typ. Units

TPG Type of gate material* 1 1

UO Surf ace mobility 600 700 cm̂ 2/ V-s

I S Bulk j ctn. sat. curr. 1.E-14 1.E-15 A

J S Bulk j ctn. sat. curr. dens. A/ m̂ 2

PB Bulk junction potential 0.8 0.75 V

RD Drain ohmic resistance 0 10 Ohms

RS Source ohmic resistance 0 10 Ohms

RSH S/ D sheet ohmic res. 0 10 Ohms/ sq

SPICE ParametersLevel 1 - 3 (Static)

* 0 = aluminum gate, 1 = silicon gate opposite substrate type, 2 = silicon gate same as substrate.

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SPICE ParametersLevel 1 - 3 (Q & N)Par am. Parameter Description Def . Typ. Units

CJ Zero-bias bulk cap./ A 0 1.E-09 Fd/ m̂ 2

MJ Bulk j ctn. grading coeff . 0.5 0.5

CJ SW Zero-bias perimeter C/ l 0 1.E-09 Fd/ m

MJ SW Per. C grading coeff . 0.5 0.5

FC For.-bias cap. coeff . 0.5 0.5

CGBO Gate-bulk overlap C/ L 0 2.E-10 Fd/ m

CGDO Gate-drain overlap C/ L 0 4.E-11 Fd/ m

CGSO G-S overlap C/ L 0 4.E-11 Fd/ m

AF Flicker-noise exp. 1 1.2

KF Flicker-noise coeff . 0.0 1.E-26

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Level 1 Static Const.For Device EquationsVfb = -TPG*EG/2 -Vt*ln(NSUB/ni)

- q*NSS*TOX/eOxVTO = as given, or

= Vfb + PHI + GAMMA*sqrt(PHI)KP = as given, or = UO*eOx/TOXCAPS are spice pars., technological

constants are lower case

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Level 1 Static Const.For Device Equations = KP*[W/(L-2*LD)] = 2*K, K not spiceGAMMA = as given, or = TOX*sqrt(2*eSi*q*NSUB)/eOx2*phiP = PHI = as given, or = 2*Vt*ln(NSUB/ni)ISD = as given, or = JS*AD

ISS = as given, or = JS*AS

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Level 1 Static Device Equationsvgs < VTH, ids = 0VTH < vds + VTH < vgs, id = KP*[W/(L-2*LD)]*[vgs-VTH-vds/2] *vds*(1 + LAMBDA*vds)VTH < vgs < vds + VTH, id = KP/2*[W/(L-2*LD)]*(vgs - VTH)^2 *(1 + LAMBDA*vds)

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SPICE ParametersLevel 2Par am. Parameter Description Def . Typ. Units

NEFF Total channel chg coeff . 1 5

UCRI T Critical E-fi eld f or mob. 1.E+04 1.E+04 V/ cm

UEXP Expon. coeff . f or mob. 0 0.1

UTRA Transverse fi eld coeff . 0 0.5

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SPICE ParametersLevel 2 & 3Par am. Parameter Description Def . Typ. Units

NFS Surf ace-f ast state dens. 0.0 1.E+10 cm̂ -2

XJ Metallurgical j ctn. depth 0.0 1.E-06 m

VMAX Max. drif t v of carr. 0.0 5.E+04 m/ s

XQC Coeff . of ch. Q share 0.0 0.4

DELTA Width eff . on Vthresh 0.0 1.0

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Level 2 StaticDevice EquationsAccounts for variation of channel

potential for 0 < y < LFor vds < vds,sat = vgs - Vfb - PHI +

2*[1-sqrt(1+2(vgs-Vfb-vbs)/2]

id,ohmic = [/(1-LAMBDA*vds)] *[vgs - Vfb - PHI - vds/2]*vds -2[vds+PHI-vbs)1.5-(PHI-vbs)1.5]/3

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Level 2 StaticDevice Eqs. (cont.)For vds > vds,sat

id = id,sat/(1-LAMBDA*vds)

where id,sat = id,ohmic(vds,sat)

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Level 2 StaticDevice Eqs. (cont.)Mobility variationKP’ = KP*[(esi/eox)*UCRIT*TOX /(vgs-VTH-UTRA*vds)]UEXP

This replaces KP in all other formulae.

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SPICE ParametersLevel 3Par am. Parameter Description Def . Typ. Units

KAPPA Saturation fi eld f actor 0.2 1.0

ETA Stat. f eedbk on Vthresh 0.0 1.0

THETA Mobility modulation 0.0 0.05 1/ V

DELTA Width eff . on Vthresh 0.0 1.0

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References

• CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995.

• M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993.

• **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986.

• *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997