EE 5340 Semiconductor Device Theory Lecture 27 – Spring 2011 Professor Ronald L. Carter...

EE 5340Semiconductor Device TheoryLecture 27 – Spring 2011

Professor Ronald L. [email protected]

http://www.uta.edu/ronc

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2

Fully biased n-MOScapacitor

0y

L

VG

Vsub=VB

EOx,x> 0

Acceptors

Depl Reg

e- e- e- e- e- e- n+

n+

VS VD

p-substrate

Channel if VG > VT

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MOS energy bands atSi surface for n-channel

Fig 8.10**

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Computing the D.R. W and Q at O.S.I.

Ex

Emax

x

aSi

x Nq

dxdE

a

SBpSid qN

VVx

)(22,max

)(2 SBp VVarea

,maxda,maxd xqNQ

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Q’d,max and xd,max forbiased MOS capacitor

Fig 8.11**

xd,max

(mm) )2-

d,max

(cm

q

Q'

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Fully biased n-channel VT calc

0V ,

qN

VV22x

,xNqQ' ,0Nn

lnV

VV'C

'Q2VVV

VV :substratep

a

CBpd,max

d,maxad,maxa

itp

FBOx

,maxdpFBCT

Tthreshold at ,G

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n-channel VT forVC = VB = 0

Fig 10.20*

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Fully biased p-channel VT calc

0V ,

qNVV22

x

,xNqQ' ,0nN

lnV

VV'C

'Q2VVV

VV :substraten

d

BCnd,max

d,maxdd,maxi

dtn

FBOx

,maxdnFBCT

Tthreshold at ,G

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p-channel VT forVC = VB = 0

Fig 10.21*

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n-channel enhancementMOSFET in ohmic region

0< VT< VG

VB < 0

EOx,x> 0

Acceptors

Depl Reg

VS = 0 0< VD<

VDS,sate-e- e- e- e- n+

n+

p-substrate

Channel

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Conductance ofinverted channel• Q’n = - C’Ox(VGC-VT)

• n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2)

• The conductivity sn = (n’s/t) q mn

• G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so

• I = V/R = dV/dR, dR = dL/(n’sqmnW)

WdV VVV'CdLI nTCG

L

0

V

VOx

D

S

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Basic I-V relationfor MOS channel

2TGOxn

satDD

TGsatDSDS

satDSDD

nTGsatDSDS

TGDS2

DSDSTGOxn

D

VVL2CW

II

so VVVV for

,VI by given be I let so

Sat0LyQ' VVVV At

VVV VVVV2L2CW

I

'

.,

,'

,

,

,

,

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I-V relation for n-MOS (ohmic reg)

2TGSOxn

sat,D

sat,DSDS

Lys,sat,DS

sat,DSTGDS

2DSDSTG

OxnD

VVLW

2'C

I

VV for const is

curr. channel that assume

0n' ,V At

physical.-non is result

,VVVV

for Note .VVVV2LW

2'C

I

ID

VDSVDS,sat

ID,sat

ohmic

non-physical

saturated

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Universal draincharacteristic

9ID1

ID

4ID1

ID1

VGS=VT+1V

VGS=VT+2V

VGS=VT+3V

2DS

Oxnsat,D V

LW

2'C

I

VDS

2Oxn1D V1

LW

2'C

I

saturated, VDS>VGS-VTohmic

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Characterizing then-ch MOSFET

VD

IDD

SG B

2TGSOxn

sat,D

TGSDS

TGSDS

VVLW

2'C

I

so , VVV

0V , VV

VGSVT

DI

LW

2'C

slope

Oxn

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Substrate bias effect on VT (body-effect)

pSBpOx

aSiSBT

SBTTa

SBpmaxd,

Ox

maxd,apFBST

T

2V2'C

Nq20VV

VVV so , qN

V22x

where , 'C

xNq2VVV

Source to relative be ncalculatio V Letting

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Body effect dataFig 9.9**

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Low field ohmiccharacteristics

DSVVVGS

D

OxnDSTGS

DSTGSOxnD

TGDS

2DSDSTGS

OxnD

VLW

KPdVdI

'C KP , VVVLW

KP

VVVLW

'CI

that so ,VVV

let e,Furthermor region. ohmic for

, VVVV2LW

2'C

I

TGDS

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MOSFET circuitparameters

region ohmic ,VVL

'CWg

saturation ,VL

'CWg

VI

g

cetancTranscondu

TGSOxn

mL

DSOxn

ms

VGS

Dm

DS

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MOSFET circuitparameters (cont)

ohmic ,VVVL

'CWg

saturation ,0g

VI

g

econductanc drain or Output

DSTGSOxn

dL

ds

VDS

Dd

GS

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OxOxOxgdOxgs 'WLCC ,C31

C ,C32

C

Fig 10.51*

MOSFET equivalentcircuit elements

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MOS small-signal equivalent circuitFig 10.52*

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MOS channel-length modulationFig 11.5*

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Analysis of channellength modulation

DD

sat,DSDSDS

sat,DSp

DSsat,DSpa

Si

ILL

L'I

VVV

V2

VV2qN2

L

mod length the as same the

is change DR the Assume

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Channel length mod-ulated drain charFig 11.6*

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e-e- e- e- e- + + + + + + + + + +

+ +

Implanted n-channel enhance-ment MOSFET (ohmic region)

0< VT< VG

VB < 0

EOx,x> 0

Acceptors

Depl Reg

VS = 0 0< VD<

VDS,sat n+

n+

p-substrate

Channel

e- channel ele + implant ion

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Si & SiO2

AlSi3N4

Si

Al & SiO2

Si3N4

Range

DRP

Ion implantation*

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“Dotted box” approx**

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curve dottedunder area curve dashedunder area

iaiimpl XNdxN 0

'ox

iit

iait

C

xqNΔV so

xand Nget implant to desired, as Vget To

FBTmaxd,i V V then , x xIf

dii

aiiiibeforessss xQQ

NN

NN qN '

impl ,'

Calculating xi and DVT

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aiaiSBppsa

iai

msxdaiaid

a

aiips

ad

NNxqVqN

xqN

xqNxqNQ

N

Nx

qNx

22

,

2

2

2

If xi ~ xd,max

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i

idiath

i

iaiathps

aiaiSBppsaOx

pspOx

iai

Ox

ssmsT

n

xNNV

n

xNNV

NNxqVqNC

C

xqN

C

QV

lnor , ln

21 22'

''

'

Calculating VT

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Implanted VT

Vt per Eq. 9.1.23 in M&K for a MOSFET with an 87-nm-thick gate oxide, Qff/q = 1011 cm-2, N’ = 3.5 X 1011 cm-2, and Na = 2 X 1015 cm-3. Both VS and VB = Figure 9.8 (p. 441)

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Substrate bias effect on VT (body-effect)

pSBpOx

aSiSBT

SBTTa

SBpmaxd,

Ox

maxd,apFBST

T

2V2'C

Nq20VV

VVV so , qN

V22x

where , 'C

xNq2VVV

Source to relative be ncalculatio V Letting

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Subthreshold conduction• Below O.S.I., when the total band-

bending < 2|fp|, the weakly inverted channel conducts by diffusion like a BJT.

• Since VGS>VDS, and below OSI, then Na>nS

>nD, and electr diffuse S --> D

t

DS

t

GSsubthresh,D V

Vexp1

VV

expI

Electron concentration at Source

Concentration gradient driving diffusion

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M&K Fig.9.10 (p.443)

Band diagram along the channel region of an n-channel MOSFET under bias, indicating that the barrier qΦB at the source depends on the gate voltage.

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M&K Fig. 9.11 (p.444)

Measured subthreshold characteristics of an MOS transistor with a 1.2 μm channel length. The inverse slope of the straight-line portion of this semilogarithmic plot is called the drain-current subthreshold slope S (measured in mV/decade of drain current).

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Velocity saturationeffects

L2v

f

vWCg

E as vv So

v

E1

vv limit" speed"

satT

satOxsat,m

sat

212

sat

eff

eff

thsat

Figure 11.10*

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References

* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.

**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986

EE 5340 Semiconductor Device Theory Lecture 27 – Spring 2011 Professor Ronald L. Carter...

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