EE241 - Spring 2000bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s00/LECTURES/...EE241 1 UC...

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UC Berkeley EE241 B. Nikoli c

EE241 - Spring 2000Advanced Digital Integrated Circuits

Lecture 23

Sequential LogicLatches and Flip-Flops


Latch versus Flip-Flop

l Latchstores data when clock is low

D

Clk

Q D

Clk

Q

l Flip-Flopstores data when clock rises

Clk Clk

D D

Q Q

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Latches

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)


Latches

D

Clk

Clk

Q

Clk

D

Clk

Q

Transmission-Gate Latch C2MOS Latch

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Pipelined Logic using C2MOS

InF Out

φ

φ

VDD

φ

φ

VDD

φ

φ

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?


C2MOS Example

1

φ

φ

VD D

φ

φ

VDDVD D

Number of a static inversions should be even

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NORA CMOS Modules

φ

φ

VDDVD D

PDN

φ

In1In2In3

φ

VDD

PUN

φ

φ

Out

φ

φ

VD D

Out

VDD

PDN

φ

In1In2In3

φ

VDD

In4

In4

VDD

(a) φ-module

(b) φ-module

Combinational logic Latch


TSPC - True Single Phase Clock Logic

M1

M2

M3

VDD

In

Outφ

φ

M1

M2

M3

VDD

InOut

φ

φ M1

M2

M3

VDD

In

Out

φ

M1

M2

M3

VDD

InOut

φ

Precharged N Precharged P Non-precharged N Non-precharged P

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Doubled TSPC Latches

φ

VDD

Out

φ

VDD

Doubled n-TSPC latch

Inφ

VDD

Outφ

VDD

Doubled p-TSPC latch


TSPC - True Single Phase Clock Logic

φ

VDD

Outφ

VDD

φ

VD D

φ

VDD

InStatic

Logic

PUN

PDN

Including logic into

the latch

Inserting logic between

latches

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Master-Slave TSPC Flip-flops

φ

VDD

D

VDD

φ

VD D

D

φ

VD D

φ

VDD

D

VDD

φ

φ

Dφ

VD D

φ

VD D

D

VDD

φ

φD

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY


DEC Alpha 21064

Dobberpuhl, JSSC 11/92

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DEC Alpha 21064

L1: L2:


DEC Alpha 21064Integrating logic into latches• Reducing effective overhead

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DEC Alpha 21164

L1 Latch L2 Latch

L1 Latch with logic


Differential Latches

CVSL-type latches

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RAM-type latches



Static Ratio-Insensitive Latches

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Types of Flip-Flops

Latch Pair(Master-Slave)

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L


Requirements in the Flip-Flop Design

• High speed of operation:ú Small Clk-Output delayú Small setup timeú Small hold time→Inherent race immunity• Low power• Small clock load• High driving capability• Integration of the logic into flip-flop• Multiplexed or clock scan• Crosstalk insensitivity

- dynamic/high impedance nodes are affected

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Flip-Flop ‘Environment’

• Flip-flop is essential for the performance of high-speeddatapaths

• Higher clock frequencies require storage elements with very short setup times and delays

• Demands for faster operation caused the departure from conventional master-slave structures to revisiting the pulse triggered flip-flops

• Increased levels of parallelism frequently require strong flip-flop driving capability

• Typical flip- flop load in a 0.18µm CMOS ranges from 50fF to over 200fF, with typical values of 100-150fF in critical paths


Flip-Flop Delay l Sum of setup time and Clk-output delay is the only

true measure of the performance with respect to the system speed

l T = TClk-Q + TLogic + Tsetup+ 2Tskew

D Q

Clk

D Q

Clk

Logic

N

TLogicTClk-Q TSetup

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Delay vs. Setup/Hold Times

0

50

100

150

200

250

300

350

-200 -150 -100 -50 0 50 100 150 200

Data-Clk [ps]

Clk

-Ou

tpu

t [p

s]

Setup Hold

Minimum Data-Output


Master-Slave Latches

l Positive setup timesl Two clock phases:

» distributed globally» generated locally

l Small penalty in delay for incorporating MUX

l Some circuit tricks needed to reduce the overall delay

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Master-Slave Latches•Case 1: PowerPC 603 (Gerosa, JSSC 12/94)

Vdd Vdd

Clk

QClk Clkb

Clkb

D


T-G Master-Slave Latch•Feedback added for static operation•Unbuffered inputúinput capacitance depends on the phase of the clockúover-shoot and under-shoot with long routesúwirelength must be restricted at the input•Clock load is high•Low power•Small clk-output delay, but positive setup

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Master-Slave Latches•Case 2: C2MOS

VddVdd Vdd

Vdd

Vdd Vdd

Vdd

VddClk Ck

Ck

Ck

Ck

CkCkb

Ckb

Ckb

Ckb

QD

•Feedback added for static operation•Locally generated clock•Poor driving capability•Robustness to clock slope


Pulse-Triggered Latches

•First stage is a pulse generatorúgenerates a pulse (glitch) on a rising edge of the clock•Second stage is a latchúcaptures the pulse generated in the first stage•Pulse generation results in a negative setup time•Frequently exhibit a soft edge property

Note: power is always consumed in the pulse generator

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Pulse-Triggered Latches•Case 1: Hybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC’96

Vdd

D

Clk

Q

Q


HLFF Operation•1-0 and 0-1 transitions at the input with 0ps setup time

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Hybrid Latch Flip-Flop

•Flip-flops features: úsingle phase clockúedge triggered, on one clock edge•Latch features: Soft clock edge propertyúbrief transparency, equal to 3 inverter delaysúnegative setup timeúallows slack passingúabsorbs skew•Hold time is comparable to HLFF delayúminimum delay between flip-flops must be controlled•Fully static•Possible to incorporate logic


Soft Edge Property•Also known as cycle borrowing, or slack passing•In latch based designs, if longest path datum reaches latch before its setup time, clock skew does not affect cycle time•If longest path reaches latch close to setup time, clock skew is directly subtracted from cycle time•Flip-flop presents a ‘hard’ edge - no slack passing.•HLFF is a compromise - has a controlled transparency period, that can absorb skew•Price is paid in the hold time

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Hybrid Latch Flip-Flop

Partovi et al, ISSCC’96

Skew absorption



•Case 2: Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits’98

Clk

D

Vdd Vdd

Q

Q

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Semi-Dynamic Flip-Flop

•Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transition•Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists•Small penalty for adding logic


J-K Latch

S

R

Q

Q Q

J

K

φ

QJ

K Q

Jn Kn Qn+1

0011

0101

Qn

01Qn

(b)

(c)

Q

(a)φ

Data can change while clock is high

QJ

K Q

φφ

D Q

Qφ

D

Delay Flip -Flop

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J-K Flip-Flop


Pulse-Triggered Latches•Case 3: 7474, Texas Instruments’64

Clk

D

Q

Q

S

R

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7474•Karnaugh maps for signals S and R

x 1

x 1

Clk, D 00 01

00

11 10

1 1

1 1

x 1

x 1

1 0

0 0

01

11

10

S R R

S

DClk

SDR

Clk

x 1

x 1

Clk, D 00 01

00

11 10

1 1

1 1

x 0

x 0

0 1

1 1

01

11

10

S R R

S

DClk

RSD

Clk

Clk

D

Q

Q

S

R

D

SDRClkS ⋅⋅⋅= RDSClkR ⋅⋅⋅=



•First stage is a sense amplifier, precharged to high, when Clk = 0•After rising edge of the clock sense amplifier generates the pulse on S or R•The pulse is captured in S-R latch•Cross-coupled NAND has different propagation delays of rising and falling edges

Case 4: Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 110

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Sense Amplifier-Based Flip-Flop

•Falling transition at S causes rising of Q and after one gate delay falling of •Falling transition on R causes rising of , and after one gate delay falling of Q

S

RQ

Q


Modified Sense Amplifier-Based Flip-Flop

•The new design is based on S-R latch realization using both inputs and the previous value of complementary output•Two possible representations for the new value of Q, to be used for pull-up and pull-down networks:

QRSQ ′+= ( )QSRQ ′+⋅=

x 1

x 1

1 0

0 0

QR ′⋅R

S

S

Q′

x 1

x 1

1 0

0 0

R

QS ′+

R

S

Q′

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Modified Second Stage

•Direct implementation of logic equations, using NMOS pull-down tree and PMOS pull-up tree, results in equivalent tree topologies•Output Q is symmetrical and produces equal delay•Delay of PMOS tree is matched to the delay of NMOS tree preceded by an inverter

S R

ddV

QQ

R S

R S

RS


Modified Sense Amplifier-Based Flip-Flop

•The first stage is unchanged sense amplifier•Second stage is sized to provide maximum switching speed•Driver transistors are large•Keeper transistors are small and disengaged during transitions

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New Sense Amplifier-Based Flip-Flop

•Delay of each of the outputs is independent of the load on the other output•Delay of Q and Q is symmetrical as opposed to the NAND based design •It is convenient for dual rail logic and driving strength for standard CMOS is effectively doubled•SAFF presents a small clock load, small setup time and all the advantages of original design


Flip-Flop Delay vs. Setup Time•Single-ended vs. differential version

0

100

200

300

400

500

600

-500 -400 -300 -200 -100 0 100 200 300 400 500 600

Data-Clk (Setup/Hold Time) [ps]

Clo

ck-O

utpu

t [p

s]

Differential

Single ended

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Simulated SAFF Performance•Typical SAFF waveforms, illustrating equal delays of both outputs and equal delays of rising and falling transitions•CMOS, nominal corner, Leff = 0.18µm, VDD = 1.8V, T = 25°C, load = 200fF on both outputs

230ps

S

R Clk Q

Q


Measured Flip-Flop Delay vs. Setup Time

•Measured delays compared to simulated values

0

50

100

150

200

250

300

350

400

450

500

-200 -150 -100 -50 0 50 100 150 200

Data-Clk (Setup/Hold Time) [ps]

Clk

-Out

put D

elay

[ps]

Simulated

Measured

Sampling Window

Setup Hold

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Flip-Flop Performance Comparison

•Total power consumed–internal power–data power –clock power•Measured for four cases–no activity (0000… and 1111…)–maximum activity (0101010..)–average activity (random sequence)

Test bench

Delay is (minimum D-Q)Clk-Q + setup time

Clk

Data

Clock

50fF

200fF

200fFD Q

Q

Stojanovic, Oklobdzija JSSC4/99


Flip-Flop Performance Comparison

•Delay vs. power comparison of different flip-flops•Flip-flops are optimized for speed with output transistor sizes limited to 7.5µm/4.3 µm•Total transistor gate width is indicated

0

10

20

30

40

50

60

70

100 150 200 250 300 350 400 450 500

Delay [ps]

Tot

al p

ower

[uW

]

mSAFF64µm SDFF 49 µm

HLFF 54µm

C2MOS80µm

TG M-S52µm Original SAFF 60µm

EE241 - Spring 2000bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s00/LECTURES/...EE241 1 UC...

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Transcript of EE241 - Spring 2000bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s00/LECTURES/...EE241 1 UC...