EE241 - Spring 2006bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s06/Lectures/Lecture8... · 1...
Transcript of EE241 - Spring 2006bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s06/Lectures/Lecture8... · 1...
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EE241 - Spring 2006Advanced Digital Integrated Circuits
Lecture 8:Logic Families for Performance
Dynamic Logic
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Notes
Homework 2 to be posted today
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Differential Logic Using Ordered BDDs
BDD = Binary Decision Diagrams
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Pass-Transistor Logic
OptionsNMOS Only
Transmission gate
NMOS + PMOS
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NMOS-only switch
A =2.5V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Threshold voltage loss causes static power consumption
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time, ns
Volta
ge, V
xOut
In
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Solutions
Transmission gates – adding complexity
Low-threshold switches – leakage!
Level-restoration
M 2
M 1
M n
M r
OutA
B
V DDV DDLevel Restorer
X
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Single-Ended Level Restoring
OutputInput
Feedback Inverter
Output InverterLevel Restoration
Transistor
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Differential Level Restoring
Differential NMOS Logic Tree
f f
Inputs
Inputs
Different level restoration leads to different logic families
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Different Restoration Schemes
Differential NMOS Logic Tree
f f
Inputs
Inputs
Swing-Restored Pass-Transistor Logic
Parameswar, et alCICC’94, JSSC 6/96
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Other Level-Restoring Schemes
Differential NMOS Logic Tree
f f
Inputs
Inputs
Differential NMOS Logic Tree
ff
Inputs
Inputs
Energy Economized Pass-TransistorLogic
DCVS with Pass Gates(DCVS-PG)
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Pass-Transistor Logic Families
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Complementary Pass-Transistor Logic (CPL)
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Complementary
• Complementary functions• Reduced number of logic levels• Less transistors than CMOS • Fast – reduced load• Complementary inputs – complementary outputs• VT drop – several solutions
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CPL
Level restoration
Yano et al, CICC’89, JSSC 4/90
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CPL
Same topology of networksJust different signal arrangements
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Complementary Pass-Transistor Logic (CPL)
AA
S S
A A
B
B
C
C
SS(a) (b)
B
B
Q Qb
n1 n2
n4n3
XOR Sum
nFET logicnetwork
- Fast- VT drop- Efficient
implementationof arithmetic
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CPL Karnaugh Maps
A
B
0 0
0 1
C1 C2
A
A
B A
BA ⋅
C2 C1
A
A
B
BA ⋅
C2 C1
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Differential vs. Single-Ended
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Leap Cell Library
Yano et al, CICC’94, JSSC 6/96
Goal: Implement full logic functionality with small libraryRely on automated design methodology
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Double Pass-Transistor Logic (DPL)
A
B
A B B A
VDD
B
A
OO
A
B
A B BA
B
A
OO
B
A
B A B A
B
A
A B
A B
AND/NAND
XOR/XNOR
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Designing DPL Gates
A
B
0 0
0 1
C3 C4
C1
C2
A
A
B
BA.
C2
C1
A B
B
C3
C4
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Designing DPL Gates (2)
A
B
0 1
1 0
C3 C4
C2
C1
A
B
0 1
1 0
C1 C2
C3
C4
B
BA⊕
B
A
A A
B
B
A
C2
C1C3
C4
A
BA⊕
A
B
B B
A
A
B
C1 C2
C3C4
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Applications of DPL
1.5ns 32-bit ALU in 0.25μm CMOS
Full adder:
Suzuki, ISSCC’93JSSC 11/93
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Dynamic Logic
Mp
Me
VDD
PDN
φ
In1In2In3
OutMe
Mp
VDD
PUN
φ
In1In2In3
φ
φ
Out
CL
CL
φp networkφn network
2 phase operation:• Evaluation
• Precharge • N + 1 Transistors
• Ratioless
• No Static Power Consumption
• Noise Margins small (NML)
• Requires Clock
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Dynamic Gates
NMOS Inverter PMOS Inverter
Courtesy of IEEE Press, New York. © 2000
See Bowhill, Chapter 7.
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Dynamic Logic
Advantages:Fast
Compact
Disadvantages:Less robust (noise margins, sensitive to leakage, noise coupling, charge sharing)
Needs clock
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Logical Effort
LE =
φ
φ
In
Out
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Logical Effort
LE =
φ
φ
Out
LE =
φ
φ
Out
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Dynamic Logic Challenges
Charge leakage
Charge redistribution
NoiseSignal interference
Supply noise
Substrate coupling
Ch 8 in Chandrakasan/Bowhill
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Charge Leakage
Courtesy of IEEE Press, New York. © 2000
ILeak = (IN sub + IN diode) – (IP sub + IP diode)
Time to switch the next gate: tsw = (CDYN * Vsw)/ILeak
Limits the minimum frequency:fmin = 1/(tsw * #phases per clk cycle)
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Compensating Leakage
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Charge Sharing (Redistribution)
Mp
Me
VDD
φOut
φ
A
B = 0
CL
Ca
Cb
Ma
Mb
X
CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=
or
ΔVout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =
ΔVout VDD
CaCa CL+----------------------⎝ ⎠⎜ ⎟⎛ ⎞
–=
case 1) if ΔVout < VTn
case 2) if ΔVout > VTn
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Charge Sharing - Solutions
Mp
Me
VDD
φ
Out
φ
A
B
Ma
Mb
Mbl Mp
Me
VDD
φOut
φ
A
B
Ma
Mb
Mbl
(b) Precharge of internal nodes
φ
(a) Static bleeder
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Aside: Dynamic Latch
Courtesy of IEEE Press, New York. © 2000
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Charge Sharing
A,B = 0DYN prechargedCharge sharing ifSEL toggles
Courtesy of IEEE Press, New York. © 2000
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Aside: Noise in ICs
Sources of noiseCoupling
Device couplingCapacitive coupling between wiresInductive coupling
Supply line bounceCharge Injection
From substrateα-particles
Robustness of a circuitNoise marginsSensitivity to noise
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Clock Feedthrough
Mp
Me
VDD
φOut
φ
A
B
CL
Ca
Cb
Ma
Mb
Xφ
2.5V
overshoot
out
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Miller and Back-gate Coupling
Courtesy of IEEE Press, New York. © 2000
ClockFeedThrough(or Miller)
Back-gate coupling
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Capacitive Coupling
Courtesy of IEEE Press, New York. © 2000
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Capacitive Coupling
Dynamic node: Static node:
Courtesy of IEEE Press, New York. © 2000
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Capacitive Coupling
Courtesy of IEEE Press, New York. © 2000
Lateral coupling: Shielding
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Minority Charge Injection
Courtesy of IEEE Press, New York. © 2000
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Supply Noise
Courtesy of IEEE Press, New York. © 2000
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Cascading Dynamic Gates
Mp
Me
VDD
φ
φ
Mp
Me
VDD
φ
φ
In
Out1 Out2
φ
Out2
Out1
In
V
t
ΔV
VTn
(a) (b)
Only 0→1 Transitions allowed at inputs!
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Cascading Dynamic Logic
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Domino Logic
Mp
Me
VDD
PDN
φ
In1
In2
In3
Out1
φ
Mp
Me
VDD
PDN
φ
In4
φ
Out2
Mr
VDD
Static Inverterwith Level Restorer
Krambeck et al, JSSC 6/82
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Logical Effort
LE =
φ
φ
In
Out
Inverter pair:
Skewed inverter pair:
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Logical Effort
LE =
φ
φ
Out
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Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1->0 transitions at input of inverter
move VM upwards by increasing PMOS
• Adding level restorer reduces leakage andcharge redistribution problems
• Optimize inverter for fan-out
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Designing with Domino Logic
Mp
Me
VDD
PDN
φ
In1
In2
In3
Out1
φ
Mp
Me
VDD
PDN
φ
In4
φ
Out2
Mr
VDD
Inputs = 0during precharge
Can be eliminated!
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Logical Effort
LE =
φ
Out
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Domino Properties
Logic evaluation propagates as falling dominoes
Evaluation period determines the logic depth
The nodes must be precharged during the prechargeperiod (can limit the minimum size of PMOS)Inputs must be stable (or have only one rising transition) during the evaluation
Gates are ratioless
Restorer is ratioed
All the gates are non-inverting
Only one transition to be optimized
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Logic Design Problem
How to design an XOR/MUX without a complementary signal available? We need it in datapaths!If the logic is followed by a flip-flop, or a latch with a hard edge, can use complementary or pass-transistor logicDomino logic is used with latches, and a new domino stage may follow the XORSolutions:
Use dual-rail domino (dynamic CVSL)Violate some of domino rules (but still design a reliable circuit)Force a hard edge
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Sum Implementation (1)
Clk
Gi:0
VDD
Clkd
VDDKeeper
Clk
Clk
Clk
Gi:0
Clkd
Si1
Si0
Sum
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Sum Implementation (2)
[Anders et al, ISSCC’02]