EE241 - Spring 2000 - University of California,...

EE241

1

UC Berkeley EE241 B. Nikoli c

EE241 - Spring 2000Advanced Digital Integrated Circuits

Lecture 16

Adders


Carry-Skip Adder

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co,2Co,1Co,0Ci,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

Co,3

Mul

tiple

xer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.

Bypass

MacSorley, Proc IRE 1/61Lehman, Burla, IRE Trans on Comp, 12/61

EE241

2


Carry-Skip Adder

Setup

CarryPropagation

Sum

Setup

CarryPropagation

Sum

Setup

CarryPropagation

Sum

Setup

CarryPropagation

Sum

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

C i,0

Critical Path

( ) ( ) RCASKIPRCAd tktkN

tkt 121 −+

−+−=

For N-bit adder with k-bit groups


Carry-Skip Adder

( ) SKIPRCAd tkN

tkt

−+−= 212

Critical path delay with constant groups

N

tp

ripple adder

bypass adder

4..8

EE241

3


Carry-Skip Adder

Variable Group Length

Oklobdzija, Barnes, Arith’85

321 cNcctd ++=


Carry-Skip Adder

Variable Block Lengths

EE241

4


Manchester Carry Chain

P0

Ci,0

P1

G0

P2

G1

P3

G2

P4

G3 G4

φ

φ

VDD

Kilburn, et al, IEE Proc, 1959.

•Implement P with pass-transistors•Implement G with pull-up, kill (delete) with pull-down•Use dynamic logic to reduce the complexity and speed up


Sizing Manchester Carry Chain

R1

C1

R2

C2

R3

C3

R4

C4

R5

C5

R6

C6

Out

M0 M1 M2 M3 M4MC

Discharge Transistor

1 2 3 4 5 6

tp 0.69 Ci Rjj 1=

i∑

i 1=

N∑=

1 1.5 2.0 2.5 3.0k

5

10

15

20

25

Spe

ed

1 1.5 2.0 2.5 3.0k

0

100

200

300

400

Are

a

Speed (normalized by 0.69RC) Area (in minimum size devices)

EE241

5


Manchester Chain with Carry-Skip

P0

Ci,0

P1

G0

P2

G1

P3

G2

BP

G3

BP

Co,3

Delay model:


PTL with SA-F/F Implementation

Matsui,JSSC 12/94

EE241

6


Propagate and Generate Signals

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A ⊕ B

Delete = A B

Can also derive expressions for S and Co based on D and P


A0,B 0 A1,B 1 AN-1 ,BN-1...

Ci,0 P0 Ci,1 P1Ci,N-1 PN-1

...

Carry Lookahead Adder

Weinberger, Smith, 1958.

EE241

7


Lookahead Adder

1−+= iiii cpgc

Looakahead Equations

( )1111

111

111

−+++

−++

+++

++=

++=+=

iiiiii

iiiii

iiii

cppgpg

cpgpgcpgc

Position i:

Position i + 1:

Carry exists if:- generated in stage i + 1- generated in stage i and propagated through i + 1- propagated through both i and i + 1


Lookahead Adder

• Unrolling of carry recurrence can be continued• If unrolled to level k, resulting in two-level AND-OR

structure• AND Fan-In = k + 1, OR Fan-In = k + 1• k + 1 transistors in the MOS stack• Limits k to 3 -4

EE241

8


Lookahead AdderVDD

P3

P2

P1

P0

G3

G2

G1

G0

Ci,0

Co,3


Block Lookahead

1123123

1232334

−++++++

+++++++

++

++=

iiiiiiiii

iiiiiii

cppppgppp

gppgpgcFourth bit carry:

iiiiiiiiiiii gpppgppgpgG 1231232333, ++++++++++ +++=

iiiiii ppppP 1233, ++++ =

13,3,4 −+++ += iiiiii cPGc

Block generate and block propagate:

EE241

9


Block Lookahead

Can create groups of groups, or ‘super-groups’:

jjjjjjjjjjj GPPPGPPGPGG 123123233*

+++++++++ +++=

jjjjj pPPPP 123*

+++=

Delay is Nctd log1=


Block LookaheadFrom Oklobdzija

EE241

10


Lookahead Example

Multiple Output Domino (MODL)

Generate Propagate


4-bit group generate 4-bit group propagate

Lookahead Example

EE241

11


64-b Lookahead Example


Lookahead Example

EE241

12


Modified CLA

Naini, CICC’92


Modified CLA

EE241

13


Conditional Sum Adders

Sklansky,Trans on Comp6/60

iii yxs ⊕=0

iii yxs ⊕=1

iii yxc ⋅=0

iii yxc +=1


Conditional Sum Adders

EE241

14


TG Conditional SumConditional CellConditional Sum Adder

2-way MUXes

Rothermel, JSSC 89


TG Conditional Sum

l Serial connection of transmission gates l Chain length = 1+log2n

Signal propagation

EE241

15


DPL Conditional Sum

CLA“Conditional carry select”


DPL Conditional Sum

Block Conditional Sums

EE241

16


Carry-Select Adder

Setup

"0" Carry Propagation

"1" Carry Propagation

Multiplexer

Sum Generation

Co,k-1 Co,k+3

"0"

"1"

P,G

Carry Vector


Carry Select Adder: Critical Path

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

S0-3 S4-7 S8-11 S12-15

Co,15Co,11Co,7Co,3Ci,0

EE241

17


Linear Carry Select

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

S0-3 S4-7 S8-11 S12-15

Ci,0

(1)

(1)

(5)(6) (7) (8)

(9)

(10)

(5) (5) (5)(5)


Square Root Carry Select

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Setup

"0" Carry

"1" Carry

Multiplexer

Sum Generation

"0"

"1"

Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13

S0-1 S2-4 S5-8 S9-13

Ci,0

(4) (5) (6) (7)

(1)

(1)

(3) (4) (5) (6)

Mux

Sum

S14-19

(7)

(8)

Bit 14-19

(9)

(3)

EE241

18


Logarithmic Lookahead Adders

A7

F

A6A5A4A3A2A1

A0

A0

A1

A2A3

A4

A5

A6

A7

F

tp∼ log2(N)

tp∼ N


Tree Adders

lmG ppP ⋅=

lmmG gpgG ⋅+=

m – more significantl – less significant

Start from the input P, G, and continue up the tree2-bit groups, then 4-bit groups, …

( ) ( ) ( )lmlmmllmm ppgpgpgpgpg ⋅⋅+=•= ,,,),(

Kogge, Stone, Trans on Comp,’73

EE241

19


Brent-Kung Adder(G0,P0)(G1,P1)

(G2,P2)

(G3,P3)

(G4,P4)(G5,P5)

(G6,P6)

(G7,P7)

Co,0

Co,1Co,2

Co,3

Co,4

Co,5

Co,6

Co,7

tadd ∼ log2(N)Brent, Kung, Trans on Comp, 3/82


Tree Adders

EE241 - Spring 2000 - University of California,...

Documents

Transcript of EE241 - Spring 2000 - University of California,...