EDN Design Ideas 2002

The novel logarithmic amplifier inFigure 1 relies on the expo-nential charging characteris-tics of a simple RC circuit. The expressionfor the time, T, required for a capacitor,C, to reach a voltage (V

IN2V

K) from 0V,

when charged through a resistor, R, withan applied voltage of V

IN, is V

IN2V

K

5VIN

(12e2T/RC), where VK

is a fixed volt-age. The expression for T reduces toT5RCln(V

IN/V

K), clearly showing an in-

herent logarithmic characteristic. Thecircuit in Figure 1 demonstrates thischaracteristic, using a 556 timer.With thevalues shown, the first stage of the 556timer is a standard astable circuit oper-ating at a frequency of approximately 1kHz. The output of this stage acts as thetrigger for the second stage. The secondstage operates as a modified monostablecircuit. In this modified configuration,the RC combination, R

1and C

1, charges

from an external voltage, VIN

, instead ofV

CC. The control-voltage pin, CV2, has

the value VIN

minus one diodedrop, V

K.

The monostable pulse width, T, thendepends on the time required for capac-itor C

1to charge to V

IN 2V

Kthrough R

1

www.ednmag.com January 10, 2002 | edn 71

ideasdesignEdited by Bill Travis

Log amp uses capacitor-charging law....................................................71

Extend the timing capabilities of a PC ......72

Optocoupler simplifies power-line monitoring ..................................76

Improved amplifier drives differential-input ADCs..................................80

Circuit forms dc-motor switch with brake ........................................................82

0.01mF0.1 mF

VCC15V

DIS1

TH1

CV1

RES1

OUT1

TRI1

GND

VCC

DIS2

TH2

CV2

RES2

OUT2

TRI2

LM556C

1k

6.8k

1

2

3

4

5

6

7 8

9

10

11

12

13

14

1N914C R19.1k

C10.02 mF

C21 mF

VCC15V

INPUTVOLTAGE

OUTPUTVOLTAGE

220

1k

100k

DCR2

F igure 1

Log amp uses capacitor-charging lawJayashree Raghuraman and Ajoy Raman, Aeronautical Development Establishment,Bangalore, India

A simple 556 timer depends on RC charging to form a logarithmic amplifier.

7

6.5

6

5.5

5

4.5

4

3.5

3

2.52 4 6 8 2010

INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

LINEAR FIT OF EXPERIMENTAL DATA

EXPERIMENTAL DATA

F igure 2

The circuit of Figure 1 produces a distinct logarithmic output.

with the applied voltage VIN

.The output of the second stage,filtered through R

2and C

2, de-

pends on the first stagesastable frequency; the supplyvoltage, V

CC; and the mono-

stable pulse width, T. BecauseV

CCand the astable frequency

are constant, VOUT

is propor-tional to T. Table 1 tabulatesthe experimental results, andFigure 2 shows graphical re-sults. The circuit operation islimited to an input range of 2.5

to 13V to satisfy the internal bi-asing requirements of the sec-ond stage of the 556. The diodedrop,V

K, is not strictly constant,

because it varies with current.In spite of these limitations,Table 1 and Figure 2 clearlyshow a distinct logarithmiccharacteristic.

72 edn | January 10, 2002 www.ednmag.com

ideasdesign

Even when you use the internal tim-ing registers and under DOS,a PC cannot easily measuretime intervals with better time resolutionthan a millisecond. Measuring long in-tervals with even this precision is a wasteof many CPU cycles. A microcontroller iswell-suited for this task; you can easily in-tegrate a PIC with a PC to extend the tim-ing precision into the microsecond rangefor periods from tens of microseconds tomore than 24 hours. The flash-program-mable PIC16F84 microcontroller fromMicrochip Technology (www.microchip.com) is an inexpensive and widelyused device. The precision timer in Fig-ure 1 requires only the IC, two capacitors,and a crystal and accepts direct input oftiming data to a PC via the parallel port.The PIC16F84 draws only 2 mA and canoperate from an output pin in the paral-lel port without a battery. You can as-semble the circuit on a small pc boardwith a male DB-25 connector glued orsoldered to one end for connection to theparallel port, LPT1. In this example, thetiming signal occurs when you block aphotogate comprising a paired LED anda phototransistor.

Listing 1 represents the timing appli-cation implemented, which comprises

two basic parts. The first part waits for asignal and starts a loop that checks thecontinuing presence of the signal and in-crements 32 timing bits while the signalis present. The second part transmits 32bits of timing information to an externaldevice, using one data-output line andtwo handshaking lines. With a 4-MHz

crystal, most instructions take 1 msec, sothe timing loop is 5 msec long. You canrun newer PIC16F84s with a 20-MHzclock, so, in principle, the timing loop canbe 1 msec long. Port A of the PIC servesfor the timing signal on bit 3 and forcommunication. A minor coding changeallows you to use positive or negative log-

PIC16F84

1 A2

2 A3

3 A4

4 MCLR

5 VSS

A1 18

A0 17

OSC1 16

OSC2 15

VDD 14

10

11

6

5

18 TO 25V

22 pF

22 pF

4.0000 MHz

3

EOPT805SL

C

4

100k500

LD271LED

B C

E

OPT805SLBOTTOM

VIEW

F igure 1

Extend the timing capabilities of a PCMartin Connors, Athabasca University, Athabasca, AB, Canada

This zero-power photogate allows you to use a PC to generate precise timing intervals.

Is this the best Design Idea inthis issue? Vote at www.ednmag.com.

TABLE 1OUTPUT VERSUS INPUT VOLTAGEInput voltage Output voltage Input voltage Output voltage

2.5 3.324 8 5.7823 3.667 8.5 5.861

3.5 3.954 9 5.8864 4.227 9.5 5.945

4.5 4.506 10 6.0985 4.705 10.5 6.187

5.5 4.956 11 6.2046 5.151 11.5 6.312

6.5 5.315 12 6.3717 5.444 12.5 6.378

7.5 5.615 13 6.476


ideasdesign

LISTING 1ZERO-POWER PHOTOGATE-ASSEMBLY PROGRAM

ic levels. If the timing signal is present atthe start of the program, an error flagarises, with an output of 4 bytes of 0xFF.A similar error occurs if the signal is pres-ent long enough (roughly a day) to causeoverflow of the counter. DATO (data out-put) occurs through bit 0. The routineuses two handshake lines: VALID on bit1 from the PIC to signal the presence ofvalid data on the DATO line and SENDfrom the PC to bit 2, signifying that thePC is ready to receive data. This robusttransmission method does not dependon timing characteristics in a critical way.

Listing 2 (pg 76) shows sample C codefor Borland Turbo C for DOS with a sim-ple timing conversion that doesnt take

account of the overhead of byte overflow.After the PIC times an event, it waits forthe PC to signal that it wants to down-load data. The transmission protocol fortransmitting 1 bit of data is as follows: PCSEND is low, and the PIC polls it. PICVALID is initially low; the PC raisesSEND and polls VALID. In response, thePIC puts DATA on the line. The PIC thanraises VALID and polls SEND; in re-sponse, the PC reads DATA. The PC thenlowers SEND, and the PIC lowers VALID.This operation repeats for 32 bits, start-ing with the lowest bit of the lowest byteand proceeding to the highest bit of thehighest (fourth) byte. Although thistransmission method is inefficient, it is

robust, and the polling timing is unim-portant. The efficiency matters little, be-cause the method involves little datatransfer. By referring to the listings, youcan step throughthe process to see howthe transfer takes place. Listing 2 in-cludes a test routine that allows you tosupply a signal from the PC to test thecircuits operation. You can downloadlistings 1 and 2 from the Web version ofthis article at EDNs Web site, www.ednmag.com.

Is this the best Design Idea in this issue? Vote at www.ednmag.com.


ideasdesign

LISTING 2PHOTOGATE-SUPPORT PROGRAM

The use of a linear optocouplerand a capacitor-based powersupply yields a simple, yet pre-cise power-line-monitoring system.The circuit in Figure 1 converts the110V-ac power-line voltage to an acoutput voltage centered at 2.5V, cov-ering 0 to 5V. The circuit isolates theoutput signal from the power line.You can connect the output directlyto an A/D converter. For other pow-er-line voltages, simply change thevalue of R

1. For a power-line voltage of

220V ac, use a value of 470 kV for R1. The

input stage is a nonisolated block thatuses the neutral line as a ground refer-ence. This block receives power from acapacitor-based power supply that pro-

vides a stabilized 5V-dc voltage and a3.3V dc reference. The TLC2272 op amp,IC

1, and the TLC2272 linear optocoupler,

IC3, form a feedback amplifier in which

the IP1

current is proportional to the in-put voltage, V

IN.

Resistor R2 adds a dc offset cur-

rent to allow for both polarities inV

IN. The match between the two

photodiodes in the IL300, IC2, en-

sures that IP2

is closely proportion-al to I

P1. The output stage converts

IP2

to a voltage level isolated fromthe power line. Variable resistorVR

2trims the overall gain, and VR

1

adjusts the output-voltage offset,which is nominally 2.5V. You cantest this circuit using simulation

the model in Listing 1 for IC2. Typical

values for K1

and K2

(optical transfer ra-tios) are approximately 0.007. The glob-al optical transfer ratio is K

35K

2/K

1. Af-

ter performing the simulation, you canbuild and test a prototype. The power

Optocoupler simplifies power-line monitoringAlfredo del Rio and Ana Cao y Paz, University of Vigo, Spain

TABLE 1OUTPUT OFFSET-VOLTAGE DRIFTTIL300 (88C) VOUT (V) TIL300 (88C) VOUT (V)17.5 2.496 37.5 2.50620 2.497 40 2.50722.5 2.498 42.5 2.50925 2.5 45 2.5127.5 2.501 47.5 2.51230 2.503 50 2.51332.5 2.504 52.5 2.51535 2.505

supply for the isolated block provides 5Vdc and a 3.3V reference from anavailable voltage of 7 to 10V. Youdo not need the regulated 5V if that volt-age is already available in your system.

An important goal in this design is toobtain a stable dc voltage at the output.This property is crucial for dc measure-ments of V

IN. Even if you suppose the ac

power line to be free of dc voltage, sometypes of loads drain dc currents, therebyintroducing a small dc voltage because ofvoltage drops in the ac lines. Thermaldrifts in the output voltage stem princi-pally from drifts in K

3. In tests of the pro-

totype, the K3

temperature coefficientwas 470 ppm/8C. Table 1 shows V

OUT at

different temperatures. The TLC2272 opamp has rail-to-rail output, yielding awide output-voltage range, and low qui-escent current, simplifying the capacitor-based power supply. Because theTLC2272 is a dual device, you can con-nect the unused half as a voltage follow-er. When you monitor a three-phasepower line, youd use one and one-halfTLC2272s. Note that the op amps in theisolated block, IC

3, and the nonisolated

block, IC1, cannot be halves of the same

chip; otherwise, youd lose the isolation.The main specifications of the circuit

are 5300V-ac-rms galvanic isolation,0.08% linearity, 470-ppm/8C thermalshifts in V

OUT, 28 phase shift at 50 Hz, and

dc to 1-kHz bandwidth at 23 dB. If youconnect the output to a 10-bit A/D con-

verter, one LSB is equivalent to 0.5V inthe 110V power line. You can add a Hall-effect sensor to the circuit for currentmeasurements. The LTS series from LEM(www.lemusa.com) is suitable for thispurpose, because these devices operatefrom a single 5V supply and provide a2.5V-centered output. Figure 2 shows asystem that integrates voltage and cur-rent measurements. The processor com-putes true-rms voltages and currents, ap-parent and active power, and powerfactor.


ideasdesign

+

2

IC1

R2

+

2

IC3

VR2

VOUT

VR1

IC2

IF

IP1

IC65V

IC53.3V

IC45V

IC73.3V

+

2

7 TO 10VDC

330 mF

350k

500k

33 mF47 mF47 mF

470 pF1 kV

100100 mF 47 mF9.1V

1

2

3

4

8

7

6

5IP2

100 pF

2.4kVIN

R1240k

330k

1k

1k3

2

110V AC

470k4

81

3

2

8

4

1

NOTES:IC1 AND IC3=TLC2272.IC2=IL300.IC4 AND IC6=TC55 RP 500201.IC5 AND IC7=TC55 RP 330291.

NONISOLATED BLOCK ISOLATED BLOCKF igure 1

An isolated optocoupler circuit allows you to make dc measurements of the power-line voltage.

DATA-PROCESSINGSYSTEM

ADC

ADC

IMONITOR

VMONITOR

OUTPUT110V AC

F igure 2

By adding two ADCs and a microcontroller, you can measure power-line voltage and currentparameters.

LISTING 1SIMULATION MODEL



ideasdesign

ADCs with differentialinputs are be-coming increas-ingly popular. This populari-ty isnt surprising, becausedifferential inputs in the ADCoffer several advantages: goodcommon-mode noise rejec-tion, a doubling of the avail-able dynamic range withoutdoubling the supply voltage,and cancellation of even-or-der harmonics that accruewith a single-ended input.But the differential inputstructure doesnt eliminatethe frequent need for addi-tional gain between the signal source andthe ADC. A frequently used gain stage isthe classic, three-op-amp instrumenta-tion amplifier (Figure 1). This popularcircuit offers excellent common-moderejection and high input impedance. Thecircuit also has an output-reference(ground-sense) terminal, allowing you toreference the output voltage to a voltageother than ground. However, this circuithas a single-ended output (relative to the

reference terminal), so its a poor matchfor a differential-input ADC.

Figure 2 shows two easy ways to cre-ate a differential-input instrumentationamplifier. In Figure 2a, IC

4and its asso-

ciated feedback resistors are connected inparallel with the original output ampli-fier but with inverted polarity relative tothe original circuit. The two outputs to-gether provide the desired function, butthe circuit requires many matched resis-

tors. Furthermore, the com-mon-mode reference inputcould require several mil-liamperes of drive, dependingon the resistor values andvoltages involved. However,the circuit does the job, andyou can build it by using ahigh-quality quad op ampand a handful of resistors.Figure 2b shows a more effi-cient and elegant approach,using only the four resistorsrequired in the original out-put stage. In this circuit, amodern, fully differential opamp, such as the AD8138, re-

places IC3

and IC4

in Figure 2a. The am-plifiers two outputs swing symmetrical-ly about its high-impedance, common-mode reference input. The differentialoutputs provide a clean, simple interfaceto a differential-input ADC.

+

2

+

2

+

2

+IN

REF

2INGAIN=1+

2RFRG

RF

VOUT

RF

RG

F igure 1

Improved amplifier drives differential-input ADCsStephan Goldstein, Analog Devices, Wilmington, MA

The classic three-op-amp instrumentation amplifier does not provide dif-ferential outputs.

+

2

+

2+

2

+

2

+IN

REF

2IN

GAIN=2+4RFRG

RF

IC1

IC2

IC3

IC4

RF

RG

+

2

+

+2

2

+

2

+IN

+VOUT

REF

2IN

2VOUT

+VOUT

2VOUT

GAIN=2+4RFRG

RF

R R

RF

RG

AD8138

AD8021

AD8021

(a) (b)

F igure 2

The four-op-amp instrumentation amplifier (a) provides differential outputs but requires many matched resistors. A differential-output op amp (b)reduces the IC count in Figure 2a to three.


Controlling a small dc motorwithout speed control sounds like atrivial task; a switch or a relayshould suffice. However, several prob-lems accompany this approach.For one, the switch, because ofthe inductive load and the low starting re-sistance of the motor, tends to wear outprematurely (with all the related sparksand EMI problems). Second, when youcut the power, the motor continues to ro-tate for a certain time, depending on itsinitial speed and inertia. The circuit inFigure 1 can be useful for designs thatdont need precise control of speed andstopping position but can benefit fromenhanced deceleration. The circuit com-prises two parts. Q

1plays the role of the

switch. D2

protects Q2

against inductivesurges. Resistor R

2keeps Q

1off as long as

switch S1

is open. R1

limits the base cur-rent of Q

1when S

1is closed. S

1can be a

manual switch, a relay contact, an opto-coupler, or a transistor. If you close S

1, Q

1

turns on, and the motor runs.Q

2, D

1, and R

3constitute the braking

circuit. This circuit is similar to the out-put circuit of TTL gates. D

3 protects Q

2

from inductive surges. When S1closes, Q

1

turns on, and the voltage at Point A goeshigh (near V

CC). The voltage at the base

of Q2

is higher than the voltage at theemitter, because of the voltage drop in D

1.

If you open S1

while the motor is run-ning, Q

1turns off. The voltage at Point A

is near zero. The self-induced, back-EMFvoltage from the motor sees a short cir-cuit in Q

2, whose emitter is more positive

than its base and thus conducts. Short-circuiting the motor results in braking it.The higher the speed of the motor, thestronger the braking effect.

You should mount the circuit of Q2

asnear as possible to the motor to reducethe series resistance of the wiring. Thisparasitic resistance limits the brakingcurrent and, thus, the deceleration. Thecircuit of Q

1can be remote. The divid-

ing line between the two circuits is atPoint A. This design mounts the circuiton the tool-changer motors of small ma-chine tools, and it has worked perfectlyfor years. The values of the componentsare not critical. The transistors shouldpreferably be Darlington pairs and, likethe diodes, should be types commensu-rate with the power-supply voltage andthe motor current. (Also, dont forget thehigh inductance of the motor.) The com-ponents in Figure 1, for example, aresuitable for a 24V, 3.5A motor.


ideasdesign

MOTOR

Q1

Q2

D2

D1

D3

S1R1

R2

R3

A

VCC

F igure 1

Circuit forms dc-motor switch with brakeJB Guiot, DCS AG, Allschwil, Switzerland

This circuit provides both motor-drive andbraking functions.


The autoreferencing circuit in Fig-ure 1 nulls out the error of a sensor,such as a pressure transducer, at itsreference levelfor example, at ambientpressure. The circuit is an analog-digital-feedback control system that uses a digi-tally programmable potentiometer toprovide the variability. The circuit in Fig-ure 1 is designed to accommodate a pres-sure transducer with a nominal 1V650-mV output at ambient pressure andprovide a voltage of 1V61 mV. Amplifi-er IC

1Ais a summing/difference circuit

whose inputs are the sensors output volt-age, V

SENSE; a voltage shift, V

SHIFT, of 100

mV; and a correction voltage, VCORR

. IC1B

functions as a comparator, comparingthe output voltage of the summing am-plifier with the ideal output voltage of thesensor, 1V. The logic output of the com-parator sets the direction for in-crementing or decrementing thepotentiometers wiper, whose bufferedwiper voltage provides the correctionvoltage, V

CORR.

The potentiometer is a Catalyst 30-tapdigitally programmable potentiometerwith an increment/decrement interface.The correction voltage varies from 0 to 200 mV and subtracts from the shift-ed sensor voltage. Mathematically,V

OUT5(V

SENSE 1V

SHIFT)2V

CORR, where

0mVCORR

m 200 mV, VSHIFT

5100 mV, and

0.95VmVSENSE

m1.05V. The 100-mV, 200-mV, and 1V references for the circuitcome from a 2.5V reference, steppeddown by a resistive divider and bufferedby voltage followers. IC

2Aimplements a

square-wave oscillator whose frequencyis approximately equal to 1/RCin thiscase, 10 kHz. You program the autoref-erencing circuit using the logic-input sig-nals OSC and CS. The circuit becomesdisabled when OSC is low and CS is high.When the circuit is disabled, V

OUTis at its

last corrected value.The circuit becomes enabled and cor-

rects the output voltage for a new sensoror different set of conditions when OSCis high and CS is low. To store the cur-rent wiper setting of the digitally pro-grammable potentiometer in nonvolatile

memory, first make OSC low and thenbring CS from low to high. If power dis-appears and is later restored, the poten-tiometer goes to the corrected valuestored in nonvolatile memory. The meas-ured error in the system is less than 1 mV,but better performing amplifiers, a high-er resolution potentiometer, and moreaccurate resistors can reduce the error tothe low-microvolt region. This circuituses three ICs and a handful of discreteparts and is an alternative, low-cost ap-proach to more complex autoreferencingcircuits using DACs, ADCs, and micro-processors.

www.ednmag.com January 24, 2002 | edn 85

ideasdesign

Autoreferencing circuit nulls out sensor errors ..................................85

Low-power keypad consumes only 100 nA..................................86

Time-tag impulses with zero-crossing circuit ..............................88

Circuit provides reference for multiple ADCs ..........................................92

Publish your Design Idea in EDN. See theWhats Up section at www.ednmag.com.

Edited by Bill Travis

2

2

+

+

5V

2

+

2

+

2

+

200 mV

100 mV

2M6064

IC1C

2k

2k

15.8k

1V

30.1kLM40401.5V

2.49k

CS

OSC

IC2A74HC 1324

1

10k

0.01 mF U/O

INC

CS

CAT 5112IC2

5V

200 mV

VCORR 499k 499k

20k

2M60647

6

5

VREF 1V

SENSOR

499k 499k

1V550 mVVSENSE

2

3

15V

5V

2M6064VOUT1V51 mV

4

11

1IC1A

VSHIFT100 mV

IC1D

IC1B

Autoreferencing circuit nulls out sensor errorsChuck Wojslaw, Catalyst Semiconductor, Sunnyvale, CA

This autoreferencing circuit nulls out output errors at a sensors reference (ambient) condition.

F igure 1



ideasdesign

Often in the use of products withkeypads, one or more keys becomestuckor are being pressed. For ex-ample, a cell phone in the bottom of apurse or in a hip pocket could have oneor more of its keys inadvertently pressedand held down for a considerable period.Depending on the circuit design and im-plementation of the keypad interface, thiscondition could cause excess current toflow, thereby draining the batteries inportable equipment. The circuit in Fig-ure 1 is a keypad interface that solves thisproblem by using an ultralow-power mi-crocontroller. The circuit typically con-sumes 100 nA while awaiting a key pressand consumes a maximum of only 2 mAif all keys are stuck or held down. Anadded bonus of the circuit is that it re-quires no crystal.

The circuit uses the MSP430, IC1, be-

cause it offers low power consumption,individually configurable I/O pins with

interrupt on rising or falling edges, andwake-up time of less than 6 msec. In nor-mal mode, port pins P3.0 to P3.3 drivethe rows high. The columns connect toport pins P1.0 to P1.2, configured as in-puts with interrupts enabled and set tointerrupt on a rising edge. The pulldownresistors hold the inputs low in the inac-tive state. The MSP430 then goes intolow-power Mode 4, in which the micro-controller draws 100 nA. This state con-tinues indefinitely until you depress a key.The circuit is completely interrupt-driv-en with no need for polling. When youdepress a key, the column associated withthat key receives a rising edge, therebywaking the MSP430. The timer for thedelay uses the internal digitally controlledoscillator of the MSP430, an RC-type os-cillator. The digitally controlled oscillatoris subject to tolerances, so you use a de-bounce delay to yield a worst-case mini-mum delay of 25 msec. That figure trans-

lates to a worst-case maximum delay ofapproximately 86 msec and a typical de-lay of approximately 40 msec. This rangeis eminently usable for keypad-debounc-ing purposes. After the debounce delay,the circuit scans the keypad to determinewhich key you depressed.

After you depress a key, the MSP430goes into a wait-for-release mode, inwhich it drives only the necessary row forthe key you depressed. (Other rowsswitch low.) The microcontroller recon-figures the P1.x I/O to interrupt on afalling edge, and it again goes into low-power Mode 4 and waits for the release ofthe key. Again, the circuit needs nopolling at this point. The detection of thekey release is completely interrupt-driv-en, allowing the MSP430 to stay asleepwhile the key is held, thereby reducingcurrent consumption. Once you releasethe key, the circuit again executes the de-bounce-delay routine. After the de-

bounce delay, the circuit againscans the keypad to determinewhether any other keys are be-ing held. If so, the wait-for-re-lease mode continues. When allthe keys are released, theMSP430 reverts to wait-for-press mode. During the wait-for release mode, only one rowof the keypad goes high, therebylimiting the maximum currentconsumption to the conditionin which all three keys on a sin-gle row are pressed. For a 3V sys-tem, this condition equates toapproximately 2 mA. Any otherkey press does not result in in-creased current consumption,because the corresponding rowis not in a high state. You candownload the software for themicrocontroller from the Webversion of this article atwww.ednmag.com.

1

32

456789

1011121314 15

161718192021222324252627

28TESTVCCP2.5/ROSC

P2.0ACLKP2.1INCLKP2.2/CAOUT/TA0P3.0/STE0P3.1/SIMO0P3.2/SOMI0P3.3/UCLK0

VSSXOUTXIN

RST/NMI

P1.7/TA2/TDO/TDIP1.6/TA1/TDIP1.5TA0/TMS

P1.4/SMCLK/TCKP1.3/TA2P1.2/TA1P1.1/TA0

P1.0/TACLKP2.4/CA1/TA2P2.3/CA0/TA1

P3.7P3.6

P3.5/URXD0P3.4/UTXD0

4.7M4.7M 4.7M

1N4148

1N4148

1N4148

1N4148

VCC

100k

324-KEY KEYPAD

IC1

F igure 1

Low-power keypad consumes only 100 nAMike Mitchell, Texas Instruments, Dallas, TX

This keypad interface draws only 100 nA in standby mode and avoids stuck-key problems.



ideasdesign

Aconstant-fraction discrimina-tor usually performs the time-tag-ging of impulsive events, whichhave a peaking time of the signal ampli-tude. The implementation ofthis technique requires a de-lay in the input signal of approximatelythe same amount as the signals risetime. You can attain this delay by usinga coaxial cable of an appropriate length.For many applications, in which the risetime for impulsive events is 1 to 10 msec,you must consider alternative solutions,because of the length of the cable youdrequire. Figure 1 shows the typical out-put from a spectroscopic amplifier,where the presence of a large amount ofdetector noise with Gaussian distribu-tion is a limiting factor for system per-formance in amplitude and timing res-olution. The time-tagging of such pulsesis subject to two well-known types of er-rors: the jitter related to the noise and

the walking time arising from the am-plitude variation of the signals. You caneliminate the walking time by differen-tiating the signal and detecting the zerocrossings. The jitter is related to the

noise around the zero-crossing line.In Figure 2, an arming discriminator

with a fixed threshold of 100 mV(53V

RMS(NOISE)) enables the IC

1, a MAX-

941 zero-crossing discriminator, via the

F igure 1

Time-tag impulses with zero-crossing circuitElio Rossi, Itesre-CNR, Bologna, Italy

A spectroscopic amplifier produces differentiated signals (lower traces) in response to inputimpulses (upper traces).

0.2V, 5 mSEC

0.1V, 5 mSEC

20 mVRMS

+330 pF

10k 10k

21 MAX942

21 MAX942

21 HC4538

21 HC4538100 pF

10k

10k

1k

10k

33k

10k

3.3k

1k

+

2

+

+

2

2

5 8

3

24

1

67

0.1 mF

0.1 mF

0.1 mF

0.1 mF

+

+

23V

0.1V

47k

1N4148

0 TO 10V

1k1k

C13

2

41

7

65

MAX941

INPUT

ENABLE/LATCH

0.1 mF

13

11

12

8

CI

2T

+T

RC

IC2B

IC2A

CX

Q

Q

CI

2T

+T

RC CX

Q

Q

14 15

10

9

100 pF5.6k

DIGITALOUTPUT

12

3

5

4

7

6

C218k

10 mF

16

5V, 1 mA

0.5 mSEC

IC1

IC3B

IC3A

F igure 2

A discriminator and a zero-crossing detector eliminates walking-time error for impulsive events.


ideasdesign

first half of IC2, an HC4538 reset-

table monostable multivibrator.The propagation delay in theseICs allows enabling the zero-crossing dis-criminator when the differentiated signalis well over the baseline noise for the fullrange of the input signal. The positive-going output pulse from IC

3, a MAX941,

corresponding to the zero-crossing time,reaches the output with a fixed length of0.5 msec, set by the second monostablemultivibrator. This second multivibratorresets the first and latches the MAX941 atthe high output level until a newtrigger arrives from the armingdiscriminator. In this way, you avoid spu-rious triggers at the beginnings and endsof input pulses. The upper-threshold dis-criminator output, with a minimum out-put length of 5 msec, serves to veto the0.5-msec output and works even for high-ly saturated input signals. Because of theinput configuration of the MAX942, it isnecessary to reduce the upper thresholdlevel to less than 2.8V. Figures 3 and 4show the timing sequences for 0.2V and10V input signals, respectively.

You can obtain the same resultsusing many different implementations ofthe circuit, depending on the ICs avail-able off the shelf. For example, you cansubstitute the MAX941 with a commondiscriminator and a CMOS analogswitch to commutate the threshold froma positive voltage to ground. A single flip-flop then completes the circuit. This de-sign uses an amplification stage withback-to-back limiting diodes in front ofthe zero-crossing discriminator. Table 1shows the results, with comparisons tothe shaping-time value of 3 msec. Youmeasure the walking time and jitter us-ing a pulse generator, preamplifier, shap-ing amplifier, time-to-amplitude con-verter, and multichannel analyzer. Figure

5 shows just three of the many his-tograms used to calculate the walkingtime and jitter results.

F igure 3

F igure 4

6000

5000

4000

3000

2000

1000

700 800 900 1000 1100 1200

0

COUNT

CHANNEL

SHAPING TIME: 3 mSEC9.915 nSEC/CHANNEL

IN 1V

IN 0.5V

IN 0.2V

F igure 5


For 200-mV input, Trace A is the output from the arming discriminator, Trace 1 is the Enable signalfor the MAX941, and Trace 2 is the signal output.

These jitter histograms are for input signals of 0.2, 0.5, and 1V.

For a 10V input, Trace A is the output from the lower level discriminator, Trace 1 is the Enable sig-nal for the MAX941, and Trace 2 is the output from the upper level discriminator.

TABLE 1MEASUREMENT RESULTS AT 1 kHz AND WITH 20 mV RMS OF NOISEShaping Peaktime time C1 C2(mmsec) (mmsec) (nF) (nF) Jitter 0.1VIN

1 0.2VIN 0.5VIN 1VIN 2VIN 5VIN 10VIN Walk1 2 0.47 0.33 ss (mmsec) 0.249 0.145 0.06 0.029 0.015 0.009 0.006 0.06 mmsec3 6 1 1 ss (mmsec) 0.594 0.395 0.156 0.081 0.042 0.017 0.009 0.2 mmsec2

6 12 2.2 2.2 ss (mmsec) 1.608 0.939 0.372 0.195 0.096 0.04 0.021 1.1 mmsec2

3 6 1 1 Amplifier 0.664 0.417 0.161 0.081 0.042 0.017 0.009 0.47 mmsec3


ideasdesign

The achievable accuracy for sys-tems with multiple ADCs dependsdirectly on the reference voltages ap-plied to the ADCs. Medical-ultrasound-imaging systems, for example, common-ly include a large number of ADCs in thesystems beam-former electronics, withthe ADCs usually organized in groups of16, 24, 32, and so on. To obtain maximumbeam accuracy, you must minimize er-rors in the ADC path. Poor accuracy ofthe reference voltages of the individualADCs degrades the overall system accu-racy.Another source of degradation is thedistributed load, which comprises manyindividual resistive and capacitive loads.Several approaches are available to pro-vide the reference voltage for such ADCarrays:

Individual on-chip references.Though this approach offers a con-venient local connection to eachADC, it can result in relatively poor

matching among the converters. A single external reference voltage

applied to all ADC reference inputs.Such a configuration allows you toengineer an external reference volt-age of arbitrary accuracy but incurserrors from the small variationsamong the internal ladders of theADCs.

An external reference directly driv-ing the ADCs reference-ladder taps.This option delivers maximum gainaccuracy by directly controlling thereference voltage applied to eachADC ladder. However, it requiresdriving the relatively low resistanceof the ladders. Moreover, someADCs do not allow access to that in-ternal bias point.

ADC ACCURACY

In many applications, gain and noiselevel have a major effect on ADC accu-

racy. The gain of an ADC is in effect theslope of its transfer function, which re-lates analog inputs to the allowable rangeof digital-output codes. One way toquantify gain is to measure the full-scaleinput range, which is a direct function ofthe reference-voltage level. For medical-ultrasound-imaging systems, variationsin the full-scale ranges of the ADCs cancause errors in beam formation. Thevariations also affect the ADCs clippingpointan effect that may be importantis certain signal-demodulation schemes.An ADCs noise level determines its us-able dynamic range. This dynamic rangeshould be as great as possible. The refer-ence-noise component of ADC noise canbe additive or multiplicative. Local by-pass capacitors on the individual ADCscan easily filter additive noise. Multi-plicative noise, on the other hand, is moreinsidious. For ultrasound applications,reference noise in the audio-frequency

REFOUT

REFIN

REFP

REFN

COM

ADC 1

REFOUT

REFIN

REFP

REFN

COM

ADC N

0.1 mF

0.1 mF

0.1 mF 0.1 mF

0.1 mF

0.1 mF0.1 mF

0.1 mF

1 mF100 mF

0.1 mF

0.1 mF 2.2 mF10V

0.1 mFIC1

IC2

10-Hz LOWPASSFILTER 10-Hz LOWPASS

FILTER

1

12

23 4

3 516.2k +

2

162

NC

NC

29

31

32

1

2

29

31

32

1

2

3V

3V 2.048V

F igure 1

Circuit provides reference for multiple ADCsRon Gatzke and Tanja Hofner, Maxim Integrated Products, Sunnyvale, CA

For ultrasound applications, a single, low-noise reference circuit can drive as many as 1000 ADCs.


ideasdesign

REFOUT

REFIN

REFP

REFN

COM

ADC 1

REFOUT

REFIN

REFP

REFN

COM

ADC 2

0.1 mF

1 mF

0.1 mF 0.1 mF

0.1 mF

10 mF6V

0.1 mF2.2 mF

10V

0.1 mF 0.1 mF 0.1 mF

IC1IC2A

11

11

11

4

4

4

+

2

NC

NC

29

31

32

1

2

29

31

32

1

2

3V

3V

0.1 mF

IC2B

5

6

+

2

IC2C+

2

2V AT 8 mA

1.5V AT 0 mA

1V AT 28 mA

47

10 mF6V

330 mF6V

330 mF6V

330 mF6V

47

10 mF6V

47

13

2

3V

3V

3V

7

8

1.47k

1.47k

1.47k

10

9

21.5k

21.5k

21.5k

21.5k

21.5k

12

3

2V

1.5V

1V

F igure 2

For ultrasound applications, a precision, low-noise reference circuit can drive as many as 32 ADCs.

spectrum can modulate large station-arysignals in the RF spectrum. Such sig-nals arise from stationary tissue in the ul-trasound target.

Audio modulation produces sidebandsin the RF signal that a Doppler detectorcan demodulate, producing audio tones.To estimate the amount of audio noisetolerable in an ultrasound application,assume a nearly full-scale RF signal ap-plied to a 10-bit ADC such as theMAX1448. The devices dynamic range ofalmost 60 dB equates to a noise floor of260 dBFS (relative to full scale). You cannormalize that noise level to a 1-Hzbandwidth. The Nyquist bandwidth foran 80-MHz sampling rate is 40 MHz. Thecorrection factor is =40 MHz576 dB,which places the ADCs noise floor at260 dBFS276 dBFS52136 dBFS. Be-cause a conservative design requires thereference-voltage noise to be at least 20

dB lower (2156 dBFS), a 2V reference re-quires an extremely low noise level of 33nV p-p (approximately 8 nV/=Hz).

A multiple-ADC array may require amore accurate reference voltage than theone internal to each converter. The ref-erence voltage internal to MAX144x con-verters, for example, has an accuracy of61%. The following two circuits are ref-erence designs for such arrays. They fea-ture a single, common low-frequencynoise filter, and they offer high-frequen-cy noise suppression via local decouplingcapacitors connected to individualADCs.

SINGLE EXTERNAL REFERENCE

Multiple-converter systems based onthe MAX144x family are well-suited foruse with a common reference voltage.You can the REFIN pin of these con-verters to an external reference source

and thus eliminate the need for any cir-cuit modification. Moreover, the highinput impedance of REFIN (even ofmultiple REFIN terminals connected inparallel) results in only a small load-cur-rent drain. Figure 1 shows a precisionsource, such as the MAX6062, that gen-erates an external dc level of 2.048V andexhibits a noise-voltage density of 150nV/=Hz. The output of the IC passesthrough a one-pole lowpass filter with 10-Hz cutoff frequency to op ampIC

2, which buffers the reference. The

buffered reference voltage then passesthrough a second 10-Hz lowpass filter.IC

2exhibits a low offset voltage for high

gain accuracy and a low noise level. Thepassive 10-Hz filter following the bufferattenuates noise produced in the volt-age-reference IC and buffer stage. Thefiltered noise density, which decreaseswith frequency, meets the noise levels re-


ideasdesign

quired for precision-ADC operation.Converters of the MAX144x family

specify a typical gain error of 64.4%(better than 60.5 dB). This performanceis better than the gain tolerance of allother building blocks in the signal pathof an ultrasound receiver. Note that thecircuit in Figure 1 ensures proper pow-er-up/power-down sequencing, becauseall active parts receive their power fromthe same supply-voltage rail. This ap-proach yields excellent gain matchingand an extremely low noise level withminimal circuitry. The circuit shouldprove adequate in many applicationsthat require multiple gain-matchedADCs.

PRECISION EXTERNAL REFERENCE

For applications requiring more strin-gent gain matching, the MAX144x fam-ily fills the bill. In Figure 2, connectingeach REFIN to analog ground disablesthe internal reference of each device.Youcan thus directly drive the internal refer-

ence ladders from a set of external refer-ence sources. These voltages can have anarbitrarily tight tolerance; the ADCs typ-ically track them within 0.1%. ADCs ofthis family have 4-kV resistance acrossthe ladders reference connection, so itseasy for the reference source to drive theload, even with many ADCs connected inparallel. IC

1generates a dc level of

2.500V, followed by a 10-Hz lowpass fil-ter and a precision voltage divider. Thebuffered outputs of this divider provide2, 1.5, and 1V, with an accuracy that de-pends on the tolerances of the divider re-sistors. The quad op amp IC

2, selected for

its low noise and dc offset, buffers thethree voltages.

The individual voltage followers con-nect to 10-Hz lowpass filters, which filterboth the reference-voltage and buffer-amplifier noise to a level of 3 nV/=Hz.The 2 and 1V reference voltages set thedifferential full-scale range of the asso-ciated ADCs at 2V p-p. The 2 and 1Vbuffers drive the ADCs internal ladder

resistances between them. The load is 4kV divided by the number of ADCs inthe circuit. As an example, 32 ADCs draw8 mA from the supplies, a load currentthat is well within the capability of IC

2.

The gain accuracy of the configuration inFigure 2 can be almost arbitrarily tight,depending on the accuracy grade of IC

1

and the tolerances of the resistors in thevoltage divider. The gain matching of theADCs in such a configuration is typical-ly 0.1%. With a noise level below 3nV/=Hz at 100 Hz, this circuit providesexemplary performance. As in Figure 1,the common power supply for all activecomponents removes any concern aboutpower-supply sequencing.


Figure 1 shows how to position amechanical device into four discretepositions but with only two free out-puts and one free input from the control

system. The position depends on a set ofcams and four corresponding limitswitches. The 24V-dc motor comes witha worm gear. Darlington transistors Q

3to

Q6

and resistors R7

to R12

form an H-bridge that drives the dc motor, M.Diodes D

3to D

6 protect these transistors

from inductive spikes. The outputs of thecontroller (not shown), connected to theControl 1 and Control 2 inputs, haveopen-collector structures that connectControl 1, Control 2, or both to groundupon activation. If you activate neitherControl 1 nor Control 2, Q

3 and Q

5con-

duct, receiving base current through R7

and D1

and R10

and D2, respectively. This

action short-circuits (brakes) the motor.In this case, Q

4 and Q

6 are turned off. Op-

tocouplers IC1

and IC2

are on, therebyshort-circuiting the limit switches, M

A

and MB.

Activating only one control input (forexample, Control 1), if the cam does notpush open the corresponding limitswitch, E

A, causes Q

3to switch off and Q

4

to switch on with R8

limiting the basecurrent. Thus, the motor rotates until thecam pushes open limit switch E

A(Posi-

tion 1 in Figure 2). The limit switch, MA,

has no influence because optocoupler IC1

short-circuits MA

when Control 2 is in ahigh state. A similar, symmetrical opera-tion occurs if you activate (ground) Con-trol 2. In this case, the motor rotates topush open limit switch E

B(Position 4).

To bring the motor to one of the middlepositionssay, Position 2you use thefollowing procedure:

1. With Control 2 high (not connect-ed), activate (ground) Control 1. Themotor rotates until it pushes openlimit switch E

A. The bases of Q

3

MA

EA

CONTROL 1 CONTROL 2

MB

EB

D1

D3D5

D2Q5

VCC

R7 Q3

R8 R9

R13

R12 R11

IC1

IC2

M

IC3

D4 D6Q4 Q6

R10

R4

Q2

R5

R6

IC1

IC2

F1

R3

R1

R2

Q1

NOTES:D1, D2: 1N4148 Q1, Q2: 2N2222, 2N3904...

Q3, Q5: BDX33CQ4, Q6: BDX34CIC1 TO IC3: PC814, H11AA1, SFH6206-2...

D3 TO D6: 1N4937R1, R2, R4, R5, R9, R12: 10 kV, 0.25WR7, R8, R10, R11: 3.3 kV , 0.25WR3, R6, R13: 1.5 kV, 0.6W

F igure 1

Motor-control scheme yields four positions with two outputsJean-Bernard Guiot, DCS AG, Allschwil, Switzerland

This simple circuit provides four-position motor control with two inputs.

www.ednmag.com February 7, 2002 | edn 99

ideasdesign

Motor-control scheme yields four positions with two outputs ..................99

Single switch controls digital potentiometer ..................................100

Versatile power-supply load uses light bulbs ............................................102

Two-transistor circuit replaces IC..............104

Digital current source is nonvolatile ................................................106

Closing the loop deepens notches ..........108

Hints and kinks for USB coding................108


100 edn | February 7, 2002 www.ednmag.com

ideasdesign

through Q6

are all high.2. Activate (ground) Control 2. Thebases of Q

5and Q

6switch low. (M

B

and EB

are closed.) The motor rotatesin reverse until M

Acloses. At this

time, all bases are low. Q4

and Q6

short-circuit the motor toground, thereby braking it toa stop.

First activating Control 2 and thenControl 1 brings the motor to Position3, the edge of cam M

B. Otocoupler IC

3re-

mains on as long as the motor receivesvoltage. The output of IC

3connects to a

feedback input of the controller. Thus,you can control whether the motor is ro-tating or stopped through this input. F

1,

a polymer-based resettable fuse, protectsthe motor and the circuit against over-

current conditions, such as a stalled mo-tor. You can mount the circuit in Figure1 on small machine tools, such as a work-piece changer. The values of the compo-nents are not critical. The transistors arepreferably Darlington types and, like thediodes, should have adequate ratings toaccommodate the power-supply voltage

and the motor current. (Dont forget thehigh inductance of the motor.) The com-ponents in Figure 1 accommodate a 24V-dc, 2.5A motor.

Is this the best Design Idea in this issue? Select at www.ednmag.com.

POSITION 1 POSITION 2 POSITION 3 POSITION 4

EA

MAMB

EB

F igure 2

Cams operate the limit switches in Figure 1, producing four discrete positions.

The control of electronic poten-tiometers in most todaysapplications comes fromcontroller-generated signals. However, asignificant number of applications existthat require adjustments using manual,front-panel controls. The circuit in Fig-ure 1 uses one IC, one switch, and 10 dis-crete components. It implements the in-terface of a single DPDT, momen-tary-contact rocker switch to a DPP (dig-itally programmable potentiometer). TheCatalyst DPP has a three-wire incre-ment/decrement interface. The tradi-tional way to implement the front-panelcontrols for potentiometers with thistype of interface is to use two single-pole,single-throw switches. Switch S

1reduces

the front-panel hardware by half. The ac-tion of the switch is natural for the con-trol of increment-up/increment-downpotentiometers.

IC1A

and IC1B

, which implement an R-S flip-flop, control the potentiometerswiper directionup or down. The out-put of the flip-flop reflects the up/downposition of S

1. The potentiometers wiper

advances on the falling edge of the signal

driving the INC input of the DPP. Theclock output of IC

1Ddrives INC. The

clock becomes enabled when you depressthe rocker switch either up or down. TheRC networks at the inputs of IC

1Cde-

bounce the switches. If you momentari-ly depress the rocker switch, the clockgenerates one pulse. If you continuously

depress the rocker switch, the clock free-runs at a frequency of approximately1/R

1C

1.

1 mF 1 mF

DPDTMOMENTARY

CONTACT

MOMENTARY

MOMENTARY

S1A

S1B

R100k

C4.7 mF

5V100k10k

IC1C

IC1B

IC1A

100k

100k10k

100k

U/D

INC

CS

5V

CAT5114

74HC132IC1D

5V

5V

5V

OFF

F igure 1

Single switch controls digital potentiometerChuck Wojslaw and Gary M Craig, Catalyst Semiconductor, Sunnyvale, CA

A single switch is all you need to control a digitally programmable potentiometer.



ideasdesign

Improvising loads for bench-testingand designing power supplies is oftena frustrating and sometimes haz-ardous experience. When you push largepower resistors to their limit, they tendto burn benches and melt solder con-nections. Many electronic loads are onthe market but are usually expensive andof laboratory-type precision and oftenrepresent overkill for the average de-signer. Incandescent light bulbs make ex-cellent loads, able to handle largeamounts of power. Moreover, they comein small packages and require no heatsinks. Furthermore, because they lightup, you obtain instant feedback, ratherlike an analog versus a digital meter. Thedrawback is that the resistance of an in-candescent lamp changes dramaticallywith the power input. The power into theload must therefore be controllable overa broad range, if the bulb is to be a use-

ful current sink. A simple approach tothis control problem is to pulse-width-modulate a power MOSFET in serieswith the load. This design uses a four-rail, 100W supply with outputs of 5, 12,and 615V. For these voltage and powerlevels, 50W, 12V bulbs provide a suitableload. This application required threebulbs connected in parallel (Figure 1).Many automotive-supply dealers offer50W, 12V bulbs.

Because these bulbs screw into an or-dinary 115V light socket, you can createa virtually unlimited combination ofloads. The use of old-fashioned porce-lain-type sockets wired in parallel allowsyou connect any number of bulbs in theload circuit. The circuit in Figure 1 ad-dresses supplies of 1 to 24V output levels,of positive or negative polarity, with pow-er levels as high as 150W. You can use thesame basic approach to load higher volt-

age supplies by using 115V light bulbsand appropriately sizing the powerMOSFET and other components. Thecircuit uses a standard PWM 3843 IC,IC

1, in open-loop mode. Potentiometer

VR1

controls the duty cycle over its fullrange. The frequency is not critical and isapproximately 37 kHz with the valuesshown in Figure 1. A small, modularplug-in transformer provides power, butyou can use any source of approximately18V dc at 50 mA.

T1

provides isolated drive to the pow-er MOSFET, Q

1. The transformer allows

you to load negative as well as positivesources. The various components in thegate circuit provide efficient drive to Q

1

over a broad range of duty cycles. The L1

choke isolates the input from the switch-ing pulses in Q

1. You could use either an

analog or a digital current readout. Thisdesign uses an LED readout salvaged

+

+

++

8 7 6 5

1 2 3 4

IC13843

VR11k, 10 TURN

1.2k

2N4401

10k

4.7 nF

470

100 mF25V

1000 mF25V

470 mF35V

0.22 mF 0.22 mF

47.5W

10

T1COILCRAFTSD 250-1

2N4402

1N4148

20V180

4.7k

Q1IRF3710

R1SELECT

L150 mH, 5A

50W12V

50W12V

50W12V

4.7 nF

47

TO CURRENT METER

TO NEGATIVE INPUT

TO POSITIVEINPUT

1N4148

2 +115 AC 12V AC

ON/OFF

F igure 1

Versatile power-supply load uses light bulbsWilliam Sloot, Computron Display Systems, Mount Prospect, IL

Incandescent light bulbs provide convenient loads for testing power supplies.


ideasdesign

from an old power supply. You must sizethe current resistor, R

1, for the power dis-

sipation and the requirements of thecurrent meter. In this application, threemetal-oxide, 0.1V, 2W resistors con-nected in series met the requirements(maximum current of 4A).You must fas-

ten Q1

to a heat sink adequate for the ap-plication. The circuit in Figure 1 uses anAavid (www.aavid.com) 530101B00100.This heat sink is a U-shaped radiatormeasuring approximately 1.753175 in.on each side. Applications requiringhigher currents could use two MOSFETs

in parallel. The gate-drive scheme shownhas enough power to drive two MOSFETs.


Linear Technologys recently intro-duced LTC4300 chip buffers I2Cclock and data lines to and from ahot-swappable card. This task is difficultbecause the IC must work bidi-rectionally, meaning that you cansimultaneously and actively drive bothsides. However, as is sometimes the case,you can replace a complicated circuit bya simple one without much loss of per-formance. For example, transistors andresistors replace the entire IC (Figure 1).The circuit handles only the clock signalor only the data signal. Two npn transis-tors, connected head-to-head, form theheart of the circuit. I2C signals come fromopen-collector or open-drain outputs, socan only pull down (sink current). WhenEnable is high, a low-going SCL signaldrives the emitter of one of the transis-tors as a common-base amplifier. The 10-kV resistor in the base circuit providesenough current to saturate the transistor

and drop the VCE

voltage to approxi-mately 0.1V, thereby pulling the otherside low.

The circuit acts like an efficient diode.With Enable low, the hot-swappable sidehas no effect on the signal, with or with-out power applied. The two-transistorcircuit offers the additional benefit of act-ing as a level translator between two log-ic levels. This example shows a buffer-translation between a 3.3V system and a

5V card. For proper operation, the Enableline must not go higher than the lower ofthe two supply voltages. Figures 2a and bshow operation at 100 kHz. Some edgeglitches and overshoot, stemming fromtransistor-junction capacitance, are evi-dent in the 3.3V signal, but these slightdefects should be tolerable in many low-cost applications. References 1 and 2treat similar level-translation circuits.

References1. Hagerman, Jim, Two transistors

form bidirectional level translator,EDN , Nov 7, 1996, pg 114.

2. Poon, CC, and Edward Chui, Low-voltage interface circuits translate 1.8V to5V, EDN, Nov 5, 1998, pg 119.

SCL SCL*

ENABLE

3.3V

10k

10k10k

5V

F igure 1

Two-transistor circuit replaces ICJim Hagerman, Hagerman Technology, Honolulu, HI

This circuit is an I2C-compatible, hot-swappabletranslator/buffer.


The 5V side (a) and the 3.3V side (b) drive operation with the circuit.

F igure 2

(a)

(b)


ideasdesign

Digitally programmablecurrent sources thatfeature automatictrimming and retain the settingdespite power-down cycles areuseful in applications such as RF-and laser-communications driv-ers. The circuit in Figure 1, for ex-ample, is particularly suited forsetting the drive current for theoptical pump in widely tunableVCSELs (vertical-cavity surface-emitting lasers). These lasers aresuitable in systems using wave-length-agile DWDM fiber-opticcommunication links. The circuitin Figure 1 delivers a stable drivecurrent that derives its controlfrom DPP (digitally programmedpotentiometer), a Catalyst Semi-conductor (www.catsemi.com)CAT5512. For the circuit valuesshown, you can set the outputcurrent to 500 mA to 1A; howev-er, you can alter this span over awide range by the judicious selec-tion of sense resistors R

1and R

2.

The unique features of theCAT5512 make possible the lowcomponent count (two chips andtwo resistors). The device com-bines a 5-bit-resolution, 100-kVDPP, a nonvolatile EEPROM forlong-term storage of the DPP setting, anda unity-gain analog-wiper-buffer ampli-fier. The DPP provides a complete digi-tal interface of the LT317 precision regu-lator chip to the R

1, R

2split

current-sense-resistor network. The re-sult is a robust, precision programmablecurrent source with 5-bit resolution overa flexible I

MINto I

MAXrange. The basis of

circuit operation is the fact that the LT317regulator generates the current necessaryto maintain a constant 1.25V across theeffective sense resistance: R

11(12p)R

2,

where p is the DPP setting: 0, 0.032,0.064, 0.097, ..., 0.98, 1. In this way,I

151.25V/(R

11(12p)R

2) over the range

of IMIN

51.25V/(R11R

2) for p50 to

IMAX

51.25V/R1

for p51. The pertinent

design equations are R151.25V/I

MAX, and

R251.25V/I

MIN2R

1.

Note that the R2

equation is an ap-proximation, based on the assumptionthat R

2is much lower than 100 kV, the

parallel DPP resistance. The full expres-sion for R2 is:R

251/(1/((1.25V/I

MIN)2R

1)21/100 kV).

You exert control of the DPP settingpand storage of the setting in non-volatile EEPROMvia the three-wiredigital interface, as described in theCAT5512 data sheet. The load-voltage-compliance limit is a function of the W

1

and W2V+ supply jumpers, connected to

the LT317. The maximum output voltageis the difference between the LT317s in-put voltage and the sum of the LT317s

dropout voltage (approximately 2V) andthe voltage drop across the R

11R

2series

resistance: VMAX

5V+ 1 2V2IMAX

(R11

R2). In the circuit in Figure 1, this voltage

is V+ 1 4.5V. This arithmetic leads to aV

MAXof only 500 mV if you use the W

1

option and V+ = 5V. This compliancefigure may be insufficient for some ap-plications. If, by contrast, you choose theW

2option and V+ is greater than 7.5V

(not necessarily regulated),VMAX

increas-es to a much more adequate 2.5V.

DIGITAL PROGRAM INTERFACE

4

7

2

8

1INC

CS

U/D

12P

P

H

W

3

5

6100k

L

LT317W1

W2

V1 (OPTIONAL)

IN OUT

VR1.25V

R1

R2

1.24

1.24

LOAD(EG, LASER DIODE)

JL4VR

(R1+(11P)R2).

VR

2.5 TO 6V

CAT5512-00DPP

ADJUST

NOTES: IMAX=VRR1

,

VRR1+R2

IMIN= (R2


ideasdesign

Notch filters re-move a sin-gle unwant-ed frequency from aninput signal. They are alsoa vital component ofpulse-shaping networks,such as time-averaging fil-ters. You can tune a state-variable filter over a widerange by changing thetime constants of its inte-grating amplifiers (refer-ences 1, 2, and 3). Text-books focus on its high-pass, bandpass, and low-pass outputs, but theysometimes fail tonote that subtract-ing the bandpassoutput from the input sig-nal creates a notch filter.The attenuation of suchan open-loop notch filteris limited by how well thecomponents match; typi-cally, its approximately 40dB. Figure 1 shows a stan-dard state-variable filterwith an amplifier, IC

4,

added to invert the bandpass output.Youcan implement a notch filter by adding afurther amplifier to sum the input signaland the output of IC

4.

An alternative is to move the input to

R9

and to take the notch output from theoutput of IC

4. Closing the loop around

the notch filter makes the depth of thenotch depend only on the gain of the in-tegrating amplifiers. Replacing R

5and R

6

by differential-input,current-output multi-pliers (for example,the Harris HA2547)creates the tunablenotch filter in Figure2. The time constantsT

1and T

2 are the

products of the valuesof the integrating ca-pacitors and the mul-tipliers transimped-ances. In Figures 1and 2, R

3controls the

width of the notch.

References1. Napier, Tom,

Multipliers imple-ment tunable filters,EDN , March 16, 1992,pg 131.

2. Siu, Chris, De-sign innovations pro-vide for voltage-tun-able, state-variableactive filters for mega-hertz ranges, EDN,Sept 28, 1995, pg 117.

3. Napier, Tom,Take tunable lowpass filters to newheights, EDN, Jan 15, 1998, pg 145.

_

+

_

+ _

+

_

+

R1

R2

R4

IC1IC2

IC3

IC4

R5HP

C1 C2

BPR6

R7

R9

R3

R8

INPUT

NOTCHVN

LP

NOTES: R14R24R4,T14R5C1, T24R6C2, AND

R74R84R9,

VNVIN

1 41`s2T1T2

1` R2R3

sT2` s2T1T2.

VIN

F igure 1

Closing the loop deepens notchesTom Napier, North Wales, PA

Changing connections makes the depth of the notch depend only on the gain of theintegrating amplifiers.

__

+

+_

+

_

+

R3

R2

R1BP

VNNOTCH

IC4IC2

IC1VIN

T2

T1

LP

NOTE: R14R2, AND VNVIN

1 41`s2T1T2

1` R1R3

sT2` s2T1T2.

+

_IC5

IC3

F igure 2

Replacing two resistors by multiplier ICs results in a tunable notch filter.


Hints and kinks for USB decodingBert Erickson, Fayetteville, NY

The USB is a serial data-transmissionsystem that uses cables to connect pe-ripheral equipment toPCs. All new computershave two or more USB re-ceptacles, and the predic-tions are that they will re-place most of the legacyreceptacles on older PCs.The 1.0 and 1.1 standards

for USB were for 1.5 and 12 Mbps at low-and full-speed rates, respectively. These

standards targeted low- and medium-speed peripherals. The latest 2.0 standard

is for a 480-Mbps rate that willaccommodate many high-speed devices along with theprevious low- and full-speedrates. At the PC-accessible USBreceptacle and at the peripher-al, if it has a receptacle, the sig-nal has the format of differen-

TABLE 1BINARY VERSUS DIFFERENTIAL-NRZI CODEBinary Differential NRZI

b(n111) b(n) d(n111) d(n) or d(n111) d(n)0 0 1 0 0 10 1 0 0 1 11 0 0 1 1 01 1 1 1 0 0

tial-NRZI (nonreturn-to-zero-inverted)code.After conversion (with a simple cir-cuit or test probes) of this differential tosingle-ended signal, the signalbecomes a waveform that as-sumes the voltage levels used to recognizeones and zeros in computer code.

In this NRZI waveform, a transitionbetween the d(n21) and d(n) bits de-codes to a binary b(n)50 data bit. Notransition decodes to a binary b(n)51bit. However, when you display the d(n)waveform on an oscilloscope of a logicanalyzer, it is difficult for an observer todecode it back to the originating binarywaveform, or vice versa. In this situation,you may doubt your judgment and turnto dedicated test equipment to make theconversion. Much of the human problemoccurs because NRZI decoding dependson knowledge of the previous and cur-rent input bits to determine a value forthe current output bit. In the encodingdescriptions in most textbooks and tech-nical articles, the transitions receive pass-ing mention, and the material presents apair of waveforms with little or no elab-oration. The following suggestions in-

volve some computer statements andlogic circuits that provide a different wayto effect the conversion.

Table 1 shows all the combinationsthat can exist in NRZI encoding. For thedifferential-NRZI-d(n)-to-binary-b(n)code conversion, the following observa-tions apply:

The conversion is independent ofb(n21).

If d(n21)d(n), then b(n)50. If d(n21)5d(n), then b(n)51. Or, simply, b(n)5d(n) XOR NOT

d(n21).You can perform the conversion by us-

ing an XOR gate and a 74LS74 D-type,positive-edge-triggered flip-flop (Figure

1a). The flip-flops Set and Clear termi-nals connect to V

CC, and you do not need

to reset either one. For the binary b(n)to differential NRZI d(n) conversion, weoffer the following observations:

The conversion is not independentof d(n21).

d(n)5d(n21) unless b(n21)50 AND b(n)50, then

d(n)5NOT d(n21), or b(n21)51 AND b(n)50, then

d(n)5NOT d(n21).You can perform the conversion by us-

ing an XOR gate and a 74LS74 D-typepositive-edge-triggered flip-flop (Figure1b). The flip-flops Set and Clear termi-nals connect to V

CCafter you use them to

set d(n) to its proper initial value. For allinput-data sequences that keep repeat-ing, you must select the last and first bitsto produce the first output bit. You candownload a computer program thatconfirms the decoding from the Web ver-sion of this article at www.ednmag.com.


ideasdesign

C

C

QCP

CP

D

D

S

S

Q

Q

CLK

CLK

d(n) DATA

b(n) DATA

Q

b(n)

d(n)

(a)

(b)

F igure 1

Simple circuits perform NRZI-to-binary (a) andbinary-to-NRZI (b) conversion.


Apopular category of aiming/pointing aids is the reflex, orred-dot, sight. This systemfinds use in such diverse applications asastronomy, archery, and shooting. In thereflex sight, light from an internalsourcetypically a high-intensity redLEDreflects from a curved, transpar-ent optical (reflex) element throughwhich you view the target. The result ofthis geometry is that the image of theLED (the red dot) appears superimposedon the target image, thus indicating thepoint of aim. When you correctly adjustthe aiming point of the telescope, bow, orgun, the target and LED images coincide.The reflex sight offers several advantagesover competing pointing technologies,such as telescopic and open sights. Thesebenefits include rapid and intuitive tar-get acquisition, noncritical eye position-ing, and a wide field of view.

For best sight performance, the inten-sity of the red-dot light source must atleast roughly match the illumination lev-el of the target. Otherwise, if the source istoo dim, the aim-point dot loses itself inthe brightness of the target. If too bright,the dot flares, and its apparent size in-creases, obscuring the point of aim andmaking precise pointing difficult or im-

possible. For this reason, most reflexsights require manual adjustment of thesource intensity. Although this adjust-ment is effective enough, the time and at-tention needed to optimize intensity witha manual control detracts from the fastand intuitive target-acquisition capabili-ties of the red dot. The circuit in Figure1 uses phototransistor Q

1to sense target

brightness and automatically adjust theLED output. The circuit maintains near-constant dot size over a wide range ofambient-light levels.

Potentiometer R1

divides Q1s pho-

tocurrent, IP, between the LED driver, Q

2,

and the bias transistor, Q3

(connected asa diode). The adjustment of R

1therefore

determines the ratio between drive cur-rent, I

L, and ambient (target) intensity

over the range of 1 to B, where B is the betaof Q

2(greater than 100). The prototype of

the intensity-control circuit was packagedin a small plastic enclosure attached to theside of a Compasseco Inc (www.compasseco.com) Tech Force model 90 30-

mm objective reflex sight. The light shieldmimics the field of view of the sight, sothe light that Q

1samples represents the

target intensity visible through the sight.Proper adjustment of R

1results in good

compensation of dot intensity for a widerange of both incandescent and naturallight. The circuit effectively maintains aconstant angular dot diameter of 4 min-utes of arc under outdoor ambient light-ing ranging from dark overcast to fullsunlight. The circuit also delivers similarperformance under indoor incandescent-lighting conditions. Compensation withfluorescent lamps, however, is less satis-factory because of the absence of an ad-equate near-infrared component in thespectrum of these light sources. Youcould probably fix this shortcoming byusing a suitable visible-light filter in frontof Q

1.

+9V500 mAHR

Q22N3904Q3

2N3904

Q1

IL

IP

NC

L14Q1

LIGHTSHIELD

AMBIENTLIGHT

CCW CW

100kR1

100R2

NOTE:PHOTODECTOR'SFIELD OF VIEW IS SIMILAR TO THAT OF THE REFLEX SIGHT'S.

RATIO ADJUSTMENT

SIGHT LED

F igure 1

Circuit controls intensity of reflex optical sightsStephen Woodward, University of North Carolina, Chapel Hill, NC

This simple circuit automatically adjusts red-dot intensity in reflex optical sights.


www.ednmag.com February 21, 2002 | edn 85

ideasdesign

Circuit controls intensityof reflex optical sights ..................................85

Indicator features expanded scale ............86

16-bit ADC provides 19-bit resolution..............................................88

Microcontroller emulates numerically controlled oscillator ................92

Method simplifies testing high-Q devices................................................94

Publish your Design Idea in EDN. See theWhats Up section at www.ednmag.com.



ideasdesign

Test equipment for a production lineshould be user-friendly (readidiot-proof) and should of-fer minimal test time. In many cases, thetest fixture must give an operator onlyone answer: pass or fail. Usually, two in-dicators assume this role: green for passand red for fail. In most applications, asensor transforms the tested parameter toa voltage; the test fixture must measurethis voltage and display the result. Some-times, an operator needs to observe thedynamics of the tested parameter to ver-ify that the results are inside the permit-ted green zone. Forexample, when evalu-ating a regulatedsystems behav-ior, the operator is of-ten interested in meas-uring the parametersdeviation and estimat-ing its average valueafter the processreaches steady state(Figure 1). In this situ-ation, using an analogmeter with markedred and greenzones is prefer-able to using a digitalor bar-graph LED dis-play.

Assume that therange of the testedvoltage is 4.75 to 5V.To make a voltmeterwith maximum 5Vreading by using a100-mA dc meter, you would usea series resistor of 50 kV. The me-ter scale is linear, and the tested voltagezone represents only 5% of full-scale(Figure 2). It is difficult for an operatorto observe the meter reading inside sucha narrow zone. It would be desirable toexpand the test zone to, say, 90% of full-scale (Figure 3). The circuit in Figure 4does just that. When the tested voltage,V

TEST, is lower than the threshold voltage,

V2, the diode, D

1does not conduct, and

the voltmeter comprises the microam-meter and resistor, R

1. When the tested

voltage surpasses the threshold V2, the

diode conducts, and resistor R2

connectsin parallel with R

1. The voltmeters im-

pedance decreases, thereby expanding themeasurement scale.You can calculate thevalues of resistors R

1, R

2, and R

3as fol-

lows: The voltage at the beginning of the

tested zone, 4.75V, should consume10% of the scale, with a correspon-ding current of 10 mA. Hence, ne-glecting the internal meter imped-ance, R

1equates to 4.75V/10 mA, or

475 kV. After the measured voltage exceeds

the threshold level, 4.75V, the volt-meter impedance equates to R

1,25

(524.75)V/(100210) mA, or 2.8kV.

Hence, (R1R

1,2)/(R

12R

1,2)5(4753

2.8)/(47522.8)52.8 kV, and R35

R2(V

CC/V

221)52.8 (5/4.7521)5

147V.

VOLTAGE (V)

TIME

5

4.75

TRANSIENTPROCESS

STEADY-STATE PROCESS

ACCEPTABLERANGE(GREEN ZONE)

MEASURED DEVIATION

MEDIUM VALUE

F igure 1

0

10

2030 40

50 6070

8090

100

0

1

2 3

44.75

5

V

F igure 2

0

10

2030 40

50 6070

8090

1004.75

5

V

F igure 3

VTEST

R3

R2

147

V2

D1

R12.8k475k

100 mA

VCC5VF igure 4

Indicator features expanded scaleAbel Raynus, Armatron International, Melrose, MA

Its desirable to observe deviations in values inside the acceptable green zone.

Its difficult to discern deviations from the norm when the greenzone represents only 10% of full-scale.

Expanding the green zone to 90% of full-scale makes readings mucheasier.

This simple circuit expands the acceptable testresults to 90% of full-scale.


mmA

mmA


ideasdesign

Many data-acquisition systemsrequire both high accuracyand a fast acquisition rate.These attributes allow the system to de-tect small data signals and to group moresensor channels into the same system.With more channels, the system can besmaller, less expensive, and less power-consuming. Long-distance optical com-munications and medical equipment,such as CT scanners, can benefit from afast and accurate data-acquisition system.Optical power systems, such as laserpumps, need to constantly monitor theirpower levels. In such systems, the in-coming laser-power range and the lasercontrol-loop response time are such thatthe system needs a dynamic range of 90dB or more and a sampling rate of 1Msample/sec. In CT scanners, 16- to 22-bitresolution is necessary for the data-ac-quisition system to process the large dy-namic range of the X-rays through vari-ous body tissues. A largenumber of photode-tectors (more data-ac-quisition channels) and highdata accuracy improve theimage resolution.

These two examples showthe need for relative accura-cy, as opposed to absolute ac-curacy. Although its impor-tant to be able to detect a10-nW change in an opticalpower of 1 mW, it is almostirrelevant to see the same 10-nW difference between 1mW and 1.00001 mW. How-ever the ADCs accuracy ap-pears under the integral-nonlinearity specification asan absolute error. For the bestrelative accuracy, a classic so-lution is to use a program-mable-gain amplifier in frontof an accurate ADC. TheAD7677 ADC specifies 615-ppm of full-scale nonlinear-ity (61 LSB at the 16-bit lev-el). A programmable-gainamplifier ahead of this con-verter must be able to settle

1000

100

10

10.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100

10

11

12

13

14

15

16

17

18

19

20

INPUT VOLTAGE(% OF FULL SCALE)

ACCURACY(BITS)

ACCURACY(PPM OF POINT) DATA-ACQUISITION-SYSTEM

SPECIFICATION107 PPM OF POINT61.9 PPM

F igure 1

2

+

+

+ +

++

3456

13121110191817

1

ADG758

IN1IN2IN3IN5IN6IN7IN8

A0

A2A1

EN

D

IC4

7

CHANNEL

CALIBRATION

5V

2

3

6

5

3

2 COMPLATCH

100

825

2.5V

AD8561

ADG749

AD8021

AD8021IC7

IC1

IC3

IC6

22

35

6

VCM1.25V

10 pF

AD7677

IN+

IN2

IC2

REF

REF2.5V

3739

43

C227 nF

15

590

590

5V

15GAIN

5

7

6 4

30k5k

R1

15

10 pF

1 mF

27 nFC1

84.5 590

+

+R2

F igure 2

16-bit ADC provides 19-bit resolutionAlain Guery and Charles Kitchin, Analog Devices, Wilmington, MA

Using a programmable-gain amplifier ahead of an ADC increases the accuracy of a 16-bit ADC to 19bits.

This system provides 19-bit accuracy by combining a programmable-gain amplifier with a 16-bit ADC.


ideasdesign

quickly enough with the same resolutionand speed as the ADC. It alsomust have the lowest noise pos-sible, because the amplifier sets the SNRof the data-acquisition system. To meetthese challenges, the amplifier in this de-sign uses an AD8021, an op amp comb-ing speed, accuracy, and fast settling time.The noise density of the AD8021 is only2 nV/=Hz. Figure 1 shows how the gainsettings of the programmable-gain am-plifier divide the specified accuracy of theADC. The system reaches 19-bit accura-cy when the input level is low.

Relative accuracy is normally specifiedas parts per million of reading plus or mi-nus the absolute minimum error. The cir-cuit in Figure 2 can achieve a relative ac-curacy of 107 ppm61.9-ppmmaximum error. Analog multiplex-er IC

4combines many lower band-

width channels to take advantage ofthe 1M-sample/sec sampling rate ofthe ADC. Because the programma-ble-gain amplifier presents a high in-put impedance to the multiplexer,you can cascade the multi-plexer, thus increasing thenumber of channels. The multiplex-er also provides a simple way to cal-ibrate the offset and gain errors ateach gain setting by applying a cali-bration-reference voltage to one of themultiplexers input ports. You need tocalibrate only at power-up or when op-erating conditions, such as temperature,change. The amplification chain com-prises the multiplexer, the comparator,and the amplifier on one side and theADC on the other side. The successive-approximation structure of the AD7677ADC allows the individual sections in theamplification chain to work simultane-ously. While the ADC converts one sam-ple, the comparator/amplifier can settlethe following channel. Therefore, thedata-acquisition system can operate atthe ADCs maximum sampling rate.

Shortly after the analog multiplexersettles, the fast comparator, IC

1, applies

the appropriate gain setting. The com-parators thresholds are such that the am-plifier does not saturate or clip the sig-nal after amplification by IC

6and IC

7.

The AD8561 comparator has a response

time of 7 nsec. It integrates a latch signalthat holds the gain constant during thetime the amplifier settles and the ADCacquires the signal. The usual program-mable-gain-amplifier configuration re-quires the user to predict the amplifiersgain setting before applying the signal atthe input. The programmable-gain am-plifier in Figure 2 has an autorange fea-ture that selects the most appropriateprogrammable-gain amplifier gain tomaximize accuracy without incurringsaturation or clipping. The comparatorincorporates hysteresis to reduce gain-setting change when signals are close tothe limits of an individual gain range.The circuit automatically boosts the ADCaccuracy to 19 bits while maintaining afull-speed sampling rate of 1M sam-ple/sec.

IC6amplifies the multiplexer signal us-

ing one of two possible gain settings: 1or 8. You can modify the feedback net-

work to provide different gains to amaximum of 25. The analog switch,IC

3, controls the gain setting. The high

gain-bandwidth product of the AD-8021 op amp provides more thanenough bandwidth, so its compensa-tion capacitor remains the same for allgains. Amplifier IC

7generates the dif-

ferential signal for the ADC. The set-tling times of the comparator and theamplifier and the acquisition time ofthe ADC are all significantly less thanthe ADCs full conversion period of 1

msec. The RC noise filters at the two ADCinputs, R

1/C

1and R

2/C

2, use this extra

time. These filters limit the noise band-width of the programmable-gain ampli-fier, which is the main noise source of thedata-acquisition system when IC

7 oper-

ates at a gain of 21.Figure 3 shows the circuits nonlinear-

ity. The photo shows a maximum non-linearity of 0.44 LSB and a minimum of20.37 LSB for the highest gain setting,which poses the most difficult challenge.This nonlinearity corresponds to a typi-cal error of 60.9 ppm. At a gain of 8, out-put noise is 85 mV rms. If desired, you canfurther reduce the noise by using soft-ware averaging. Figure 4 shows the com-plete data-acquisition system assembledusing the AD7677 evaluation board. Thepc-board area measures 15330 mm.


This plot shows the differential nonlinearity of a data-acquisition system for all possible ADCcodes.

The dime shows the relative size of the complete data-acquisition system.

F igure 3

F igure 4


ideasdesign

Microcontrollers commonly addintelligence or digital functions toproducts, but they can also providea variety of analog signals. An 18-pin PIC16C54 microcontroller, combined with

an inexpensive, 8-bit DAC and a simplelowpass filter, can generate sine wavesfrom dc to approximately 50 kHz with atuning resolution of 24 bits. The accura-cy and stability of the output is as good

as that of the crystal driving the micro-controller. You can connect a binary data signal to one or more PIC ports to ap-ply FSK (frequency-shift-keying), BPSK (binary-phase-shift-keying), or QPSK

GND

13

12

1115

17

181

2

16

3

4

14

10

9

8

7

6

B7

B6

B5

B4

B3

B2

B1

B0

D7

D6

D5

D4

D3

D2

D1

D0

LC

A3

A2

A1

A0

5

5

6

7

8

9

10

11

12

FREQUENCY-CONTROLINPUTS

OSC2

OSC1RTCC

MCLR

VCC

5V

0.047mF

0.047mF0.047mF

16C54

20 MHz

DAC08

1 COMP

16

15V

3

V1

V+

5V

REF+ REF1

1413 15

3.3k 3.3k0.047mF

IO

IO

1k

2

4

6800 pF

4.7 mH 1.5 mH+

TL082

_

5

1.1k

6.8k

5V

5V

6

7

8

4

2200 pF

15V

0.047mF

0.047mF

100

SINEOUTPUT

F igure 1

Microcontroller emulates numerically controlled oscillatorTom Napier, North Wales, PA

An inexpensive microcontroller and DAC emulate a numerically controlled oscillator.

LISTING 116C54 NUMERICALLY CONTROLLED OSCILLATOR-EMULATION ROUTINE


ideasdesign(quadrature-phase-shift-keying) modu-lation to the output. Figure 1 shows theemulation scheme, and Listing 1 controlsthe operation of the microcontroller. The16C54s firmware emulates a 24-bit nu-merically controlled oscillator. A fixed-length loop continuously adds the con-tents of one set of registers (the frequencycontrol) to another set (the phase accu-mulator). The phase accumulator incre-ments at a rate proportional to the de-sired output frequency and wraps aroundonce per output cycle.

With a 24-bit accumulator, the outputfrequency is f3N/[67108864(L12)],where f is the clock frequency, N is thetuning control number, and L is the num-ber of instructions in the loop. (The loopperiod is two instruction times longerthan the instruction count, L.) For ex-ample, if the PICs clock crystals fre-quency is 16.777 MHz, and the loop has30 instructions, you can set any frequen-cy to approximately 40 kHz in steps of1/128 Hz. Once per loop, the highest byteof the phase accumulator selects an out-

put sample from a 65-element look-uptable, which contains one quadrant of asine wave. To create the other three quad-rants, bit 6 determines whether to readthe table forward or backward, and bit 7specifies the output sign. An exclusive-OR operation on bit 7 with a port bit gen-erates BPSK operation. An exclusive-ORoperation on both bits 6 and 7 with portbits generates QPSK modulation. The re-sult goes to the DAC via the PICs 8-bitoutput port. A 50-kHz lowpass filter thenconverts the DACs output into a smoothsine wave.

You can preset the output frequency orload it serially via two pins of the PICs 4-bit port. You obtain FSK by using an in-put bit to select which of two frequency-control registers to use. If the twofrequencies have a large common multi-ple, as in minimum-shift keying, the ac-cumulator can be shorter, leading to ahigher output frequency for a given clockinput.Without modulation, the firmwareloop can be as short as 26 instructiontimes (Listing 1). You can insert nonop-

eration instructions to make the loop-repetition rate a convenient submultipleof the crystal frequency. For example, a31-instruction loop and a 20-MHz crys-tal yield a scale factor close to 104steps/Hz.

The code takes advantage of a quirk inthe 16C54s operation: If two addressesexist on the return stack, the first copiesendlessly into the second every time theroutine pops the second. The initializa-tion code puts two copies of the loop-start address into the return stack, caus-ing all subsequent RETLW instructionsto jump to the start of the loop. Index-ing into the look-up table with a calcu-lated GOTO instruction both supplies anoutput sample and executes a jump torestart the loop. This procedure is muchfaster than executing a CALL, a GOTO, aRETLW, and a further GOTO. You candownload Listing 1 from the Web versionof this article at www.ednmag.com.


The design of low-phase-noise oscil-lators requires careful at-tention to resonator un-loaded Q. In the construction of alow-phase-noise, high-frequency oscilla-tor, the goal is to achieve an unloaded-Qfigure greater than 400 in a reasonablepackage. Also, you need to monitor theeffect of the package and pc-boardarrangement. Shielding, inappropriategrounding, and some construction tech-niques can degrade unloaded Q. Q me-ters; various bridges, such as Maxwell andHayes; and both vector and scalar im-pedance analyzers are useful but incon-venient-to-use test instruments. Youmust carefully set up test fixturing andcalibration that duplicates the final en-vironment to obtain reasonable agree-ment with the final measured results. Asimple test set uses nothing more than

the voltage-divider relation with the de-vice under test embedded as a series trapnetwork (Figure 1).You can measure theinductors value, or calculate it fromknown equations based on the inductorsform factor, such as solenoid, toroid, hel-ical, or flat spiral. You use the inductorsvalue to select C

1, a variable, air-dielectric

high-Q capacitor. At resonance, the im-

pedance of the inductor-capacitor com-bination goes to zero

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