EDN Design Ideas 1998

EDN DESIGN IDEASEDITED BY BILL TRAVIS & ANNE WATSON SWAGER

DC/DC converters for use inside the telephone handsetrequire operation from the high-source-impedance phoneline. Additionally, the CCITT specifications call for maxi-mum on-hook power consumption of 25 mA. The dc/dc

converter in Figure 1 is 70%-efficient at an input power of25 mA, providing 5V at 3.4 mA. Controlled, low-peak switchcurrent ensures that the 48V input line experiences noexcessive voltage drops during switching.

DC/DC converter operates from phone lineGARY SHOCKEY, LINEAR TECHNOLOGY CORP, MILPITAS, CA

A 48-to-+5V flyback converter provides 3.4 mA of output current.

FIGURE 2

L1 L3

L2

VA

T110:1:1

SW

GND

FB

SHDN

LBO

LBI

LT1316

0.022 F

R32MR2

1.30M1%

R469.8k1%

R6121k1%

R5432k1%

C10.1 F

Q1

R11.3M

7

1

2

3 4

8

VOUT5V

+

+

48V

6 5

2N3904

604k1%

Q2MPSA92

47 F

47 F

1N5817

1N4148

1N4148

NOTES:T1=DALE LPE-4841-A313, LPRI=2 mH.Q1=ZETEX ZVN4424A, BVDSS=240V, RDS(ON)=4.3V AT VGS=2.5V.R6, Q2, AND R5 MUST SIT NEXT TO THE FB PIN.

VIN

RSET

FIGURE 1

Switch voltage and current waveforms (a) show how the primary current ramps up during the switching cycle. The outputripple voltage is approximately 100 mV p-p (b).

SWITCH-PINVOLTAGE

10V/DIV

SECONDARYCURRENT

200 mA/DIV

SECONDARYCURRENT

200 mA/DIV

PRIMARYCURRENT50 mA/DIV

PRIMARYCURRENT50 mA/DIV

1 SEC/DIV 50 mSEC/DIV

VOUT200 mV/DIV

AC-COUPLED

(a) (b)

EDN DESIGN IDEAS

The circuit operates as a flyback regulator with an auxil-iary winding to provide power for the LT1316 switching-reg-ulator IC. When you first apply power, the LBI pin is low,causing the SHDN pin to connect to ground through LBO.Grounding the SHDN pin places the part in shutdown mode,and only the low-battery comparator remains active. Duringthis state, VIN rises at a rate determined by R1 and C1. The ICdraws only 6 mA in shutdown mode. R1 needs to supply onlythis shutdown current, the current through R2 and R3, andC1s charging current.

When LBI reaches 1.17V (which corresponds to a VIN ofapproximately 3.7V), the LBO pin lets go of SHDN and theIC enters the active mode; switching action begins, and theoutput voltage begins to increase. As the device switches,the VIN pin draws current out of C1. VIN then decreases suf-ficiently to trip the low-battery detector, stopping theswitching. Start-up proceeds in this irregular fashion until,eventually, the voltage at VA increases to 5V. (VA is the sameas VOUT because L2 and L3 have the same number of turns.)After start-up, current flows to the IC from VA rather thanfrom the 48V rail, increasing efficiency. The circuit will not

start if VOUT is loaded before it reaches 5V.During each switch cycle, current in the transformer pri-

mary ramps up until reaching the current limit (Figure 2a).The value of R4 sets the peak switch current. The circuit usesa 69.8-kV resistor to provide a peak switch current of 50 mA;increasing R4 decreases the current limit. Secondary peakcurrent is approximately equal to the primary peak currentmultiplied by the transformers turns ratio (Figure 2b). TheFB pin has a sense voltage of 1.23V, and you can set VOUT bythe following formula:

For the load currents of 4 to 80 mA, the circuit achieves aminimum of 70% efficiency. Less than 80 mA quiescent cur-rent flows when the converter supplies 0.5 mA over 36 to72V. (DI #2148) e

To Vote For This Design, Circle No. 356

The asynchronous RS-232C interface is a simple, low-costoption for interconnecting processor-based systems. Inmany applications, you need to transfer variable-size mes-sages. However, the character-oriented RS-232C protocoloffers no direct mechanism for transferring messages as self-contained packets. The method described here uses anobscure feature found in most UART devices to indicatepacket boundaries. The feature is the capability to transmitand recognize the Break character. This character is noth-ing but a space, or low, in the transmit line of a durationequal to or greater than an entire asynchronous character-transmission time, including the start and stop bits (Figure1). In this framing method, the message data bytes sand-wich between two Break characters to form a data frame(Figure 2).

A Turbo C program demonstrates the transfer of variable-size messages between two PCs with 8250-compatible UARTs(Listing 1). You can download the program from EDNs Website, www.ednmag.com. At the registered-user area, go intothe Software Center to download the files from DI-SIG,#2140.

A null-modem cable interconnects the PCs COM ports.The same routine works with most other UARTs. Themethod allows data-packet reception in interrupt mode andwastes no CPU overhead looking at each character to detectpacket boundaries. Instead, the UART does the detecting.Because the Break is not a legitimate data character, it is data-

Transfer data frames over asynchronous RS-232C linesSK SHENOY, NAVAL PHYSICAL AND OCEANOGRAPHIC LAB, KOCHI, INDIA

BREAK MARK

DATA (NULL)START

SPACE

STOP

FIGURE 1

Most UARTs can transmit and recognize the Break character,a state of logic 0 between the start and stop bits.

BREAK DATA 1DATA 1 DATA 2 DATA n BREAK

FIGURE 2

The Turbo C routine in Listing 1 sandwiches data bytesbetween two Break characters to form a data frame.

96 EDN JANUARY 15, 1998

V 1.23RR

0.6VOUT5

6

=

+ .

EDN DESIGN IDEAS

transparent, and you can use it for binary-data exchange.You can use this in-band scheme with repeaters andmodems, as long as they permit transmission of the Breakcondition. The packet-boundary detection is relativelyimmune to a missed Break character and to data errors. Youcan render the detection more robust by introducing data-length and check-sum fields in the frame to allow detectionof errors and flow control using an RTS/CTS (request-to-send/clear-to-send) handshake.

To transmit a Break, set bit 6 (Set Break) of the line-con-trol register to 1. The UART then sets its Tx line low, until bit6 encounters a 0. Transmission of a Null character (00 hex)makes the duration of the Break equal to one character-transmission delay. Bit 6 of the line-status register (TxMachine Status) indicates when this delay is over; then, theBreak bit resets. To enable detection of the Break, bit 2 of theinterrupt-enable register (interrupt-on-Rx-error condition)

sets during UART initialization. Bit 0, set to 1, enablesreceive-data interrupts. In the interrupt-service routine (ISR),bits 1 and 2 of the interrupt-identification register indicatethe interrupt type.

A global variable, Receive_Count, initialized to zero, han-dles frame reception. Upon detection of a Break, the UARTraises an interrupt. If Receive_Count is zero, the interrupt isa start-of-frame break and the UART ignores it. (You can usethe interrupt to set a Packet_Receive_On flag.) On each sub-sequent receive interrupt, the ISR stores the data in theReceive buffer with Receive_Count as the index. IfReceive_Count is nonzero when the Break interrupt is raised,the interrupt is an end-of-frame break. Then the routine callsthe frame-processing function and resets Receive_Count tozero. (DI #2140) e


LISTING 1DATA-FRAME-TRANSFER PROGRAM

EDN DESIGN IDEAS

Algorithm extracts cube rootJOHN T HANNON JR, PHILIPS CONSUMER ELECTRONICS CORP, KNOXVILLE, TN

The C routine in Listing 1 generates the cube root of eithera positive or a negative number. The number can rangefrom a small fraction to greater than 1 billion. Note thatthis idea is irrelevant for a PC, which includes a mathlibrary with the compiler and produces a more accurateresult with less effort. However, this idea is useful if you use

a processor for which you dont have a math library.The main routine inputs a number from the keyboard and

calls the cuberoot function. After calculating the cube root,the routine prints the result on the screen. The routine thenrecalculates the cube of this cube-root answer and prints thisnumber on the screen so you can compare the accuracy of

Using a piezoelectric element for alarm applications offerslow cost, low power, and flexibility. By coupling this elementwith a 12C508 programmable controller (Microchip Tech-nology, Chandler, AZ), you can implement an eight-pinalarm generator. This approach provides multiple driver for-mats with a minimum of additional cost and footprint.

The controller in Figure 1 drives the piezoelectric elementdirectly from pins 2 and 7 with complementary squarewaves. A siren, chirp, warble, or constant-alarm output isavailable by setting the corresponding mode on pins 5 and6 (Table 1). The design codes each mode as separate process-es, which you can consider as variations of frequency, fre-quency step, and dwell.

The design also codes the positive and negative true alarmenables, pins 3 and 4, into the device. The controller reteststhe mode and these alarm enables at periodic intervals in thecurrently selected modes cycle. This retesting permitsdynamic selection of the output formats using the modepins without a power reset. Applications can then use any or

all of the output formats to indicate application alarm or sta-tus conditions.

The 12C508s internal RC oscillator provides the timingcontrol used in each of the modes. Using an average of 3 mA,the controller operates from 2 to approximately 5.25V. Thefrequency-stepped formats are in constant timebasedincrements with constant frequency dwell times. Based on a2.2-kHz piezo-element resonant peak, each of the modescharacteristics uses code-settable, dedicated registers toestablish the output format.

The coded sequences use 127 bytes of code space. You canport the sequences into one of several code-compatibleMicrochip controllers or use a stand-alone peripheral con-troller, as in Figure 1, for any number of alarm applications.You can download applicable code from EDNs Web site,www.ednmag.com. At the registered-user area, go into theSoftware Center to download the file from DI-SIG, #2147.(DI #2147) e


VDD

PIEZOELECTRICELEMENT

VDD

A0

A1

GND

OUT OUT

ENB

ENB

12C5081 8

7

6

5

2

3

4 SEE TABLE 1

VDD

FIGURE 1

Controller provides multiple alarm-driver formatsWILLIAM GRILL, RIVERHEAD SYSTEMS, LITTLETON, CO

A programmable controller and a piezoelectric element com-bine to produce an alarm generator with multiple output for-mats: continuous frequency, two chirps, a warble, or a siren.

A1 A0 Alarm output

0 0 Continuous 2.2 kHz

0 1 Two single 2.2-kHz chirps: 0.2 sec each with 0.2 sec between

1 0 Warble: eight frequency steps swept continuously from below to above to below 2.2 kHz

1 1 Siren: repeating six frequency steps beginning at 2 kHz and stepping up to approximately 4.1 kHz

TABLE 1STRAPPED ALARM CONFIGURATIONS

102 EDN JANUARY 15, 1998

EDN DESIGN IDEAS

the result with the original number. Five deci-mal places are set up for the print command toallow an accurate comparison.

This algorithm is similar to the square-rootalgorithm that uses the divide-and-averagetechnique to reach a minimum error value.Before the cube-root operation begins, the rou-tine determines if the number is positive ornegative. If the value is negative, the programsets a flag so the returned root value can be setto a negative value. To start the process, theroutine sets up an error value and assigns aninitial value for the integer root. The error valuefor this function is 0.00001, and the initialvalue of root is 2.0. The routine squares thisvalue and divides it into the given number. Theroutine then adds the result to the originalvalue of root and divides this sum by 2 to gen-erate the new value of root. This process con-tinues until the absolute value of the differencebetween the cube of the value of root and thegiven number is less than the error valueinthis case, 0.00001.

For some values, this algorithm approachesbut never reaches the set error. Thus, the rou-tine increments a counter after each iteration.If the counter reaches the maximum set countbefore the routine finds the minimum error,the function ends and returns the value of root.If the original number was negative, the rou-tine changes the cube root to a negative value.

With the values in Listing 1, the accuracy fornumbers from 0.1 to greater than 1 billion isbetter than 0.001%. For numbers less than 0.2,the accuracy is slightly lower. However, thisaccuracy difference is a result of the error valuethat you use in the calculation. By setting theerror value (float variable error) to a smallervalue, such as 0.000001, the accuracy for verysmall numbers can also approach this value.

Two other factors affect the accuracy: thenumber of bits the processor uses for floating-point numbers, and the size of the originalnumber. For numbers with small absolute val-ues, the variable error controls the accuracy.The accuracy, which is

(calculated rootactual root)/actual root,

is approximately equal to

error variable/33original number.

So, with error set to 0.00001, the accuracy is about 0.003%for the cube root of 0.1, 0.03% for the cube root of 0.01, 0.3%for the cube root of 0.001, and so forth. In the limitthecube root of 0you cant divide by 0 to find percent accu-racy, but the actual root that the program calculates is

0.0156250.For numbers with large absolute values, the number of

iterations determines the accuracy. For instance, the algo-rithm calculates the cube root of 1012 as 10083.87109 after25 iterations and as10000.00000 after 45 iterations. (DI#2144) e


LISTING 1CUBE-ROOT EXTRACTOR

EDN DESIGN IDEAS

The circuit in Figure 1 uses a typical technique for varyingthe output voltage of a power supply via a programmablecontrol voltage. Although the topology and schematicdetails of the power supply are not critical, the protectiontechnique is novel.

The control IC is a UC3843AN PWM controller. This ICapplies 2.5V to the noninverting input of an internal erroramplifier but does not bring this input out to a pin (node B).The inverting input of the error amplifier is available at anexternal pin (node A). To regulate VOUT, the control IC mustmaintain the voltage at Node A equal to the 2.5V at Node B.The component values in the figure allow the dc outputvoltage of the power supply to vary between a minimum of5V and a maximum of 75V, as a function of VCONTROL, whichcan vary from 0 to 3V (corresponding to a VOUT of 5V and75V, respectively).

In the absence of Q1, VOUT and the voltage division of R3and R4 determine the voltage at Node A. The circuit com-pares this voltage with the 2.5V at Node B. The power sup-plys output-voltage control loop keeps the voltage at NodeA equal to Node B by appropriately controlling VOUT.

The circuit provides programmability of VOUT by sinkingcurrent from Node A. VOUT must source any current thatflows from this node. Also, the current must flow throughR3, which causes the voltage drop across R3 to increase. VOUT

is then always equal to the voltage drop across R3 plus a cur-rent set by VCONTROL. IC1s op amp forces the voltage across R2to equal the voltage at Pin 3 of IC1.

The addition of just one component, IC2, adds preciseovervoltage protection to the variable-output power supply.IC2 is a low-voltage shunt regulator that incorporates aninternal 1.24V precision reference. This low reference volt-age allows you to use this protection circuit with conven-tional power-supply control ICs for which 2.5V is a commoninternal reference voltage. Under normal operating condi-tions (for output voltages between 5 and 75V), IC2 doesnothing. The voltage at IC2s reference (Pin 1) is less than itsinternal 1.24V reference, so its cathode (Pin 3) draws no cur-rent. In this case, IC1 solely controls the voltage at the baseof Q1. For example, if VCONTROL is 3V, then the voltage acrossR2 is 1.13V and VOUT equals 75V. Note that, to simplify thisexample, the beta of Q1 is assumed to be infinite.

However, in the event of any kind of fault that mightcause the voltage across R2 to rise above 1.24V (which corre-sponds to a maximum VOUT of 81.7V), the shunt regulatorbegins to function. As the voltage at Pin 1 of IC2 begins toexceed the internal 1.24 reference voltage, the cathode of IC2begins to conduct. The cathode of IC2 then pulls down onthe base of Q1 to maintain 1.24V at Pin 1 of IC2. As this hap-pens, IC2 through Q1 controls the voltage across R2. This con-

+

1.00k

1k

1.65k

VCONTROL0 TO 3V

VCC5V

IC1

2

3

1

3

24

8

1+

+

R1

LM358

10

Q1

0.1 F 6.8 FTANTALUM

IC2TLV431A

2N3904

45.3kR4

45.3kR3

732R2

VOUT

ERROR AMPLIFIER

NODE A NODE B2.5V

5 TO 75V DC

UC3843AN

FIGURE 1

Shunt regulator provides overvoltage protectionROBERT N BUONO, MAHWAH, NJ

Adding one shunt regulator, IC2, to an otherwise typical programmable power supply provides precise overvoltage protection.

EDN DESIGN IDEAS

trol causes the output of IC1 to saturate at a positive voltageof approximately 3.7V because IC1 can no longer keep thevoltage across R2 equal to the voltage at its input (Pin 3). Thebenefit to circuit operation is that IC2 now operates with aconstant-cathode current determined by the voltage acrossR1, which equals 3.71.8V/1kV=1.9 mA. This level of cath-ode current ensures that IC2 regulates properly.

This protection circuit is immune to any potential failure

mode of IC1s op amp or the programming voltage source,VCONTROL. IC1 operates only from 5V. If its output (Pin 1)shorts to ground, the minimum VOUT results. If its outputshorts to VCC, IC2 sinks 51.8V/1 kV=3.2 mA, and VOUTclamps at the maximum of 81.7V. (DI #2146) e


A flashing LED is an excellent visual alarm. Unfortunately,the LED is a dc device and requires additional circuitry tooperate from an ac source. Several circuits can perform thenecessary function, but the circuit in Figure 1a is the mostefficient. This circuit is also reliable, compact, and inex-pensive.

The F336HD red-flashing LED (part no. 276-036 at RadioShack) operates directly from 5V and produces a consistentpulse of light at approximately 1 Hz without a time-constantcapacitor. This LED starts immediately when you applypower and is insensitive to temperature variations. TheW04G full-wave bridge rectifier produces a full-wave dcwaveform from the 120V-ac line. The 0.5-mF capacitor pro-vides current limiting for operating the LED from the recti-fied 120V-ac line. The 100V resistor protects the circuit from

surges when you first apply power. The 1N4733 5.1V zenerdiode protects the LED from high-voltage excursions.

Some applications require a more intense alarm. A simpletriac pulser can pulse a 120V-ac lamp or other resistive loadof as much as 8A (Figure 1b). This circuit is also reliable,compact, efficient, and inexpensive. The circuit is similar tothe one in Figure 1a, but, in this case, the F336HD LED dri-ves an MOC3010 opto-coupled triac driver. The 180V resis-tor provides current limiting for the 2N6343 triac gate. Thisconfiguration can pulse a load as high as 960W. You canincrease the power rating by choosing a different triac. (DI#2143) e


LED flasher and triac pulser work off ac lineDENNIS EICHENBERG, PARMA HEIGHTS, OH

A full-wave bridge rectifier provides a dc signal for the red-flashing LED (a). Adding a triac allows the circuit to pulse a 120V-ac lamp or other resistive load of as much as 8A (b).

1N47335.1V

F336HD

W04G

0.5 mF200V

1001/4W

120V AC60 Hz

1N47335.1V

F336HDW04G

0.5 mF200V

1001/4W

120V AC60 Hz

(a) (b)

LOAD2N6343

1802W

MOC30101 4

2 3

FIGURE 1

Entry blank must accompany all entries. $100 Cash Awardfor all published Design Ideas. An additional $100 CashAward for the winning design of each issue, determinedby vote of readers. Additional $1500 Cash Award forannual Grand Prize Design, selected among biweekly win-ners by vote of editors.

To: Design Ideas Editor, EDN Magazine275 Washington St, Newton, MA 02158

I hereby submit my Design Ideas entry.

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Title

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E-mail

My e-mail address may be published Yes No

Company

Address

Country ZIP

Design Idea Title

Social Security Number(US authors only)

Entry blank must accompany all entries. (A sepa-rate entry blank for each author must accompany everyentry.) Design entered must be submitted exclusively toEDN, must not be patented, and must have no patentpending. Design must be original with author(s), mustnot have been previously published (limited-distributionhouse organs excepted), and must have been construct-ed and tested. Fully annotate all circuit diagrams. Pleasesubmit software listings and all other computer-readabledocumentation on a IBM PC disk in plain ASCII.

Exclusive publishing rights remain with Cahners Pub-lishing Co unless entry is returned to author, or editorgives written permission for publication elsewhere.In submitting my entry, I agree to abide by the rules of

the Design Ideas Program.

Signed

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Design Idea Entry Blank

Your vote determines this issues winner. Vote now,by circling the appropriate number on the readerinquiry card.

The winning Design Idea for the August 15, 1997, issue isentitled Gates provide low-cost sine-wave generator, sub-mitted by Adolfo Mondragon of Philips Components (Juarez,MX).

EDN DESIGN IDEAS

EDN DESIGN IDEAS

The circuit in Figures 1 and 2 generates frequency-locked tri-angle waves of constant amplitude. It uses readily availableTTL and other older-technology parts. The circuit portion in

Figure 1 comprises the frequency dividers, counters, andconverter. The portion in Figure 2 contains current sources,output circuits, and comparators. The circuit satisfies a need

Scheme yields frequency-locked triangle wavesDANIEL DUFRESNE, DECATRON, ST BRUNO, PQ, CANADA

R0(1)R0(2) QAR9(1)R9(2)

CKA QDQCQB

CKB

2367

12

98

111

14

IC9DM74LS90

R0(1)R0(2) QAR9(1)R9(2)

CKA QDQCQB

CKB

2367

12

98

111

14

IC8DM74LS90

S1F/100F/10

SELECT DIVIDER RATIOINPUT CLOCK, TTLJ2

BNC

RISE/FALL

QDFALL=POSITIVE PEAK

LOWCLK

D

Q

IC11ADM74LS74A

R261k

J3BNC

R14220

R241k

R2815k

D3LED

D2LED

R16220

R15220

R297.5k

C710nF

C50.22 F

R307.5k

C60.22 F

C91 F

VCC

VCC

R251k

IC1D

IC1C

IC1B IC10A

VCC

VCC

VCC VCC

R271k

VCC

PRE

CLR

Q

QQ

4

3 65

5 6

21

9 8 TTLOUTPUT

DM74LS05

DM74LS05

DM74LS05

DM74LS10

DM74LS10

1212

13

IC10B3

645

3 4

HIGH

S2SW-PB

TEST

TEST

CLRUPDOWN

ABCD

QAQBQCQD

1454

11151

32

1213

67

109

LOAD

CO

IC6DM74LS193

BO

CLRUPDOWN

ABCD

QAQBQCQD

1454

11151

32

91011

512

7

1213

6710

9

LOAD

CO

IC7DM74LS193

IC13BDM74LS123

IC12AD-DAC-08

BO

ABCLRCEXTREXT/CEXT

6

QQ

R3115k

C81 F

VCC

VCC

123 4

13

15

IC13ADM74LS123

ABCLRCEXTREXT/CEXT

14

MSB-B1

LSB-B8THRCNT VS

VS

VRFVRF+

IOUTIOUT

COMPEN

B2B3B4B5B6B7

13

121110987

2

14

15

16

465

RAISE INPUTFREQUENCY

LOWERINPUT

FREQUENCY

IO

12V

12V

TESTNOT

13

12V

FIGURE 1

This divide-by-10 or -100 triangle-wave generator usesdigital AGC techniques to maintain a constant output-signal amplitude over a wide frequency range.

EDITED BY BILL TRAVIS & ANNE WATSON SWAGER

EDN DESIGN IDEAS

for a triangle wave of approximately constant amplitude, ata frequency exactly one-tenth or 1/100 that of an input TTLclock. The input frequency can vary over a wide range beforethe circuit loses lock. The triangle-wave output frequencyranges from 250 Hz to 2.5 kHz. Two decade dividers dividethe input clock by 10 or 100. Switch S1 selects the dividerratio. The signal RISE/FALL is a 50%-duty-cycle wave thatturns on a 2I current source, comprising transistors Q3, Q4,and Q5; a I current source comprising Q1 and Q2 is alwayson.

After you initially adjust R21, op amp IC3 keeps any dc off-set (caused by tracking imbalances between the currentsource and sink) to a minimal value. The output signal fromthe 8-bit DAC, IC12, controls the current level in both thesource and sink. The currents sum on capacitor C2, thus gen-

erating a triangle wave. An op amp buffers the triangular sig-nal; potentiometer R22 adjusts the output level. Assuming afixed input frequency and a fixed capacitor value, you canadjust the current sources for the desired amplitude.

If the frequency decreases, the triangle-wave amplitudeincreases. To keep the amplitude constant, comparator IC4detects that the positive-peak amplitude is too high. Thecomparator sends input-clock signals to decrement the 8-bitcounter IC6 and IC7, thus controlling the source- and sink-current value through the DAC. Similarly, if you raise theclock frequency, the triangle-wave amplitude decreases.Comparator IC5 detects that the positive-peak amplitude atthe end of the triangle waves rise is too low. IC11a latches thecomparator output and gates clock pulses to increase thecount and the source- and sink-current values.

+

+

+

Q32N3906

R11001%

R21001%

R31001%

Q42N3906

Q52N3906

Q62N3906

Q12N3904

Q22N3904

D11N4001

C10.1 F

C20.1 F

C30.1 F

C40.33 F

R23220k

J1BNCR13

220R2210k

R194.7k

R510k

R410k

R6200

R21100

R7150

R81M

R91M

R101M

R20100k

12V

12V

IO

RISE/FALL

IC1A

IC2

IC4

IC3

DM74LS05

1 2

VCC

AUTOZERO CIRCUIT

3 7

2

1 54

6

12V

12V

12V

TL081

1

1

54

4

2

3

8 6 5

7

7

12V

12V

12V

TL081

TRIANGULAR-WAVE OUTPUT63

2

OUTPUT LEVEL

HIGH

VCCVCC

PEAK TOO HIGHLM311

+

R184.7k

R113.9k

R12220

R17910

IC5

14

2

3

8 6 5

12V

12V

LOW

VCC

PEAK TOO LOWLM311

7

FIGURE 2

A companion to Figure 1s converter, this block contains the supporting current sources, output circuits, and comparators.

EDN DESIGN IDEAS

If you run out of counts on IC6 and IC7, the carry and bor-row output signals trigger the monostables, IC13A and IC13B.LED D2 or D3 lights to warn you to change the input fre-quency accordingly. Frequency tracking is asymmetric: Assoon as the circuit detects the high limit, pulses decrementthe counter. The sooner the high limit occurs, the moredecrementing pulses the counter receives. However, youdetect that the current is too low only when the RISE/FALLsignal falls, and the triangular wave is still below the posi-tive-peak low limit. This occurrence triggers a single pulse.

To adjust the circuit, set the divider to f/10, apply a 10-kHzTTL signal to the clock input, short-circuit C2, push the TESTbutton, and adjust R22 for a zero-centered triangular wave.Release the TEST button, and remove the short circuit. Youcan increase the frequency range by using a bigger counterand a higher resolution DAC or by band-switching the cur-rent-summing capacitor, C1, with some added logic that theborrow and carry outputs of IC7 trigger. (DI #2127) e


You can use a standard monolithic-microwave IC (MMIC) toconfigure an efficient and economical microwave mixer.Some systems require a mixer with an input level lower than10 dBm. Many available mixers, however, require greaterthan 10-dBm input power. The circuit in Figure 1 exploitsthe inherent nonlinearity of a Mini-Circuits (Brooklyn, NY)MAR6 microwave amplifier to configure a low-level mixer.The idea is to add the input signals and feed the sum to theMMIC (Figure 1a). The amplifiers saturation characteristicproduces the harmonics and intermodulation products. TheMMIC has greater than 10-dB gain at frequencies over 1GHz, a desirable characteristic for making mixers for the 0.9,1.8-, and 2.5-GHz bands.

The MMIC also has a maximum power output of 2 dBm

at 1-dB compression, a useful trait for obtaining intermodu-lation products with low input power. The gain of the MMICvaries from 17 dB at 100 MHz to 10 dB at 2.4 GHz. The gaincan thus generate intermodulation products using two inputsignals whose power is lower than 10 dBm. Finally, theMMICs 3-dB noise figure is an important factor for low-levelinput signals. The adder uses two standard-value 22VV resis-tors and thus presents a reasonably good impedance matchin 50VV systems (Figure 1b). For perfect impedance match-ing, you would need 20.7VV (unavailable) resistors. Withthe 22VV resistors, the input VSWR is less than 1.4 at 1 GHz.To obtain optimum results, you should use microstrip tech-niques, with the dimensions in Figure 1b, in designing thepc board.

(a)

(b)

MMICAMPLIFIER

OUTPUT

INPUT

LOCALOSCILLATOR

MMICTLINE

TLINE

TLINE

TLINE TLINE5 pF5 pFOUTPUT

470

12V

22

22

INPUT 1

INPUT 2TLINE: TRACK WIDTH=3 mm, TRACK LENGTH=5 mm, DIELECTRIC WIDTH=1.5 mm, er=4.8 (VITRIUM FIBER).

VCC 1 nF

FIGURE 1

A summing network and a standard MMIC (a), connected with microstrip techniques (b), produce an efficient mixer for low-level signals.

Off-the-shelf MMIC suits mixer applicationsJ LEIRA PAZ, M PEREIRA VARELA, AND FP FONTAN, UNIVERSITY OF VIGO, SPAIN

You can use this mixer in a variety of applications: down-converters and modulators, for example. Another exampleis an amplitude-shift-keying (ASK) modulator for digitalapplications (Figure 2). The mixer block in Figure 2 uses thecircuit in Figure 1a. The measurements of Figures 3, 4, and5 reflect a 1-GHz carrier frequency and a 4-Mbps digital sig-nal. To obtain a good relationship between the carrier leveland the modulated-signal level, use a 5-dBm input-carrierlevel, a 0.5-dBm digital signal, and a 12V supply. The out-put-signal level is 0 dBm.

Figure 3 shows the magnitude of the intermodulationproducts as a function of the 100-MHz signal power. Theinput frequencies are 1.3 GHz and 100 MHz. The mostimportant intermodulation frequencies are the sum-and-dif-

ference intermodulation products, 1.2 and 1.4 GHz. Figure4 shows the input-input and output-input isolation charac-teristics. Figure 5 gives the variation of the input and out-put VSWR as a function of the input frequency. (DI #2136)

eTo Vote For This Design, Circle No. 328

EDN DESIGN IDEAS

50

MODULATEDOUTPUTSIGNAL

1-GHzGENERATOR MIXER

TTLINPUT

100 nF

220 1 H 100 nF

FIGURE 2

The circuit in Figure 1b is the mixer block in this 1-GHz ASKmodulator.

SIGNAL POWER (dBm)(1.3-GHz INPUT=3 dBm)

OUTPUTPOWER(dBm)

5

10

15

20

25

30

3530 25 20 15 10 5 0

1.4-GHz INTERMODULATION

1.2-GHz INTERMODULATION

FIGURE 3

The output levels of the sum-and-difference intermodulationproducts in Figure 2s circuit vary linearly with the 100-MHzsignal power.

INPUT FREQUENCY (MHz)

ISOLATION(dB)

5

10

15

20

25

300 500 1000 1500 2000 2500 3000

INPUT-INPUT ISOLATION

OUTPUT-INPUT ISOLATION

FIGURE 4

Input-input isolation for Figure 2s circuit improves withincreasing input frequency; output-input isolation degradesbut remains reasonably high to 3 GHz.

FREQUENCY (MHz)

SWR1.5

1.4

1.3

1.2

1.9

1.8

1.7

1.6

1.1

10 500 1000 1500 2000 2500 3000

INPUT VSWR

OUTPUT VSWR

FIGURE 5

The slight input-impedance mismatch and varying input reac-tance of the MMIC produces input VSWR degradation withfrequency, but the VSWR remains within a respectable 1.4 atfrequencies to 1 GHz.

EDN DESIGN IDEAS

The circuit in Figure 1 translates the level of humidity from0 to 100% into a stable, respective dc signal of 0 to 100 mV.The heart of the circuit is IC1, the IH3602-C relative-humid-ity sensor (Microswitch/HyCal Sensing Products, Freeport,IL). This device operates on 5V at 200 mmA and provides a dcoutput of 0.8 to 4.0V over the 0 to 100% humidity range.The output impedance is 5 mmA when sourcing, and on-chipcircuitry preconditions the humidity-related charge of athermoset polymer dielectric capacitor. The dc output con-tains a small amount of 1-kHz modulation, which is an arti-fact of typical switched-capacitor circuits. Device accuracy is2% relative humidity, and linearity is 0.5%. The six-pinTO-5 package includes a precision thin-film, 1-kVVRTD thatyou can use in applications that require temperature-cor-rected relative-humidity data.

The LT1236-5 provides a stable 5V supply for IC1, whichprecludes any ratiometric changes in the sensors output thatwould otherwise occur with less stable 5V supplies. Amplifi-er IC2As voltage follower buffers the sensors high-imped-ance output. IC2B, a 1-kHz, two-pole Butterworth filter,reduces the 1-kHz chopper modulation. The unique outputstage comprising IC3 is a precise, dc-accurate, ultralinear,noninverting summing/scaling amplifier. The LT1112 per-forms well for this function because it has high large-signalgain (AVOL), low input bias current (IB), and low input offsetvoltage (VOS). The summing node of IC3A is a handy spot toadd a temperature-correcting term, as the figure indicates.C1 and C2 roll off any high-frequency gain/phase-relatedoscillations.

The 0% relative-humidity adjustment not only takes care

+

+

+

_

+

IC2A

_

+

IC2B

_

+

IC3A

IC3B

_

+

NOTES:*POLYPROPYLENE 2% CAPACITORS;IC1=IH3602-C (HYCAL);IC2=LT1078-ACN8;IC3=LT1112-ACN8;ALL RESISTORS (EXCEPT TRIM POTS) ARE 0.1%, 25 PPM.

RETURN

OR9V

BATTERY(MN-1604)

ON

LT1121-58 5

5

1

1 5

8 1

4

67

8 5

2

36

3

3

2

2

4

76

LT1236-52

2 41 8

30.1F

0.1F

0.1F

2.2F

LTC1044

9V

3 6

10 FTANTALUM

10 FTANTALUM

5V

5V

RTDEXCITATION

IC1

6

4

CASE

+

+

}} RTDOUTPUT

5V

5.00V REF

113k113k

5V

0.002*F

0.1F

0.1F

5V

0.001F*

0.047F

E1

E2

0 TO 100 mV OUTPUT(0 TO 100% RH)

E0

R1402k

R2402k

R624.9k

R340.2k

R450k

18.7k

R549.9k

C1470 pF

C20.001 F

0.1F

OPTIONALRTD AMP

50k(19T)

402k

49.9k

0% RHADJUST

100% RHADJUST

(0.8V)

34k

5V

5VSIMPLIFIED DC TRANSFER FUNCTION:

E0=

R3 R3E13 E23+ + ...

R4+R5R6

ELECTROLYTIC

7

R1 R2

FIGURE 1

Signal conditioning precisely indicates humidityWILLIAM WHITEHEAD, LAFAYETTE, CO

Precise signal conditioning transforms the 0.8 to 4.0V output of an accurate 0 to 100% relative-humidity sensor, IC1, to a 0-to 100-mV output.

EDN DESIGN IDEAS

of the nonzero output of IC1, but also compensates for anyresidual offsets. You achieve a full-scale output of 100 mVusing the 100% adjustment.

The circuit draws 2.56 mA, which, if battery-powered,results in a battery life of about 250 hours. You can drop thetotal consumption to approximately 625 mmA by changingIC2 and IC3 to LT1078s and by powering IC1 from the 5V out-

put of the LT1121-5. This change lengthens battery life tomore than 1000 hours. However, these changes also reducethe overall accuracy of the circuit and prevent IC3 from dri-ving anything but very light capacitive loads, such as high-impedance ADC inputs. (DI #2145) e


Vital-signs monitor consumes less than 50 mmALEONARD SCHUPAK, DISCOVISION ASSOCIATES, IRVINE, CA

A remote data-acquisition circuit for monitoring a patientsvital signspulse rate, respiration, and temperatureusesvery little power as well as inexpensive sensors and circuits(Figure 1). The data-acquisition portion uses the low-costCD4000 series of CMOS ICs and consumes less than 50 mmAfrom a 3V battery. The circuit uses 5033oversampled sigma-delta ADCs with a PWM/FM system, which combines threedata channels on one RF carrier.

In Figure 1, the pulse sensor comprises a pair of conduc-tive plastic electrodes that monitor two EKG lead pointsacross the patients chest. These electrodes are similar tothose used on a popular and effective pulse monitor for ath-letic activities. The respiration sensor is an Amp (Harrisburg,PA) DT1-028K, which consists of a piezoelectric-film elementmounted on a flexible beam that attaches with a chest strapsimilar to the same athletic monitor. The strap uses the beamas one of its suspension loops, the electronics assemblyattaches to the other end, and the complete assembly strapsto the patients chest. The temperature sensor comprises a50-kVV thermistor and linearizing resistor mounted in theEKG electrode, which makes a good thermal connection tothe patients body.

Using the unique properties of the CD4069 as an analogcomponent, the circuit implements two second-ordersigma-delta ADCs that sample the ac components of thepulse (EKG) and respiration at a nominal 2-kHz clock rate.The circuit develops this clock using the thermistor as a tun-ing element in a temperature-to-frequency converter. Tem-perature is a very low-frequency (essentially dc) data-chan-nel component, and pulse and respiration are higherfrequency ac. Thus, you can easily combine all three chan-nels in one serial data channel for transmission over the RFlink.

The analog circuit also includes an open-lead detectorthat rings an alarm if the EKG lead loses contact. IC1C andIC1F form a Schmitt trigger that disables the RF-carrier out-put when the sense of skin conductivity is lost.

IC2A and IC2D form a straightforward clock oscillator.Although easy to design, this oscillator imposes some inter-

esting calibration problems in operation. The thermistor,R1, and tuning capacitor, C1, determine the frequency. For athermistor of 11 kVV at 98.688F, C1 should be 0.022 mmF fora clock frequency of 2 kHz. Connecting these componentsto IC2A and IC2D, as the figure shows, provides a convenientpc-board layout with good isolation from these low-levelinput signals. You can use an additional resistor set to opti-mize the frequency range, depending on the thermistorselection. The operator usually performs a calibration cyclewhen you apply the unit to the patient, setting the currentreading to a known temperature obtained directly from thepatient.

The operation of the ADC is straightforward but has someunusual aspects. (Note that because of the way the CD4069inverter worksused here exclusively for analog-amplifierfunctionsthe figure uses a one-input NAND gate as thelogic symbol to differentiate from the triangle symbol.) AnADC channel comprises three CD4069 inverters in series, forwhich two operate as analog integrating amplifiers biased inthe linear region. In this configuration, each CD4069 sectionyields about 30 dB of gain and a bandwidth in excess of 2kHz. The third inverter and flip-flop input act as the typicalcomparator part of the ADC.

The first stage is a relatively uncomplicated integratorwith an indeterminate time constant of approximately 1 to10 mmsec. The second stage has a pole/zero response that flat-tens to 20 dB at approximately 5 kHz. Feedback from thesampling register (flip-flop) provides a stable, wideband

Channel A Channel B Phase increment ()

0 0 45

0 1 90

1 0 135

1 1 180

TABLE 1PHASE INCREMENTS

EDN DESIGN IDEAS

inner loop as well as the main outer loop. The 100-MVVresistors in the feedback loops are readily available from sev-eral vendors in surface-mount configuration and are reliablewhen you use good assembly practices.

The components in the figure comprise only the front-end input portion of the design; the noise filter and subse-quent decoder/application circuits reside at the receiver.Before transmission, the circuit combines the three chan-nels of data into one modulating signal using a PCM formatsimilar to modified FM (MFM) for which the temperature-controlled clock oscillator determines the pulse-rate clock.In other words, the transmitter uses a complex set of mod-ulating codes that include a PCM/FM component superim-posed on an amplitude-shift-keyed (ASK) carrier. The tem-perature-sensitive oscillator frequency varies about 20%

total over the expected range of body temperatures, and thisvariable rate is adequate to transmit the digital PCM data.

A CD4008 full adder encodes the digital data from eachADC flip-flop in MFM form. A simple 3-bit digital synthe-sizer accomplishes the encoding; the contents of output reg-isters IC3C and IC3D determine the output phase. The ADCsdata contents determine the incremental phase change ateach clock (Table 1). The circuit then uses the most signifi-cant bit of the output register as the ASK signal. The 4-bit reg-ister then stores the sum of the data, or the phase incrementwith the current contents, representing the digital phase ofthe modulation carrier. The maximum resulting fundamen-tal frequency of this carrier is then one-half the clock fre-quency. (DI #2149) e

Inexpensive sensors and simple CD4069-based sigma-delta ADCs comprise the front end of low-power, remote data-acquisi-tion for monitoring a patients temperature, pulse, and respiration.

IC1C4069

IC1F4069

VCC

R1C1

IC2A4069

IC2D4069

IC1B4069

IC1A4069

IC2B4069 IC3A

40175

D0 Q0

IC2C4069

5 6 9

1 2 3 4 43 3 2

6 5

8 1 2 13 1222M

100M

100M

10M

100M

1M

100k

1M

CLK RSTIC3G

40175

9 1 OPEN LEAD

0.1 F

EKG-HI

EKG-LO22 pF

10 pF

IC1E4069

IC1D4069

IC2E4069 IC3B

40175 IC4CD4008

IC3F40175

D1 Q1

VCC

D5 D6

IC2F4069

13 12 11 10 1011 4 5

8 9

100M

10M

100M

1M

100k

22 pF

10 pF

DT1-028K

IC3E40175

D4 Q4

IC3D40175

D3 Q3

IC3C40175

D2 Q2

A1A2A3A4

S1S2S3S4

B1B2B3B4

CI CO

61357

6 7

4

149

215

10

14 15

12

10

11

11

1213

13

MODU-LATORDRIVE

FIGURE 1

EDN DESIGN IDEAS

NC VCC

VB

VOUT

GND

ANODE

CATHODE

NC

HCPL-2601

1 8

7

60.1 F

10k

5

2

3

4

D1

D2

D3

D4

MOTOR ORSERVO OUTPUT

RIN16.0k, 3W

RIN26.0k, 3W

IC2

5V

R3C2

RTC VCC

B

A

CTC

RS

NC NC

MODE

Q/Q SEL

Q

AR

MR

GND

R1

R2

C1

56k

120k

330 pF

IC3

1

2

3

4

5

6

7

MC14541B

IC1

IC1

MOTOR RUNNING

14

13

12

11

10

9

8

5V

FIGURE 1

Most applications require redundantsystem checks to ensure that devices areoperating as expected. The circuit inFigure 1 detects when a PWM-con-trolled servo motor is running. You canmonitor the motor-running signal out-put with a CPU or tie the output tohardware that indicates a fault if themotor is running when it should be off.The motors output connects to inputresistors RIN1 and RIN2. The use of tworesistors protects the motor or servo amplifier in the case ofa short circuit. RIN1 and RIN2 also serve as current-limitingresistors for the LED in the opto gate, IC2.

The value of RIN1 and RIN2 in Figure 1 is suitable for 150Vnominal servo output voltage. Because the input voltage canreverse, the circuit uses a full-wave bridge (D1 to D4) beforethe input of the opto-gate IC. The circuit needs a high-speedopto gate, because when the motor runs at low speeds, theservo-output duty cycle can be only a fractional percentage,thereby providing only 1-mmsec or narrower pulses to sam-

ple. When no signal is present at theinput resistors, the output of the optogate is high, causing the output ofinverter IC3 to be low. The low outputallows the MC14541 counter, IC1, tocount at the frequency determined byR1, R2, and C1.

You can determine the time-out bymultiplying the count range (selectedby inputs A and B) by the period of thefrequency set in IC1. Table 1 shows

approximate time-outs. Upon the initial application ofpower, the motor-running signal remains active until thetime-out occurs. Upon detection of a servo pulse of 500 nsecor longer, the master reset pin (Pin 6 of IC1) goes high, resetsthe internal counter, and asserts the motor-running signal.The motor-running signal remains low for the amount oftime shown in Table 1. The time-out for the circuit in Fig-ure 1 is approximately 10 msec. (DI #2155)

e

Optocoupled gate detects motor operationJIM KNIPFER, LIEBEL-FLARSHEIM CO, CINCINNATI, OH

A B Approximatetime-out period

0 0 350 msec

0 1 45 msec

1 0 10 msec

1 1 2.8 sec

TABLE 1APPROXIMATETIME-OUT PERIODS

Did you leave your motor running? This circuit lets you or your C know.

In mP/mC systems, you sometimes need to use many outputports and update all the ports simultaneously. For instance,in systems that use multiplexing techniques, the outputports require refreshing for every scanning period. Oneexample is a system of multiple dot-matrix LEDs. Supposethat an N-column, 838 LED matrix uses a row-scanningtechnique. Every eight-dot column of the nth LED connectsto the nth port (n=1N) and the mth row (m=07), in whichrow a switching transistor controls all the LEDs. To updateeach row, the rows switching transistor turns off, and all Nports receive an update from the display buffer. The switch-ing transistor for that row then turns on. The method in List-ings 1 and 2 and Figure 1 allows you to simultaneouslyupdate all N output ports.

Two approaches are available for implementing the par-

allel-output port. In the first approach, every output port hasits own address. The address-enable lines of the output portsconnect to the chip decoder. To update the output ports, theapplication program needs to directly refer to the portsaddress (Figure 1a). The native MCS-51 assembly routine inListing 1 simultaneously updates all N output ports in theconfiguration of Figure 1. Assume the addresses of theseports are OUTPUT_PORT0, OUTPUT_PORT1, OUTPUT_PORT1+1OUTPUT_PORT(N1).

Alternatively, you can connect all the output ports in theconfiguration of Figure 1b. In this method, only one addressrefers to all the output ports. For example, to update all Nports, the application program must refer to the portsaddress and then iterate the following steps N times: Readdata from address N from the buffer, route the data to the

Scheme implements multiple output portsW KURDTHONGMEE, NAKORN SI THAMMARAT, THAILAND


EDN DESIGN IDEAS

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

D1

D2

D3

D4

D5

D6

D7

D8CLKOC

19 18 17 16 15 14 13 12

OUTPUT PORT 1

IC1

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

D1

D2

D3

D4

D5

D6

D7

D8CLKOC

19 18 17 16 15 14 13 12

OUTPUT PORT 2

IC2

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

D1

D2

D3

D4

D5

D6

D7

D8CLKOC

19 18 17 16 15 14 13 12

OUTPUT PORT 3

IC3

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

D1

D2

D3

D4

D5

D6

D7

D8CLKOC

19 18 17 16 15 14 13 12

OUTPUT PORT 4

IC4

DATA BUSDB0..7CS0CS1CS2CS3NOTES: DECODED ADDRESS=CHIP SELECTION.

IC1 TO IC4=SN74HC574N.

IC1 TO IC4=SN74HC574N.

1 11 2 3 4 5 6 7 8 9 11 2 3 4 5 6 7 8 9 11 2 3 4 5 6 7 8 9 11 2 3 4 5 6 7 8 9

(a)

(b)

DB0DATA BUS

NOTES: DECODED ADDRESS=CHIP SELECTION.

CS

DB1DB2DB3DB4DB5DB6DB7

OCC

D1D2D3D4D5D6D7D8

Q1Q2Q3Q4Q5Q6Q7Q8

IC1

23456789

1918171615141312

11

1OC

C

D1D2D3D4D5D6D7D8

Q1Q2Q3Q4Q5Q6Q7Q8

IC2

23456789

1918171615141312

11

1OC

C

D1D2D3D4D5D6D7D8

Q1Q2Q3Q4Q5Q6Q7Q8

IC3

23456789

11

1

11

OUTPUT PORT 1

OUTPUT PORT 2

1918171615141312

OCC

D1D2D3D4D5D6D7D8

Q1Q2Q3Q4Q5Q6Q7Q8

IC4

23456789

1918171615141312

1

OUTPUT PORT 3

OUTPUT PORT 4

FIGURE 1

One way to update output ports is to address every port (a); another method is to address them all simultaneously (b).

EDN DESIGN IDEAS

referred port, and let N=N1.Note that, in the above example, data from location n in

the buffer updates the nth port, where n is between 0 andN1. Listing 2 is the MCS-51 native routine to simultane-ously update the output ports. Assume that the singleaddress of the N ports is OUTPUT_PORT. By using this sin-

gle-address configuration, you do not need to refer to out-put ports addresses every time you need to update them.You thus eliminate one instruction in the update loop, mak-ing the routine shorter and faster. This routine is suitable forimplementation in an interrupt-service routine. (DI #2151)

e


LISTING 1MCS-51 ROUTINETO UPDATE OUTPUT PORTS LISTING 2MCS-51 ROUTINE

FOR SIMULTANEOUS UPDATE

It is sometimes desirable to display theoutput of a PIC mC graphically, ratherthan numerically. However, the opera-tion increases system complexity andexpense. In addition to the LCD itself,you usually need a graphics controllerand at least 1 kbyte of RAM. However,you can obtain a satisfactory plot (Fig-ure 1) without the use of a controller orany RAM. At first glance, the parame-ters seem daunting. The least expensivegraphics LCDs (for example, theOptrex DMF696, at $39.51 fromDigikey (Thief River Falls, MN)) have aresolution of 128364 (width3height)pixels, which equates to 1024 bytes. Amidrange PIC mC, such as the PIC16C37A, has only 192 bytes of RAMavailable, including whatever you need for program vari-ables.

Furthermore, you must frequently refresh the LCD:Optrex recommends a 70-Hz rate. The PICs cycle time (thetime it takes the mC to execute one command) is 200 nsec.The mC divides a 20-MHz oscillator input by 4 to produce

the 5-MHz cycle frequency. Because theLCD needs 8192 pixels at an approxi-mate 70-MHz refresh rate, the PIC hasthe time to issue only approximatelynine commands for each pixel. More-over, this time must include the timingpulses (Figure 2) as well as the data.

The key to matching the PICs capa-bilities to the task is recognizing that agraph is a specialized display. The plotis of a single-valued function of y vs x,so the display has 128 points at anytime. The majority of the pixels carryno information whatsoever. Inasmuchas the maximum resolution possible onthe vertical axis is only one part in 64,1 byte (1-in-256 resolution) is morethan adequate to contain one datum,

and the 192 bytes of PIC RAM is more than enough for theplot. (To allow for borders, the graph in Figure 1 actually hasa plottable area of only 120353 pixels.)

Another problem is to write code that is terse enough tomaintain the required refresh rate. The fastest way to move abit (pixel) out of the PIC is to rotate it through the carry flag

FIGURE 1

PIC plots pixels sans controllerDARYL CHRISTOPHER, JUNIATA COLLEGE, AND TOM FISHER, INEXPENSIVE SYSTEMS, HUNTINGDON, PA

This simulated plot shows the blinkingcursor at X=74 measuring Y=177.

and into an output port. This operation would normallymean wasting an entire output port, because the remainderof the ports pins would always contain stale shifted pix-els. However, the PIC allows A/D input through pins desig-nated for digital input, so all the I/O pins are usable. Figure3 shows the PIC 16C73 port assignments. Listing 1 showsthe code fragment that displays a single pixel on the screen.

Note that the routine requires only six cycles. However, ifyou include the start-of-line pulse (CP1, two cycles), sub-routine calls (two cycles), and other overhead, the worst caserequires 12 cycles. This time budget results in an unaccept-able refresh rate of approximately 50 Hz. The screen areasthat require unchanging information, such as borders, tickmarks, and labels, are stored in program ROM. Because itwould take too many cycles to recover this data from look-up tables (which are cumbersome in the PIC), you code eachbyte explicitly and clock them out 1 bit at a time using theroutine in Listing 2.

You need approximately 700 lines of repetitious codingand a large, binary shape table to specify the static informa-tion; a good editor simplifies this chore. You implement ablinking x-axis cursor by periodically replacing the datum inthe appropriate RAM location with 255 decimal. This oper-ation has the effect of drawing a flashing vertical line abovethe pointed-to datum. By setting 64 screen scans with and64 without the 255, you obtain a blink rate of approximate-ly 2 sec. You control the cursors position by rotating a 50-kV potentiometer that feeds the PICs A/D converterthrough Pin RA2. As the cursor moves, the x and y coordi-nates of its position display numerically at the bottom of thegraph. The updatable, three-digit x and y positions (requir-ing a total of 6 bytes of RAM) make up a classic character gen-erator, with each numerals shape stored in 7 bytes of RAM.

It is essential to frequently update the screen to continu-ously reverse the polarity of the LCDs electrodes and thusprevent the destruction of the display. The M line takes careof this operation by switching the polarity at the beginningof each screen scan. Although it is possible to invoke shortroutines between scans, if the PIC must perform lengthy rou-tines, it is necessary to blank the screen by using a call toErase_Screen. The program requires approximately 1.4kbytes of program memory (in Page 1 ROM) and 135 bytesof data RAM. You can download the program as an MPASM1.40-compatible source file from EDNs Web site, www.ednmag.com. At the registered-user area, go into the Soft-ware Center to download the file from DI-SIG, #2153.Although using a PIC mC as an LCD controller/video RAMimposes severe restraints on what you can display, thisapproach reduces complexity and cost for simple graphs. (DI#2153) e


EDN DESIGN IDEAS

PIC16C73A

RA0

RA2

OSC1

RC1RC2RC3

RC0

VEEVCCVSS

FLM D1

CP1CP2

M

DMF697

9V 5V

10kCONTRAST

MPS2907

50kCURSOR

20 MHz

FIGURE 3

FLM

CP1

CP2

M

D1

LINE 0 LINE 1

FIGURE 2

LISTING 1CODE FRAGMENTFOR A SINGLE PIXEL

LISTING 2CODE FOR OBTAININGSTATIC INFORMATION

The 16C73A sends these signals to the DMF697. FLM is start-of-scan, CP1 is start-of-line, CP2 is data latch, M is driver-volt-age polarity, and D1 is data.

This minimal circuit displays the graph and permits cursormovement; it makes no provision for acquiring data.

EDN DESIGN IDEAS

Metal garage doors may be solid andsecure, but they are not transparent toradio waves. If your garage has alu-minum siding, you may experiencefrustration with the operation of yourgarage-door opener. If you must driveup to the door and nearly touch it ordrive near a window to activate thedoor opener, this Design Idea is for you.The antenna extension in Figure 1moves the receiving antenna beyondthe door so the system can respond toyour command.

Construction is simple. The antennais completely passive and uses a J-poledesign. The antenna uses readily avail-able 300V flat TV twin-lead and RG-17450V miniature coaxial cable. Thelength suits an opener that operates at310 MHz. Most popular openers, suchas Stanley, Genie, and Chamberlain,operate at this frequency. However,some units operate at 315 MHz, somereplacement controls operate at 390MHz, and some automobile manufac-turers offer 380-MHz designs. You canusually find the operating frequency inthe users manual, or you can obtain itdirectly from the manufacturer.

A J-pole antenna consists of a half-wave antenna matchedto the low impedance of the coaxial cable by means of aquarter-wave matching stub. In Figure 1, the half-waveantenna comprises the piece of wire above the notch cut intoone side of the 300V flat TV twin-lead cable. You solder thelower ends of the stub together. Experiments show that theoptimum location of the coaxial tap is 7/8 in. above the short-ed end. You use 14 ft of RG-174 coaxial cable as the lead-in.Route this lead above the garage door and out through theweather stripping without drilling any holes. Be sure that thecenter conductor of the coaxial cable connects to the half-wave side of the twin-lead and that the ground braid con-nects to the notched side of the twin-lead. Solder both theseconnections and cover them with clear silicone rubber toprotect them from weather conditions.

Prepare the end of the coaxial cable that connects to theexisting garage-door antenna by exposing the center con-ductor and soldering on a 6-in. length of hookup wire. Youcan insulate the connection with heat-shrink tubing or tape.Twist the hookup wire tightly around the existing antennawire for its full length to form a gimmick capacitor suitablefor coupling the signal into the receiver without undulyloading the receiver and altering its characteristics. Secure

the shield of the RG-174 coaxial cable to the frame of thedoor opener to effectively ground it. You can locate theantenna above the garage door on the wood trim. Do notstaple across the 300V twin-lead.

Mount the twin-lead to the door using adhesive pads andnylon cable ties or by means of a single small nail or screwat each end through the center web of the twin-lead. You canattach the coaxial cable to the garage rafters or ceiling withthe same nylon cable ties and adhesive to keep it out of theway of moving parts. Route the cable above the door to allownormal operation of the door and out below the garage-doorheader beam so that the doors weather stripping seals whenthe door closes.

The addition of this antenna extension to any garage-dooropener markedly increases operating range. Measurementsshow an improvement of approximately 2.5 dB, equivalentto a 30 to 40% increase in range. The improvement is espe-cially noticeable for installations in which the garage is effec-tively shielded by metal doors, metal siding, and a lack ofwindows. (DI #2152) e


HOOKUPWIRE

6 IN. 14 FT

SHORTEDTOGETHER

TWIN-LEADTV CABLE

NOTCH TOBREAK LEAD ON

ONE SIDE

GROUND LUG

RG-174

rQ

iQ

IN.

8 IN.

IN.

iQ17 IN.

iU

FIGURE 1

Antenna extension provides open-door policyRICHARD PANOSH, VISTA, BOLINGBROOK, IL

A sensitivity treatment for your garage-door opener uses readily available coaxialcable and TV twin-lead in a simple configuration.

EDN DESIGN IDEAS

In the proximity detector of Figure 1, a 4-in.-sq piece of cop-per-plated pc board serves as an antenna that forms oneplate of a capacitor. An approaching (grounded) personserves as the other plate, producing a capacitance value of 2to 5 pF that increases as the person approaches. At 6 in. fromthe copper plate, for example, the person produces a capac-itance value of approximately 2 pF.

A simplified circuit illustrates how the circuit transformsdistance/capacitance into a proportional voltage (Figure 2).Transitions of the input square wave apply directly to thelower input of the exclusive-OR (XOR) gate but are delayed0.6933R13C1 sec before the comparator reconstructs thetransitions and applies them to the upper XOR input. R2 andC2 filter the resulting XOR output to produce a voltage pro-portional to distance.

The XOR outputs duty cycle is proportional to the sum ofthe R1-C1 networks delay and the comparators propagationdelay, so a small variation in comparator delay can masksmall changes in antenna capacitance. The circuit in Figure1 overcomes this limitation using a dual comparator (IC1).Passing the XOR inputs through nearly identical compara-tors largely nullifies the effect of offset voltage, drift, andpropagation delay through the comparators.

Figure 1s delay capacitance consists of a 33-pF capacitor,C1, in parallel with 15 pF (6 in. of coaxial cable at 30 pF perfoot) and the 4-in.-sq antenna plate. This capacitancecharges to 5V through R1 during each positive half cycle ofthe input square wave. When no one is near the detector,this capacitance equals 48 pF and produces a delay of 16.5nsec at the upper XOR input. With a hand 6 in. from thedetector, the capacitance rises to 50 pF and produces a delay

Dual comparators stabilize proximity detectorARTHUR HARRISON, US ARMY RESEARCH LABORATORY, ADELPHI, MD,AND JOSEPH STERN, MAXIM INTEGRATED PRODUCTS, SUNNYVALE, CA

+

IC2AMAX407_

+562

IC2B_

+

IC1B_

+

IC1AMAX912_

+

R22015

TURNS

1000

10.0

5V

2

3

0.1 F

30.1k

1

Q12N3904

R375k

TP2

TP1

5V

5V

249

HLMP3762

10k1N41487

8

4

5V

10k

5

6

1k0.22 F

5V

1k

0.1 F

0.1 F5V

0.1 F

FOSC=1 MHz0 TO 5V

R1499

LE1

Q1

Q2

GND1C8

0.1 F

C133 pFNPO

45303

11

2

4 3

10k

1/4 74HC86N

14

4.7 F

5V 5V-DCINPUT

15

LE2

GND213

14

9

10

4990

10k

10k 0.22 F

5V

RG316/U6-IN. LENGTH

ANTENNA PLATE4 IN. SQ

This proximity detector lights the LED when a person approaches the antenna plate within a threshold distance set by poten-tiometer R2.

Exclusive-ORing two inputs, one delayed by the R1-C1 network,and subsequent filtering by R2 and C2 implements a capaci-tance-to-voltage conversion.

VOUT+

_

+V

C1

R1+V

V+V

+V

R2

C2

FIGURE 2

FIGURE 1

EDN DESIGN IDEAS

of 17.3 nsec, yielding a time difference of only 0.8 nsec.To detect such small time differencesover temperature

and with accuracythe comparators must be stable in off-set voltage and propagation delay. (Changes in offset volt-age as well as propagation delay affect delay time.) One 10-nsec comparator is generally stable to within 1 nsec. Toresolve subnanosecond intervals, use the dual-comparatorapproach of Figure 1, which increases the useful resolutionby a factor of four to five.

Op amp IC2A offsets and amplifies the dc voltage at TP1,which corresponds to the distance between hand and anten-na plate. A hand movement toward the antenna causes thevoltages at TP1 and TP2 to rise. IC2B and Q1 serve as a com-

parator with hysteresis, which compares the TP2 voltage with2.5V. Thus, any TP2 voltage above 2.5V (which correspondsto a proximity of 6 in.) turns on the LED. You can adjustpotentiometer R2 to set a threshold other than 6 in., and youcan connect a DVM at TP2 to read out the proximity in inch-es. R3 adds hysteresis to ensure a well-defined transition.

To ensure frequency stability for the high-speed dual com-parator in Figure 1, the copper-clad pc board should have aground layer in addition to the circuit layer. Power-supplybypassing should include 0.1-mF ceramic capacitors that sitvery close to the comparators supply terminals. (DI #2150)

e


The low-cost, three-transistor boost switching regulator inFigure 1a is a modified astable multivibrator comprising Q1,Q2, and L1, which substitutes as a load for Q2. At the full out-put power of 200 mW, the oscillation frequency is approxi-mately 60 kHz. The efficiency is 65% with VOUT equal to 24Vand sourcing 8 mA.

When the base of Q2 is high, energy stores in L1s magneticfield. When the circuit drives the base of Q2 low, the inducedvoltage from L1s magnetic field collapses to add with thesupply voltage. This voltage spike charges C1 through D1.When the accumulated charge in C1 results in a voltageequal to the zener voltage of D2 plus 0.6V, Q3 pulls Q2s baseto ground, decreasing the amount of time Q2 is on in subse-quent oscillations and thereby decreasing the energy trans-

ferred to C1. This feedback through D2 regulates the outputvoltage to 24.6Vthe tolerance of D2. To change the outputvoltage of the circuit, simply change the zener voltage of D2.

Many VCOs require tuning voltages as high as 20V, andyou can use this switching regulator to generate a 0 to 20Vtuning voltage from a 0 to 5V control voltage (Figure 1b).The circuit configures one-half an LM358N as a noninvert-ing amplifier with a gain of 4. C1 eliminates gain for the noisegenerated by the 24V supply. You can manually adjust thetuning voltage using R1 or control the voltage using feedbackfrom a PLL. (DI #2159) e


Low-cost switcher converts 5 to 24VPAUL C FLORIAN, PLANO, TX

A simple three-transistor switching regulator (a) supplies 24V and 8 mA. The circuit can help provide a 0 to 20V VCO tuningvoltage from a 0 to 5V control voltage (b).

+

+

+

C1100 F

10VELECTROLYTIC

C110 F35VELECTROLYTIC

10k 1k 1k

0.001 F 0.1 F

0.1 F

150 pF

0.047 FQ1

R1

C1

L1

VOUT

D1

D2

Q2

Q3

330 HDCR2ISAT 200 mA

5V

5V24V

1N4933

24VZENER

1N5252B

24V8 mA

10k

0 TO 5VCONTROL VOLTAGE

300k, 1%

3

2

8

4

1 0 TO 20VTO VCO

LM358N

100k1%

(a) (b)NOTES:Q1 TO Q3 ARE 2N3904.ALL RESITORS ARE 5%.

Qw

FIGURE 1

EDN DESIGN IDEAS

+ +

++

IN

CLKOUT

8

1

OPOUT OPIN V+

5

GND V

3 4 7

5V

5V

C30.1 F

C20.0047

FQ1

2N7000

C10.1 F

C50.1 F

R6100k

C40.1 F

C80.1 F

C100.1 F

C7470 F

C9470 F

D11N4001 T1

D21N4001

C1110 F

C1210 F

R1390k

R310k1%

R410k1%

R510k1%

R2100k

R71k

R810k

R101k

R91M

C60.1 F

IC378L05

IC1C

IC2

J3OUTPUTJ1

INPUT

J2COMM

+

+

+

13

1214

0 TO 1VRMS60 Hz

0 TO10V DC

CALIBRATE

31

2

4TLC2274

811

6

57

fC=71 Hz

6 2

+

9

10

5V

VO VI

GND

IC479L05

VO VI

GND

120V AC12V AC5V

5V

5V

MAX292

IC1AIC1B IC1D

FIGURE 1

Chopper techniques convert a dc input signal from a process variable to a 60-Hz ac signal for measurement on a three-phasepower monitor.

The circuit in Figure 1 allows you to record process variables(4 to 20 mA, 0 to 10V dc) on a three-phase power monitordesigned to record only ac waveforms. Many of theserecorders have a seventh channel, normally used for record-ing neutral current, which you can use as a process-variableinput. The circuit operates by generating a 0 to 1V-rms out-put sine wave whose amplitude is a function of a 0 to 10V-dc input signal. IC1 can be any rail-to-rail quad op amp ratedfor 5V power supplies. Input stage IC1A buffers the input-voltage divider R1-R2 and drives the two-quadrant multipli-er, IC1B. IC1B acts as a multiplier by using Q1 to switch its gainfrom 1 to 1.

When Q1 is off, IC1B has a gain of 1. Switching Q1 at 60Hz chops the dc signal applied to the input into a 60-Hzsquare wave whose amplitude is proportional to the inputsignal. The chopping signal comes from Schmitt trigger IC1C.A portion of the ac power signal goes to IC1C through volt-age divider R8-R7. R9 and R10 provide a small amount of hys-teresis to prevent oscillation and ensure fast switching. Theoutput of IC1C is the 60-Hz square wave that controls Q1. The

chopped signal from IC1B connects to the switched-capaci-tor filter, IC2. This eight-pole lowpass filter converts thesquare wave from IC1B to a sine wave.

Capacitor C2 sets the filters 71-Hz cutoff frequency. C5and R6 form a 16-Hz highpass filter that removes any dc off-set from the output of the switched-capacitor filter. IC1Dbuffers the filter and provides a 0 to 1V-rms, 60-Hz output.Calibration involves applying a 10V-dc signal to the inputand adjusting R2 until the output reads 1V rms on an ac volt-meter. Measurements show linearity within 1% over theentire input range. To use the recorder, connect the input tothe process variable under measurement, and connect theoutput to any voltage-input channel on the 1V-rms powerrecorder. You can also use the circuit on current-input chan-nels designed to use low-voltage, 1V-rms current clamps. Torecord 4- to 20-mA signals, shunt the input with a 500Vresistor. (DI #2157) e


60-Hz modulator records process variablesWARREN JOCHEM, RESEARCH TRIANGLE INSTITUTE, RESEARCH TRIANGLE PARK, NC

Entry blank must accompany all entries. $100 Cash Awardfor all published Design Ideas. An additional $100 CashAward for the winning design of each issue, determinedby vote of readers. Additional $1500 Cash Award forannual Grand Prize Design, selected among biweekly win-ners by vote of editors.

To: Design Ideas Editor, EDN Magazine275 Washington St, Newton, MA 02158

I hereby submit my Design Ideas entry.

Name

Title

Phone Fax

E-mail

My e-mail address may be published Yes No

Company

Address

Country ZIP

Design Idea Title

Social Security Number(US authors only)

Entry blank must accompany all entries. (A sepa-rate entry blank for each author must accompany everyentry.) Design entered must be submitted exclusively toEDN, must not be patented, and must have no patentpending. Design must be original with author(s), mustnot have been previously published (limited-distributionhouse organs excepted), and must have been construct-ed and tested. Fully annotate all circuit diagrams. Pleasesubmit software listings and all other computer-readabledocumentation on a IBM PC disk in plain ASCII.

Exclusive publishing rights remain with Cahners Pub-lishing Co unless entry is returned to author, or editorgives written permission for publication elsewhere.In submitting my entry, I agree to abide by the rules of

the Design Ideas Program.

Signed

Date

Design Idea Entry Blank

Your vote determines this issues winner. Vote now,by circling the appropriate number on the readerinquiry card.

The winning Design Idea for the September 1, 1997, issue isentitled Transistor trio makes vector anemometer, submit-ted by W Stephen Woodward of University of North Carolina(Chapel Hill, NC).

EDN DESIGN IDEAS

A simple and inexpensive implementa-tion using an eight-pin 12C508 controller(Microchip Technology, Chandler, AZ)provides both bit-rate detection and asynchronous, appended-clock outputfrom an asynchronous input-data stream(Figure 1a).This implementation relies on two

code sequences (Figure 1b). A trainingsequence first identifies the bit rate. Thissequence begins with register andcounter initialization followed by a gapdetection. Following the detected, 0.325-sec, high-true gap, the controller moni-tors eight transitions. Between each tran-sition, a local loop counter counts thenumber of loops necessary to arrive atthe next transition. The controller teststhe accumulated number of loopsbetween transitions to identify the countperiod that resulted in the fewest loops.After processing all eight transitions ofthe training sequence, the controllerevaluates the shortest maintained countaccording to a table index based on thetraining loop s code length. Because thecontroller s timing is crystal-based andthe loop s path lengths are equal, theprocessed count corresponds to the bitrate that the controller then uses to definea delay necessary for the second codesequence.The second output-code sequence

begins by locating a fixed, second gap ofapproximately 40 msec. This time allowsthe controller to completely terminate thetraining sequence before beginning thecontroller s main iterative loop. Thesequence then takes the delay, identifiedearlier, and processes the serial input data on Pin 4 to the out-put at Pin 7 while maintaining complementary clocks on pins 5and 6. Equalizing the instruction paths for this code sequenceis a key requirement of this application.The controller uses a 3.6864-MHz crystal to provide precise

baud-rate timing. This scheme allows the combined code appli-cations to support 300- to 9600-bps asynchronous inputs. An8-bit training pattern of 55 (hex) allows multiple single-bit iso-lated transitions to qualify the detected bit rate (Figure 1b).The output-sequence code provides resynchronization of

the clock-related delay counters at the input data-transition

edges on Pin 4. This resynchronization allows flexibility in sup-porting data-bit edge delays and distortion and variations in thecontroller s crystal or external timing reference s accuracy. Youcan download applicable code from EDN s Web site, www.edn-mag.com. At the registered-user area, go into the SoftwareCenter to download the file from DI-SIG, #2158. (DI #2158)


Synchronizing controller detects baud rateWILLIAM GRILL, RIVERHEAD SYSTEMS, LITTLETON, CO


EDN DESIGN IDEAS

MICROCHIP12C508

DATA OUT

DATA IN

CLOCK A

CLOCK B

GND1

2

3

4

5

6

7

8VDD

3.6864 MHz

200

15 pF (TYPICAL)

DATA IN

DATA OUT

CLOCK A

CLOCK B

GAPEIGHT-TRANSITION

TRAINING SEQUENCE GAP NORMAL MODE(b)

(a)

FIGURE 1

A simple controller (a) provides baud-rate information and a synchronous output clock by usingtwo code sequences (b).

EDN DESIGN IDEAS

Li-ion battery chargers must apply constant current when thebattery charge is low and constant voltage when the batterycharge is high. To avoid battery damage, the tolerance on theapplied voltage must be less than 1%. The charger in Figure 1complies with these requirements.The circuit converts energy from 120V ac to a regulated volt-

age or current as necessary to charge two Li-ion cells in series.IC1, a popular controller for offline power-supply applications,operates as a forward converter, producing an isolated, half-wave-rectified battery voltage or current from the full-wave-rec-

tified line voltage. This converter operates at 250 kHz and han-dles ac inputs from 90 to 135V.IC2 is a chemistry-independent battery charger. Though

designed to drive an external transistor, in this case, it drivesthe MOC211 optoisolator to control IC1 across the isolation bar-rier. IC2 s internal circuitry sets the battery voltage to8.4V0.5%. The 0.1V current-sense resistor, R1, and ISET resis-tor, R2, set the battery current to 1A2%. (DI #2161)


+

+

+

DRV

PGND GND ISETISEN

VCC

VL

CCI

CCV

ON CELL2

OFFV

BATT

DCIN CS+ CS

IC1MAX846

IC2UC3845B

REF OUT

R/C

GND FB COMP

120VAC

LINE

EMI FILTER (DELTA 01DEEW3R)CTX03-13384-X1

MURS16039k

47k1W

12

1

7

61000 pF220 F

250V

DF04S

MBRS1100

MBRS1100

470 F10V

DO3316-47347 H

8

7

10 F

0.1 F

470pF

470pF

6.2k

1N4148

11

IRF830

2

6

3 1k

21/2W

1/2 MOC211(MOTOROLA)

4.7k

5 2 1

R10.1

1/2W

15 4 7

8

2

3

5

11 10

12

16 1 13 140.1 F

0.1 F

0.1 F

4.7 F

TWO-CELLLi+BATTERY

MBRS120

1k 1N4148

1/2MOC211

16.5k1%

R2

4

FIGURE 1

Charge Li-ion batteries from ac line voltageMATT SCHINDLER, MAXIM INTEGRATED PRODUCTS, SUNNYVALE, CA

A high-voltage controller, IC1, transformer, and chemistry-independent battery charger, IC2, charge two-cell Li-ion batteries directly from the acline.

EDN DESIGN IDEAS

An unshielded twisted-pair cable that is transformer-coupled toa digital system can easily act as a radiating antenna, notbecause of the differential analog signal the cable carries, butbecause of common-mode currents induced by unwanted straycoupling from the digital portions of the system. These currentsfrom fast digital transitions contain harmonics in the hundredsof megahertz and can be a nightmare to design engineers whohave to make systems conform to radiated-emissions limits.If the coupling transformer has a center tap on the winding

to which the cable attaches, you can use this tap to reduce thelevel of these nasty common-mode currents on the cable. Con-necting the tap to a quiet earth ground provides a path to shuntthese currents harmlessly to earth before they can sneak outthe cable and radiate (Figure 1). A capacitor in the connectionprovides the same RF grounding function but presents a highimpedance to any 60-Hz ground loop currents if the far end ofthe cable also connects to a ground-referenced transformerwinding. This capacitor should be only a few hundred pico-farads, must have short leads and circuit traces between trans-former tap and good earth ground, and must have a sufficient-ly high voltage rating to withstand high-voltage transients as theend market requires.The technique works as follows: The opposite ends of the

transformer winding are balanced with respect to ground; thatis, the windings push and pull with equal amplitude but oppo-site polarity on each and every transmitted data symbol. Thecenter of the transformer is the pivot on which the winding bal-ances. As such, this pivot point is neutral relative to ground; anactual connection to ground makes no difference to the differ-

ential information signal.If a common-mode signal impresses both conductors, the

resulting currents at opposite ends of the winding flow bothtoward and away from the center tap in the same phase. Thisflow causes magnetic cancellation between the two halves ofthe winding, and the resulting inductance is very low, resultingonly in the residual leakage inductance. In this way, both con-ductors have a low-impedance path to earth ground withoutaffecting the wanted differential signal. Note that filtering eachconductor with an RC network also provides the low-imped-ance path to ground; unfortunately, this filter also destroys thedifferential signal in high-bit-rate applications.The technique in Figure 1 also helps reduce susceptibility to

common-mode currents that external fields induce; the unwant-ed currents pass harmlessly through each half of the trans-former winding and cancel each other out. Interwinding capac-itance the usual mechanism by which common-modevoltages can affect transformer-coupled receiver inputs isless critical because both conductors have a low-impedancepath to ground, resulting in minimum common-mode voltage oneach conductor.Using a common-mode choke in addition to the center-tap

trap results in a real common-mode killer. The two techniquescomplement each other, and it can be helpful to use bothtogether in stubborn cases. As Figure 1 indicates, you canplace the common-mode choke virtually a transformer on itsside in line with the cable, preferably at a point just before thecable exits the (ideally) shielded enclosure to avoid stray-noisepickup on the cable after the choke. A similar but opposite mag-

Emissions killers trap common-mode currentsGLEN CHENIER, FUJITSU NETWORK COMMUNICATIONS, RICHARDSON, TX

A center-tap capacitor connected to earth ground implements a common-mode current trap and reduces RF emissions. A common-mode chokein addition to this center-tap trap results in a common-mode killer.

CENTER-TAPCAPACITOR (470 pF WITHSUFFICIENT VOLTAGE RATING)

DIGITALDRIVER

COMMON-MODECHOKE

UNSHIELDED TWISTED-PAIR CABLE

OPTIONAL 10- TO 301-pF CAPACITORS FOR ANY HIGH-FREQUENCY DIFFERENTIAL-MODE EMISSIONS

FIGURE 1

EDN DESIGN IDEAS

netic magic takes place in the common-mode choke, whichmust present a high series impedance instead of a low shuntimpedance to common-mode currents. The winding turns ratiois 1-to-1, and the polarity is such that the magnetic fields fromthe differential signal now cancel, resulting in almost zero atten-uation other than that resulting from the leakage inductance.On the other hand, the common-mode currents cause mag-netic addition, which results in high impedance and reduces thelevel of unwanted currents.You can also make a common-mode choke by slipping a

large ferrite sleeve over the two conductors of the twisted pairsor by winding one or more turns of the twisted pairs through alarge toroid doughnut. Many ferrite suppliers make these

sleeves and toroids just for this purpose. Also, well-balancedcommon-mode chokes of the more conventional transformer-like construction are also readily available from datacomm-transformer suppliers.Two capacitors following the common-mode choke can

reduce high-frequency differential-mode emissions caused bynon-common-mode currents. (DI #2160)


The circuit in Figure 1 allows standard TTL logic levels to safe-ly drive a high-power dc load. The circuit provides for both sig-nal and ground isolation as well as a solid-state circuit break-er.

The input signal drives IC1A, which in turn provides drive cur-rent for optoisolator IC2A. In the absence of an overcurrent con-dition, IC2B conducts the signal to the gate of the MOSFET.When sufficient current passes through current-sense resistor,

R1, to cause a voltage drop of approximately 0.7V, SCR Q1latches on. When Q1 is on, the circuit pulls Pin 3 of IC2B low,which stops the transistor side of IC2B from conducting. R2 thenholds the gate of the MOSFET low, which prevents it from con-ducting until you reset the SCR. (DI #2163)


LOAD(MOTOR ORVALVE COIL)

24V24V

1N4007

OPTIONAL

RESET

1N4007IRF540

CONTROL POWER GROUND

Q1EC1030

4.7kR10.1

5W, 1%

2.2k

R2 1k

CONTROL POWERGROUND

LOGIC-LEVEL PWM INPUT

POWER

56

3

5V

330

INPUT74HC14

21IC1A

IC2B12

IC2APS2501-2

8

7

FIGURE 1

An overcurrent condition in this isolated PWM driver turns on SCR Q1, which stops IC2B from conducting.

Isolated driver forms solid-state circuit breakerBOB WATSON, CORLEY MANUFACTURING CO, CHATTANOOGA, TN

EDN DESIGN IDEAS

To measure a high-frequency signal using an 8-bit mC, the timeperiod of the measured frequency must be relatively close tothe internal clock of the mC. For example, if the internal clockperiod is 1 msec, then the maximum frequency that you canmeasure is 1 MHz in most mC applications.However, you can use the circuit in Figure 1a to measure a

frequency much higher than the internal clock frequency of themC. This circuit uses an external binary ripple counter operat-ing in asynchronous mode. The circuit gates the incoming fre-quency to the counter using NAND gates and control lines fromthe mC. To enable counting, the mC sets CNTL1 and CNTL2 to1. Once the measurement time is complete, CNTL1 resets to 0,which stops further inputs to the counter.To read the value of the low 12 bits of the frequency, the mC

toggles CNTL2 N times until the internal 8-bit timer incrementsby one. The low 12-bit value of the frequency is then equal to4096 N. Reading the value of the counter in this mannerrequires only one I/O line as opposed to 12 lines to read thecounter s 12 bits. In combination with the internal 8-bit counterin the mC, a 20-bit frequency measurement is possible. The lim-iting factor of the measurement is the maximum frequency inputto the NAND gates and the ripple counter.Although the circuit in Figure 1a is straightforward, the circuit

does involve the additional cost of a 14-pin NAND gate and a16-pin counter, which may be undesirable in many applications.In PICmicro 8-bit mCs, the internal 8-bit counter/timer, TMR0,has an associated 8-bit divider, or prescaler. The counter hasread/write capability, but you can t read the prescaler value.You can modify Figure 1a s circuit using a PICmicro mC toimplement a 16-bit frequency counter (Figure 1b).This circuit uses the internal 8-bit prescaler to divide the

incoming frequency. The circuit feeds the output of theprescaler to the 8-bit timer, TMR0, for measurement. As withFigure 1a s circuit, once the gate time is over, CNTL1 blocksadditional clocks from the input signal. Then, CNTL2 pulses the8-bit prescaler N times until the 8-bit timer/counter, TMR0, incre-ments by 1. In this case, the lower 8-bit value of the measuredfrequency equals 256 N. The mC then concatenates the valueof the counter with the 8-bit timer s value to give a 16-bit valueof the measured frequency.Figure 1c shows a further simplification of the circuit in Fig-

ure 1b by replacing the NAND gates with two transistors andfour resistors. To start the counter, the mC configures CNTL1and CNTL2 as inputs or in a high-impedance mode. Thus, thecircuit directs the incoming signal to the prescaler and in turnto the 8-bit timer/counter, TMR0. When the gate time is com-plete, the mC makes CNTL1 an output going low. A low CNTL1deactivates the transistor, whose output becomes an open col-lector. The mC can now make CNTL2 an output normally highand going low to pulse the input to the prescaler. The mC puls-es CNTL2 low N times until the value of TMR0 increments by 1.The low 8-bit value of the frequency is equal to 256 N. To begincounting again, the mC reads the value of TMR0, which clearsthe prescaler, and again configures CNTL1 and CNTL2 as

inputs.Note that the architecture of the PICmicro mC allows accu-

rate timekeeping for the gating pulse because the timing of asoftware loop is predictable and accurate to within one instruc-tion cycle; a PICmicro mC executes each instruction in onecycle, except for branch instructions, which take two cycles. (DI#2164)


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EDN Design Ideas 1998

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Transcript of EDN Design Ideas 1998