EDN Design Ideas 2001

182
E lectronic ballasts for fluorescent lamps use various techniques to turn on the bulbs. The design usually in- volves a compromise between turn-on voltage and lamp life because the two are inversely related. One way to reach a rea- sonable compromise is to initially allow a momentary inrush current to warm the filaments, followed by a series of inter- rupted short circuits across the lamp that generate the required high voltage to trigger the fluorescent. With a preheated filament, the necessary strike potential reduces to half. The trigger circuit in Figure 1 controls the electronic switch across the bulb. At start-up, IC 1D ’s output is low as C 1 and C 2 charge toward V CC . IC 1D ’s low output pulls IC 1C ’s inverting input low, which causes V O to clamp high. A high level at V O closes the switch and forces current through the filaments. After approxi- mately 0.5 sec, IC 1D ’s output changes state and allows IC 1C to accept the high-fre- quency signal at its noninverting input. IC 1A is a square-wave oscillator, which causes V O to be a high-frequency-pulse series that lasts for approximately 1 sec. At the end, C 2 reaches a high enough volt- age to force IC 1B to pull down IC 1A ’s non- inverting pin to ground. With a ground- ed IC 1A output, V O clamps low. The high-frequency switching strikes the preheated lamp. In case the bulb fails to start, the circuit turns off and then on again. Residual charges on the capacitors discharge through D 1 and D 2 to ensure precise timing. _ + IC 1A _ + IC 1C _ _ + + IC 1B D 1 D 2 C 2 2.2 mF C 1 2.2 mF IC 1D 82k 10k 1M 10k 10k 100k 100k 7.5k 100 pF 12V 12V 12V 12V 12V 14 9 8 12V 12 13 3 10 11 1M 1M 1M 1M 1M 1M 1M 1M 0.5 SEC 1 SEC V CC V 0 5 4 2 6 7 1 1.5 SEC 0.5 SEC 330k 10k 12V ELECTRONIC SWITCH TO HALF-BRIDGE CIRCUIT NOTES: IC 1 =LM339N. DIODES=1N4606. Figure 1 Preheat starter for electronic ballast Arthur E Edang, Don Bosco Technical College, Mandaluyong City, Phillipines This trigger circuit generates a high-frequency-pulse series to strike a preheated lamp. Is this the best Design Idea in this issue? Vote at www.ednmag.com/edn mag/vote.asp. www.ednmag.com January 4, 2001 | edn 113 ideas design Preheat starter for electronic ballast..............................................................113 Low-cost circuit programs EEPROMs ......................................................114 Circuit yields ultralow-noise VGA..............116 Sequential channel selector simplifies software ......................................120 mC provides timer function ......................124 Edited by Bill Travis and Anne Watson Swager

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Collector of EDN Design Ideas 2001

Transcript of EDN Design Ideas 2001

  • Electronic ballasts for fluorescentlamps use various techniques to turnon the bulbs. The design usually in-volves a compromise between turn-onvoltage and lamp life because the two areinversely related. One way to reach a rea-sonable compromise is to initially allowa momentary inrush current to warm thefilaments, followed by a series of inter-rupted short circuits across thelamp that generate the requiredhigh voltage to trigger the fluorescent.With a preheated filament, the necessarystrike potential reduces to half.

    The trigger circuit in Figure 1 controlsthe electronic switch across the bulb. Atstart-up, IC

    1Ds output is low as C

    1and C

    2

    charge toward VCC

    . IC1D

    s low outputpulls IC

    1Cs inverting input low, which

    causes VO

    to clamp high. A high level atV

    Ocloses the switch and forces current

    through the filaments. After approxi-mately 0.5 sec, IC

    1Ds output changes state

    and allows IC1C

    to accept the high-fre-quency signal at its noninverting input.IC

    1Ais a square-wave oscillator, which

    causes VO

    to be a high-frequency-pulseseries that lasts for approximately 1 sec.At the end, C

    2reaches a high enough volt-

    age to force IC1B

    to pull down IC1A

    s non-inverting pin to ground. With a ground-ed IC

    1Aoutput, V

    Oclamps low.

    The high-frequency switching strikesthe preheated lamp. In case the bulb failsto start, the circuit turns off and then onagain. Residual charges on the capacitors

    discharge through D1

    and D2

    to ensureprecise timing.

    _

    +IC1A

    _

    +IC1C

    _

    _

    +

    +

    IC1B

    D1

    D2C22.2 mF

    C12.2 mF

    IC1D

    82k10k

    1M

    10k

    10k

    100k

    100k

    7.5k100 pF

    12V

    12V

    12V

    12V

    12V14

    9

    8

    12V

    12

    13310

    11

    1M

    1M

    1M

    1M1M

    1M

    1M

    1M

    0.5 SEC 1 SEC

    VCC

    V0

    5

    42

    6

    7

    1

    1.5 SEC

    0.5 SEC

    330k

    10k

    12V

    ELECTRONICSWITCH

    TOHALF-BRIDGE

    CIRCUIT

    NOTES:IC1=LM339N.DIODES=1N4606.

    F igure 1

    Preheat starter for electronic ballastArthur E Edang, Don Bosco Technical College, Mandaluyong City, Phillipines

    This trigger circuit generates a high-frequency-pulse series to strike a preheated lamp.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    www.ednmag.com January 4, 2001 | edn 113

    ideasdesign

    Preheat starter for electronic ballast..............................................................113

    Low-cost circuit programs EEPROMs ......................................................114

    Circuit yields ultralow-noise VGA..............116

    Sequential channel selectorsimplifies software ......................................120

    mC provides timer function ......................124

    Edited by Bill Travis and Anne Watson Swager

  • 114 edn | January 4, 2001 www.ednmag.com

    ideasdesign

    When you migrate to 3.3V systemsupplies, you must usually replaceyour old, reliable EEPROM pro-grammer with a new, overly flexible andexpensive universal programmer. Wecould not find a 3.3V programmer forless than $1000. For less than $100, thecircuit in Figure 1 extends the function-al life of any 5V EEPROM programmer.You can apply the circuit to any bidirec-tional 5 to 3.3V level-translating appli-cation. The key to the circuit lies inchoosing the correct logic families. The74VHC and 74LVC families handle the

    5-to-3.3V conversion better than previ-ous logic families, such as the 74HC se-ries. The 74HC family accommodates3.3V operation, but the input-protectiondiodes clamp the input voltage within adiode drop of V

    DD(Figure 2a). So, ap-

    plying 5V to the input of a 74HC partpowered from 3.3V results in much un-desired current. An external resistorcould limit this current, but this fixwould impact bus speed. The 74VHCTand 74LVC families do not use a reverse-biased diode to V

    DD(Figure 2b), so the

    input voltage can safely rise to 5.5V, re-

    gardless of the supply level.The 74HCT family handles the 3.3-to-

    5V conversion. This 5V CMOS logic fam-ily uses input switching levels skewed toaccommodate TTL-level inputs. The lowand high levels are 0.8 and 2.4V, respec-tively, in comparison with the typicalCMOS levels of 1.5 and 3.5V. Because theinputs receive high levels of 3.3V at most,CMOS-optimized 74HC logic would notguarantee recognition of logic 1 inputs.On the other hand, to a 74HCT poweredfrom 5V, a 3.3V input level represents asolid logic 1. We selected the tristatable

    IC2

    12

    2

    3

    3

    4567

    813

    1

    OEB5

    CEB5

    91012

    11

    8

    765

    4

    IC374VHC541

    IC474VHC541

    OEB3

    WEB3

    CEB3

    OEB1 OEB1

    OEB2

    OEB1

    OEB2

    OEB2

    OEB1

    OEB2

    1 1

    19

    19

    138765

    432

    IC674HCT541

    19

    8765

    4321

    0.1 mF

    V3OE3

    OEB5

    1OE3

    OEB5

    IC574VHC541

    19

    8765

    4321

    IC164-kBYTEEEPROM

    1 2

    3 4

    5 6

    74HC04

    74HC04

    74HC04

    OEB3 OE39 8

    13 12

    74HC04

    11 1074HC04

    74HC04

    CEB30EB3WEB3

    32-PIN PLCC

    5VADDRESS

    BUS5V

    ADDRESSBUS

    3VADDRESS

    BUS3V

    DATABUS

    3VDATABUS

    3VDATABUS

    3VADDRESS

    BUS

    5VADDRESS

    BUS

    5VDATABUS

    5VDATABUS

    5VDATABUS

    0.1 mF

    V3

    0.1 mF

    V5

    0.1 mF

    V3

    0.1 mF

    0.1 mF 0.1 mF2.2 mF 2.2 mF

    V3

    V3V5

    + +

    IN OUTCOM

    2 33.3V

    F igure 1

    Low-cost circuit programs EEPROMsJarrod Eliason, Ramtron, Colorado Springs, CO

    For less than $100, this circuit adapts a 5V EEPROM programmer for 3.3V operation.

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    ideasdesign

    buffer function for the EEPROM-pro-grammer level translation. Thecircuit in Figure 1 programs a3.3V, 64-kbit EEPROM, using a 5V pro-grammer. For the address and controlpins, the output-enable pin of the74VHC chips is constantly active. For thebidirectional data bus, the OEB5 andOE3 signals control the in/out selection.When OEB5 is low and OE3 is high, aread operation takes place, and the EE-PROM has control of the data bus. WhenOEB5 is high and OE3 is low, a write op-eration takes place, and the programmerdrives the data bus.

    A 28-pin DIP socket, IC2, connects to

    the 5V EEPROM programmer. The cir-cuit uses an additional adapter to inter-face to the 32-pin PLCC target device,IC

    1. The 74VHC and 74LVC logic parts

    are not readily available in DIP form, soyou can use SOIC-to-DIP adapters forbreadboarding. If the 74HCT541 is notavailable, you can use the alternate-pinout 241 or 244.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    Anumber of single-chip VGAs vari-able-gain amplifiers are available to-day. Unfortunately, they all havedrawbacks, such as high noise, 55V lim-it, low input impedance, or nonlineargain/frequency characteristics. The cir-cuit in Figure 1 is a 16-step, ultralow-noise VGA that solves many of these

    problems. IC1

    is a low-noise quad opamp, and IC

    2is a quad SPDT CMOS

    switch. The stages switch in successivemultiplication (gain) factors using a TTLbinary code. The values shown provide 0-to 45-dB gain in 3-dB steps. For best low-noise performance, the higher gain stagesprecede the lower gain stages. The circuit

    exhibits approximately 3 nV/=Hz, re-ferred to the input, for most gain settings.The highest noise is 4.5 nV/=Hz at again of 9 dB. Distributing the total gainacross multiple stages increases the overall bandwidth. The output stage has a different configuration to yield a low-output-impedance output driver

    R1

    R2100

    IC1A

    IC2A

    IC1B090

    OPTIONAL RANGE-SHIFT

    ATTENUATOR

    _

    +

    SIGNALIN 3

    2

    4

    15V

    15V

    _

    +

    0.1 mF

    0.1 mF

    0.1 mF

    0.1 mF

    13

    LT1125

    66.5

    115V

    115V

    1 2

    3

    6

    5

    16

    4 SB

    SA

    GND VSS

    VDD

    D

    ADG333

    SB

    SA12

    12D 13 14

    1615

    11

    D

    1110

    IC2BADG333

    SB

    SA

    IC2CADG333ABR

    IC2DADG333ABR

    SB

    SA

    BIT 3

    BIT 2

    BIT 1

    BIT 0

    1

    6 5

    1k

    1k

    1k

    1k

    332

    IC1C_

    +IC1D_

    +

    LT1125CS LT1125CS LT1125CS

    7

    78

    9

    10

    14SIGNAL

    OUT

    2k

    825

    D 1817

    19

    24 dB

    12 dB 6 dB 3 dB

    20

    F igure 1

    Circuit yields ultralow-noise VGADale Ouimette, California Institute of Technology, Pasadena, CA

    This VGA offers ultralow noise, a wide dynamic range, and high bandwidth.

    (a) (b)

    VDD

    PAD PAD

    F igure 2

    The 3.3V-powered 74HC-logic inputs are notamenable to 5V inputs (a); 74HVC and 74LVCinputs have no such problem (b).

  • 118 edn | January 4, 2001 www.ednmag.com

    ideasdesign

    VREF/2

    VIN+

    VIN1

    A GND

    CLK R

    CLK IN

    CS'

    RD'

    WR'

    INTR'

    VCC

    DB7

    DB6

    DB5

    DB4

    DB3

    DB2

    DB1

    DB0

    D GND

    IC2ADC0804

    20

    11

    12

    13

    14

    15

    16

    17

    18

    10

    9

    6

    7

    8

    19

    4

    1

    2

    3

    5

    BIT 3

    BIT 2

    BIT 1

    BIT 0

    VCC

    + 10 mF AT 20V

    _

    +

    RGIC1

    AD620

    R11k

    C11 mF

    C34.7 mF

    R210k

    R31M

    C2140 pF

    +VS

    1VSRG

    3

    1

    2

    8

    +CONTROL

    1CONTROL

    0 TO 5VCONTROL VOLTAGE REF

    15V

    0.1 mF

    115V

    0.1 mF

    7

    4

    5

    6

    GND VCC

    VCC

    S1ADICT S1ADICT

    +

    S1ADICT

    D1

    F igure 2

    An ADC controls the gain-setting codes for the circuit in Figure 1.

    at all gain settings.If you need to remotely

    control the gain, you mustconcern yourself with groundloops that can compromisethe low-noise characteristicsof the circuit. One solution isto place optoisolators in thefour digital-control lines, sothat no ground connectionexists between the two endsof the cable except throughthe power supply. Themethod you use is an analogdifferential-control voltageusing an ADC to generate the4 bits. Figure 2 shows a cir-cuit that performs this func-tion well. IC

    1is a differential

    receiver, and IC2

    is an 8-bitADC. In some applications,you could get away with usingonly the ADC, because it already has adifferential input. However, you musttake care not to exceed the narrow com-mon-mode range of the ADCs input. Amore robust solution is to place a differ-ential receiver in front of the ADC, asshown. R

    1and C

    1 form a lowpass filter for

    the control voltage to the ADC. The 4high-order bits from the ADC control theCMOS switches. As shown, the ADC op-

    erates in a self-clocking mode and needsno other controls.

    R2

    and C2

    control the sampling fre-quency, approximately 640 kHz for thevalues shown. D

    1, R

    3, and C

    3provide

    power-up initialization for the ADCsclocking function. The control-voltagesteps are 310 mV apart, providing amplenoise immunity. Table 1 shows the per-formance of the overall circuit with ana-

    log control. You can use R1

    and R2

    in Figure 1 to shiftdown the overall gain rangewith little sacrifice of noisecharacteristics. You can obvi-ously alter the individual gainstages to yield other rangesand step sizes, such as 0 to 30dB in 2-dB steps. At the ex-pense of circuit simplicity,you could replace the quad opamp with four ultra-low-noise op amps, such as theLT1128 or AD797. This re-placement lowers the noise toapproximately 1.4 nV/=Hz.You could also increase thenumber of stages, therebyproviding a wider dynamicrange, finer gain steps, orboth. The benefits of this cir-cuit over commercially avail-

    able single-chip VGAs include ultra-lownoise, high bandwidth, 613V range, highinput impedance, ground-loop immuni-ty, and user-defined dynamic range andstep size.

    TABLE 1PERFORMANCE VERSUS GAINNoise

    Gain (referred to input) 3-dB bandwidthStep (dB) V/V (nV/==Hz) (MHz)0 0 1 3.1 10.51 3 1.4 3.8 7.72 6 2 4.4 5.13 9 2.8 4.5 4.64 12 4 3.6 2.75 15 5.6 3.6 2.76 18 7.9 3.7 2.67 21 11.2 3.7 2.68 24 15.8 3 0.889 27 22.4 3 0.8910 30 31.6 3 0.9411 33 44.7 3 0.9612 36 63.1 3 0.9713 39 89.1 3 0.9714 42 125.9 3 1.0415 45 177.8 3 1.02

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

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    An efficient but powerful circuitis useful for a variety of applicationswith limited I/O and for which youwant to use one input to sequentially se-lect a different output channel (Figure 1).When the software changes the state ofonly one input, the circuit sequentiallyselects one output channel at a time fortest purposes. Because the test-applica-tion environment is potentially harsh, thecircuit must have relatively high noiseimmunity and transient protection at theinputs. You must also be able to reset thecircuit to resynchronize the hardwarewith a test program after any interrup-tion in testing.

    Although the resulting circuit mayseem simple and standard, it is distinctlyrobust. The delayed reset signals at IC

    2s

    Pin 1 and IC3s Pin 2 return the counter

    and flip-flop ICs to their initial state sothat OUT

    1is the first channel active at the

    first count. The power-on and switch-ac-tivated reset circuit includes R

    1, D

    3, and

    D4

    to protect against ESD that could arcover the switch contacts when someonefirst touches the switch. The IN signal in-put circuit has similar transient protec-tion with R

    2, D

    1, and D

    2. A simple RC os-

    cillator generates the clock signal at IC2s

    Pin 9, and the second four-stage binary-ripple counter, IC

    3, divides this clock by

    16. The oscillator frequency is approxi-mately 21 Hz, but you can change R

    3and

    C1

    to produce the desired frequency,which is approximately 1/R

    3C

    1. You can

    also use a potentiometer in place of R3

    tomake the frequency adjustable. Keep inmind that the flip-flop clock-cycle peri-od should be much less than the expect-ed active and inactive periods of the INsignal but long enough to produce ade-quate debouncing of the input signal tomaintain good noise immunity. The cir-cuit serves a low-speed application, so theclock at IC

    2s Pin 9 is 1.3 Hz.

    The circuit filters and buffers the INsignal before sending it to the flip-flop

    0.1 mF 0.1 mF 0.1 mF

    0.1 mF

    C10.1 mF

    0.1 mF

    0.1 mF

    VCC GND

    RST

    D0

    D1

    D2

    D3

    Q0

    Q1

    Q1

    Q2

    Q3

    74HC175

    VCC

    IC3

    IC2IC1CIC1B

    IC1A

    IC1D IC1E

    IC4

    GND

    CLKA A0Y0Y1Y2Y3Y4Y5Y6Y7 I8

    I1I2I3I4I5I6I7

    A1

    A2CLKB

    RSTA RSTB

    Q1A

    Q2A

    Q3A

    Q4B

    74HC393

    VCC GND

    CS2

    CS1

    LE

    74HC237

    IC5

    01OUT8OUT1OUT2

    OUT3OUT4OUT5OUT6OUT7

    02

    030405

    06

    0708

    VCC GND

    UDN2981

    16 8

    3

    4

    5

    1

    2

    3

    6

    8

    15141312111097

    12345678

    5V

    0.1 mF

    5V

    5V 5V

    14 167 8 9 10

    1

    3

    2 12

    5 4

    CLK

    3 4 4

    5

    12

    13

    9

    5 6 2

    7

    6

    10

    15

    10k

    5V

    5V

    D11N4148

    D21N4148

    D31N4148

    D41N4148

    10k

    R11k

    R3470k

    IN

    141 2

    7

    5V

    5V

    2.2M

    RESET

    9 8 11 10

    18171615

    14

    13

    1211

    F igure 1

    Sequential channel selector simplifies softwareAlex Knight, Cummins Engine Co, Columbus, IN

    A robust circuit uses one input to sequentially select one output channel at a time.

  • 122 edn | January 4, 2001 www.ednmag.com

    ideasdesign

    input at IC2s pin 4. The Schmitt invert-

    er, IC1

    with its built-in hysteresis and thecascaded flip-flop circuit provide highimmunity to noise, and the cascaded flip-flop ignores any glitches on the input sig-nal that occur asynchronously to the flip-flop clock signals positive-goingtransitions. The circuit uses the Q

    1out-

    put signal as the CLKA

    clock input to thefirst four-stage binary ripple counter, IC

    3.

    Negative-going transitions increment thecounter as the timing diagram indicatesat counts 1, 2, and 3 (Figure 2). The cir-cuit uses the Q

    2output to select the ac-

    tive-high CS1

    chip-select input of IC4s

    one-of-eight decoder, which allows plen-ty of time for the ripple counter outputsto stabilize, even at high flip-flop clockspeeds. These outputs do not simultane-ously change states. With CS

    1high, the

    positive-going Q3

    output signal at the LE

    input of the decoder (IC4, pin 4) latches

    the output channel that the state of theA

    0-to-A

    2address inputs select. Latching

    the output channel ensures you that anysubsequent noise-induced counter-out-put state changes will not affect the out-put-channel states. While CS

    1is low, the

    Y0-to-Y

    7outputs from IC

    4are also low.

    This design maintains a similar off-timefor all of the output channels, as reflect-ed in the input signal, although the cir-cuit delays any change of state for eachof the outputs by approximately two cy-cles of the flip-flop clock period.

    IC5

    can drive loads that sink as muchas 350 mA at room temperature, such asrelays, solenoids, dc motors, and lamps.This eight-channel source-driver IC isunnecessary if CMOS outputs suffice asthe channel-select signals. The IC

    5source

    voltage can climb to 35V if you add a sep-

    arate supply. IC5

    has internal diodes onall of the outputs to clamp inductivespikes.

    The circuit includes a switch for gen-erating a reset signal, which you can usein addition to or instead of an external re-set signal. The input can also be an ex-ternal analog signal or non-TTL, as longas you properly compensate for any dcoffset necessary to work at the switchingthresholds of the Schmitt inverter. Youcan cascade additional ripple-counterstages and add decoders and output driv-ers to select from more output channels.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    IC2, PIN 1

    IC2, PIN 9

    RST

    Q1

    Q0

    D0

    CS1

    CLKA

    CLK

    LE

    Y2

    Y1

    Y0

    A2

    A1

    A0

    Negative-going transitions increment the counter at counts 1, 2, and 3.

    F igure 2

  • 124 edn | January 4, 2001 www.ednmag.com

    ideasdesign

    The circuit in Figure 1 is a mC-based programmable timer with twooutput channels. The first channel,activated by pressing the red switch, S

    3,

    has a red LED at its output. This channelis active until it reaches its desired time-out point. The second output channelconnects to a green LED and is active af-ter a preselected time-out period. Thesecond channel remains active until thenext depression of the red switch.You candeactivate both channels at any time bypressing the green switch, S

    1. In normal

    mode, the display shows the current re-

    mainder of the desired time in seconds.The display decrements by 1 until itreaches 0. The timebase in seconds de-rives from the main oscillator of the mC,which generates a real-time interruptevery 8 msec. The mC multiplies the 8msec by 125, yielding a timebase of 1 sec.You program the desired time interval bypressing the yellow switch, S

    2; the display

    shows the programmed value. If youneed to change the programmed value,pressing the red switch decrements thevalue by 1 until it reaches 0, after whichit starts with 99. If you need to put the

    timer interval into memory, press thegreen switch, and the mC writes the value in its internal EEPROM. You can download the software for theMC68HC11E1 mC from EDNs Web site,www.ednmag.com. Click on SearchDatabases and then enter the SoftwareCenter to download the file for DesignIdea #2629.

    VCC

    VCC

    S1

    J2

    VCC

    VCC

    VCC

    VCC

    D31N4007

    S2 S3

    VCC

    IC2MC34064

    IC37805

    IC1MC68HC11E1

    INRSET

    GND

    J14321

    IN OUT

    GND

    76

    4219

    105

    764219

    105

    43

    44

    4546

    474849

    50

    52

    51

    8

    7

    17

    19

    18

    34

    33

    32

    2

    10k

    10k 10k

    10k

    1k

    10k

    10k

    10k

    10k

    10k

    10k

    10k

    10k

    10k

    10k

    1k

    1k

    1 mF1 mF

    1 mF

    10 mF 0.1 mF 0.1 mF

    10 mF2

    12

    3

    OUT2OUT1

    D2

    D1

    GREEN LED

    RED LED

    DISPLAY 2 RIGHTHP-HDSP-H103

    DISPLAY 1 LEFTHP-HDSP-H103

    3 8

    3

    1 3

    8

    27 pF 27 pF

    10M

    XTAL4.096 MHz

    GREEN

    YELLOW

    RED

    31

    30

    29

    28

    27

    42

    41

    40

    39

    38

    37

    36

    35

    9

    10

    11

    12

    13

    14

    15

    16

    21

    22

    23

    24

    25

    3

    20

    6

    4

    5

    F igure 1

    mmC provides timer functionTito Smailagich, ENIC, Belgrade, Yugoslavia

    An MC68HC11 mmC provides flexible timing functions.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

  • www.ednmag.com January 18, 2001 | edn 143

    ideasdesign

    For VCRs, TVs, and other equipmentthat requires a standby mode, youmust supply power to a mP whenother components are asleep to receiveand interpret any wake-up signal fromthe remote control or from the broad-casting company. These types ofsystems have rather low powerconsumption, and classical switch-modepower-supply ICs represent a clearoverkill for less-than-1W output levels.Any active power-supply circuit alsoneeds to be more cost- effective than thestandard structure using a metallic trans-former. The circuit in Figure 1 reducesthe cost by eliminating the use of the op-tocoupler.

    IC1

    directly drives an external 600VMOSFET. The lack of an auxiliary wind-ing greatly simplifies the overall applica-tion circuitry; the controllers integrateddynamic self supply provides V

    CC. IC

    1

    works as a peak-current PWM controller,combining fixed-frequency operation at40, 60, or 100 kHz and the skip-cyclemethod for low standby-power con-sumption. IC

    1regulates the peak current

    and allows operation over universalmains. Because the circuit operates atconstant output power, the following for-mula determines the necessary peak cur-rent:

    With an internal error amplifier that

    +

    +FB

    CS

    GND

    HV

    VCC

    DRV

    L1

    N

    4.7 mF/400V

    NCP1200P40

    2

    3

    4

    8

    6

    5

    6.8 RSENSE

    100 nF

    1:0.08 1N5819

    1N4007

    12V/1.3W

    10V AT 90 mA

    470 mF/16V

    R118k

    MTD1N60E

    IC1

    LP=2.7 mH

    NOTE: THE TRANSFORMER IS AVAILABLE FROM ELDOR ([email protected], REF 2262.0058C) AND FROM COILCRAFT ([email protected] REF Y8844-A).

    F igure 1

    10.610.410.2

    10

    9.89.69.49.2

    100 150 200 250 300INPUT VOLTAGE (V AC)

    OUTPUTVOLTAGE

    (V)

    F igure 2

    Open-loop power supply delivers as much as 1WChristophe Basso, On Semiconductor, Toulouse, Cedex, France

    IC1 regulates the peak current and allows this 1W supply to operate from universal mains.Open-loop power supply delivers as much as 1W ............................................143

    Four-way remote control uses series transmission ......................................144

    Analyze LED characteristics with PSpice ....................................................150

    Programmable-gain amplifier is low-cost ......................................................152

    PC hardware monitor reports the weather ..................................................154

    Edited by Bill Travis and Anne Watson Swager

    The input-voltage rejection stays within 1V from 130 to 260V ac.

    .FL

    P2I

    OSCP

    OUTP

    =

  • 144 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    clips at 1V maximum, RSENSE

    is equal to1/I

    P(maximum). In this example, a 40-

    kHz circuit and a 6.8V sense element de-liver as much as 1W of continuous pow-er with L

    P52.8 mH. You can recompute

    RSENSE

    for lower or higher output-powerrequirements. The 12V zener diode pre-vents the circuit from generating over-voltages. R

    1deactivates the internal short-

    circuit protection, which normally reactsupon feedback-path loss.

    Thanks to its avalanche capability, theMTD1N60E requires no clipping net-work, which further eases the design. Theefficiency measured 64% (low line,P

    OUT5866 mW) and 61% (high line,

    POUT

    51.08W). Figure 2 plots the input-voltage rejection, which stays within 1V

    from 130 to 260V-ac mains. This figureillustrates current modes inherent audiosusceptibility.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    Asimultaneous four-way remote-controlsystem adheres to size,cost, and reduced-complex-ity constraints and uses aseries transmission to driveparallel loads (Figure 1).You can use this system aslong as the time constant ofthe load is much larger thanthe total transmission timefor all data. With these con-siderations, this design candrive any object with foursimultaneous controls asmotors.

    The design uses a 9-bitdata packet. The emitterside of the designconverts 4 data bitsand a 5-bit ID code fromparallel to serial. The datapacket continuously trans-mits, and the total informa-tion arrives at the HF 433-MHz emitter. The receiver side convertsthe 9-bit serial data to parallel data. Then,the design compares the received ID codeto the local code. The comparison resultclocks the 4 data bits for the D latch. Thisconfiguration actually controls a small,battery-powered boat with two-way, re-mote-control switches. The switches aremom-off-mom types, which give front-stop-rear and left-center-right com-mands. The boat has two dc motors for

    propulsion and direction. The transmis-sion uses two 433-MHz, AM-radio mod-ules for the HF link.

    Power consumption is 10 mA duringemission, so the emitter circuit can use a9V battery (Figure 2a). D

    1protects the

    device against polarity inversion. S1

    andS

    2are three-position, mom-off-mom

    switches. Only the center, or null, posi-tion is static. The user must push theswitch in one direction and maintain it to

    keep the desired action. When released,the switch returns to its null position.With no action on S

    1and S

    2, the logic lev-

    els on data inputs D6

    to D9

    of IC1

    are lowdue to R

    3to R

    6.When an action occurs on

    S1

    or S2, the corresponding data input of

    IC1

    is close to 5V. You can activate S1

    andS

    2at same time. Voltage-divider pairs R

    1

    and R3

    or R1

    and R4

    and R2 and R

    5or R

    2

    and R6

    produce acceptable levels for IC1

    inputs.

    PARALLEL TO SERIAL 433-MHzEMISSION

    433-MHzRECEPTION

    SERIAL TO PARALLEL

    COMPARISON

    4D LATCH

    9-BIT DATA PACKET

    9-BIT DATA PACKET

    CLOCK

    CLOCK

    DATA (4 BITS)

    DATA (4 BITS)

    DATA (4 BITS)

    ID CODE (5 BITS)

    ID CODE (5 BITS)

    LOCAL ID CODE

    DATA CLOCKS AFTERTHREE IDENTICAL TRANSMISSIONS

    EMITTER

    RECEIVER

    F igure 1

    Four-way remote control uses series transmissionJM Terrade, Clermont-Ferrand, France

    The emitter converts 4 data bits and 5 ID-code bits to serial data and continuously transmits the resulting datapacket. The receiver compares the received ID code with the local code three times before clocking in new data.

  • 146 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    In the emitter circuit, two three-position switches, S1 and S2, determine the voltage on C1 (a) and the voltage levels of data bits D6 to D9 of IC1 (b).

    Diodes D2

    to D5

    permit C1

    to chargethrough R

    7. Then, Q

    1conducts, and Q

    2

    is on. D6

    acts as a power-on indicator.The voltage drop across D

    6, R

    9, and zen-

    er-diode D7

    results in a 5V supply for IC1

    and IC2. C

    1continuously charges until S

    1

    and S2

    return to the null position. Then,C

    1discharges through R

    8, and Q

    1switch-

    es off after approximately 8 to 10 sec(Figure 2b).

    Inputs A1

    to A5

    of IC1

    are three-stateinputs: low, high, and unconnected lev-

    el. Thus, 243 combinations (35) are pos-sible. However, three-state DIP switchesare expensive, and 64 possibilities areenough for many applications. If Pin 6 ofS

    3provides a low level, A

    1to A

    5can be ei-

    ther low levels or unconnected. If Pin 6of S

    3provides a high level through R

    10, A

    1

    to A5

    can be either high levels or uncon-nected. This arrangement gives 64 com-binations.

    R11

    , R12

    , and C2

    form the local oscilla-tor. The output of IC

    1at Pin 15 provides

    the 9-bit data packet to the HF emitter,IC

    2. The HF module uses amplitude

    modulation. The antenna is a 17-cm wirethat attaches directly to the pc board.When the power is on, transmission al-ways occurs. After a user releases S

    1and

    S2, the emitter continues to transmit the

    null-position information until powergoes off, which takes approximately 8 sec.

    On the receiver side (Figure 3a), theantenna is also a 17-cm wire attached di-rectly to the pc board. The incoming sig-

    + +

    REAR

    RIGHT

    LEFT

    FRONT2

    2

    MS-500

    MS-500

    R310k

    R1S1

    S3

    S2R2

    D21N4148

    D11N4148

    R710k

    R8470k

    R910k

    D6LED

    10k

    4.7k

    C110 mF

    10 mFD7

    BZX55-5V1

    D3

    VCC

    DOUT

    VCC

    VCC

    A1

    A2

    A3

    A4

    D6D7

    D8D9

    A5

    D4 D5

    R10

    R410k

    R510k

    R610k

    1N4148

    1

    2

    3

    4

    5

    1

    2

    2

    3

    3

    1

    4

    4

    5

    6

    1

    2

    3

    4

    5

    6

    12

    11

    10

    9

    8

    7

    TECTC

    RTC

    RS

    GND

    C24.7 nF

    R11100k

    R1247k

    ST2

    IN-VCC8V

    IC2TX-433-SAW

    IC1MC145026

    15

    13

    11

    100 nF

    100 nF

    GND47k

    10k

    14

    6

    7

    9

    10

    15

    11

    12

    13

    16 8

    ANTENNA

    9V BATTERY

    9V

    0V

    +

    2100 nF

    4.7k

    4.7k

    1

    3

    1

    3

    Q1UN10KM

    Q22N2907

    D6

    VC1

    S1: FRONTS2: RIGHT

    S1: FRONTS2: CENTER

    VCC

    0 0 0 01 0 1 01 0 0 00 0 0 0

    D7D8D9

    POWER IS ON. LED D6 IS ON.ALL DATA BITS TRANSMIT CONTINUOUSLY.

    '8 SEC

    5V

    5V

    2.5V

    NOACTION

    NOACTION

    TIME

    TIME

    BITS A1 TO A5=ID CODE.

    (a)

    (b)

    ON

    F igure 2

  • 148 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    nal arrives at the HF module, IC1, which

    has a stable 5V power source. The 9-bitdata packet is available at the output, orPin 14, of the module. Just as for theemitter, DIP switch S

    1provides as many

    as 64 possibilities for the ID code, and thesetting must be the same combination asthe emitter.

    The 4 data bits are available at outputsD

    6to D

    9of IC

    2. When a valid transmis-

    sion arrives at the receiver, Pin 11 of IC2

    goes high. But each time a user changesthe position of the commands on theemitter, the Valid-T signal goes low until

    the new transmission is valid. Three cor-rect transmissions are necessary. There-fore, the design needs a stable RX_OKsignal, and, for this reason D

    1, R

    1, R

    2, and

    C1

    create a time constant. The RX_OKsignal goes low only when the transmis-sion stops or when the ID code is invalid,which can happen if the emitter has nosupply and stops emitting or if anothertransmitter is in the same area (Figure3b).

    The internal D latch, IC2, clocks new

    output levels only when the circuit re-ceives a new data packet. In this way,

    when only one transmitted bit changes,the other bits keep their previous level.When the ID code is not valid or whenthe HF link is lost, which implies that thedistance between the emitter and the re-ceiver is too long, D

    6to D

    9keep their pre-

    vious levels. However, RX_OK goes lowafter 70 msec and forces D

    6to D

    9 to go

    low.

    C110 mF

    R233k

    R11k

    D11N4148

    VCC

    D9

    D8D7

    D6

    A1

    A2

    A3

    A4

    R1

    C1

    A5

    1

    2

    3

    4

    5

    1

    2

    3

    4

    5

    9

    6

    1

    2

    3

    4

    5

    6

    12

    11

    10

    9

    8

    7

    D-IN VALID-T

    R2C2

    GND

    100 nF

    10k

    6

    7

    12

    13

    14

    15

    11

    10

    16 8ANTENNA

    9V BATTERY

    +

    2100 nF

    OUT

    TEST

    VCC

    VCC

    VCC

    VCC-HF VCC-BF VCC-OUT

    IC1RF290-A5S

    IC2MC145027

    GND GND

    IN

    1 10 15

    3

    2 7 11

    13

    14

    TEST

    +47 mF+

    180k

    RX_OK

    22 nF

    47k

    D'9

    D'8

    D'7

    D'6

    78LO5ACZ

    GNDV0 VI

    100 nF

    1

    2

    3

    S1

    D6

    D7 TO D9

    RECEIVED DATA AT PIN 9 IC2

    VALID-TRANS(PIN 11 IC2)

    RX_OK

    LOGIC LEVEL FORAND GATES

    D'6

    D'7 TO D'9

    LOW LEVEL FORCE D'6 TO D'9 LOW

    TIME

    TIME

    TIME

    TIME

    TIME

    TIME

    TIME

    TIME

    '70 mSEC

    '2.5V

    THREE IDENTICAL DATAPACKETS'45 mSEC

    KEEP EMISSION ALIVEFOR '8 SEC

    9-BIT DATA PACKET

    HIGH INPUT LEVEL: DATA IS ENABLED

    (a)

    (b)

    ON

    F igure 3

    In the receiver (a), three correct transmissions must occur before Pin 11 of IC2 goes high (b).

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

  • 150 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    Recent advances in LED technol-ogy have lead to LEDs widespreaduse in outdoor-signal applications,such as in traffic and railroad signals. Atypical LED signal consists of an LED ar-ray and a power supply. When a low-volt-age power supply is either desirable ormandatory, series/parallel combinationsof LEDs become inevitable. However, an-alyzing and optimizing series/parallelcombinations of LEDs with varying for-ward characteristics can be complicated.Using the parametric and Monte Carlocapabilities of PSpice greatly simplifiesthis task.

    To model an LED in PSpice, use thediode model.You can set the IFK and ISRparameters in the diode model to zero;Figure 1 shows the resultant PSpice diodeforward-current model and correspon-ding equations. As the equations in thefigure show, you can express the forwardvoltage across the diode model, or V

    FWD,

    as the sum of the voltage across the se-ries resistance and the voltageacross the intrinsic diode.

    The dominant term in the VFWD

    equa-tion of Figure 1, assuming R

    Sis less than

    10V, is the logarithmic term. Therefore,if you vary the model parameter N inMonte Carlo or parametric analyses, thenthe V

    FWDvaries accordingly. A helpful

    hint: When creating an LED model usingprograms such as Parts (www.mi-crosim.com), use curve-tracer plots or anenlarged photocopy of the VI curve fromdata books to extrapolate data pointsalong the VI curve.

    Figure 2 shows an example for whichN varies linearly between 2.07 and 2.53,or 2.3610%. The forward voltage at 20mA varies from 1.59 to 1.94V, or1.76569.9%. By editing theN52.3299 statement in the LED mod-el to N52.3299 DEV 10% assigns a10% device tolerance to the LED model.Therefore, when you execute a Monte

    Carlo analysis, the forwardcharacteristics ofeach LED in the cir-cuit vary randomly. Figure3s example performs 20Monte Carlo sweeps at1V/sec, with N set for a10% tolerance.

    The final example is theanalysis of a simple circuit(Figure 4a). The inputconsisted of a 60-mA

    RS

    VD VFWD

    +

    +

    2

    2

    IFWD=ISz(eVD/NzVT21).

    VFWD=IFWDzRS+NzVTzln +1 .

    VD=NzVTzln +1 . IS

    IFWD

    IS

    IFWD

    F igure 1

    F igure 2

    F igure 3

    Analyze LED characteristics with PSpiceSam Mollet, GE Harris Harmon Railway Technology, Grain Valley, MO

    This simple model and equations are the result of settingPSpices diode-model parameters IFK and ISR to zero.

    This simulation run varies N linearly from 2.07 to 2.53.

    Assigning a 10% tolerance to N causes the forward characteristics of each LED in the circuit to varyrandomly during Monte Carlo analysis.

  • 152 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    pulse, and the simulations determine thepeak current through D

    1for 0, 10, and

    100V resistance values. The model state-ment assigned a 10% tolerance to N, andthe example executes 50 Monte Carlo

    runs. The results for R50 reveal a largestandard deviation of 10 mA. The resultsfor R510 reveals a smaller standard de-viation of about 5 mA (Figure 4b). Theresults for R5100 reveals a small stan-

    dard deviation of only 1 mA.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    F igure 4

    To analyze a simple circuit (a), simulations determine the peak current through D1 for three resistance values. The results for R5510V reveal a stan-dard deviation of approximately 5 mA (b).

    Numerous programmable-gain amplifiers are avail-able, but a simple solutionprovides the option of using 256gain steps with an 8-bit DACand higher steps with higher bitDACs (Figure 1). According tothe inverting-amplifier configu-ration of an op amp, theoutput voltage isV

    OUT5V

    IN(R

    F/R

    IN), where R

    Fis

    the feedback resistance, RIN

    isthe input resistance, and V

    INis

    the input voltage of the amplifi-er circuit. Generally, by chang-ing the feedback resistance, youcan get the desired gain.

    In this design, the 8-bit DAC in the in-put stage acts as a programmable atten-uator for the input signal and permits amaximum full-scale I

    OUT1of 1 mA. The

    value of IOUT1

    is proportional to the in-

    put-voltage signal. The shunt feedbackresistance, R

    F, converts I

    OUT1to a voltage.

    Thus, the input signal, VIN

    , acts as a ref-erence input to the DAC. Instead of in-creasing the value of the feedback resis-tor for higher gain, this circuit uses the

    DAC in series with the op amp to atten-uate the input signal and achieve the de-sired variable-gain factor. You calculatethe current output, I

    OUT1, from the DAC

    as follows, where D0

    through D7

    are thedigital inputs to the DAC:

    For example, if all of the bits are ones,the 8-bit digital image is FF, and the cor-responding amplifier full-scale output is:

    In an actual application, keep the val-ue of R

    Ffixed for the maximum gain. By

    varying the digital image pattern from 00to FF, you can get the variable amplifiergain according to your requirements.

    _

    +

    8-BIT DACAD 7524

    8-BIT DATA

    VOUT

    RF

    LF356

    GND

    1OUT2

    1OUT1

    RFB

    5V

    VINRIN

    IREF

    F igure 1

    Programmable-gain amplifier is low-costJ Jayapandian, Indira Gandhi Centre for Atomic Research, Kalpakkam, India

    A DAC in series with an op amp attenuates the input sig-nal to achieve the variable-gain factor.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    R1{R}

    R2{R}

    R3{R}

    D1LEDREDD2LEDRED

    D5LEDRED

    D8LEDRED

    D4LEDRED

    D7LEDRED

    2

    +

    LED

    I160m

    (a) (b)

    .256

    D

    128

    D

    64

    D

    32

    D

    16

    D

    8

    D

    4

    D

    2

    D

    R

    VI 76543210

    IN

    IN1OUT

    +++++++=

    .R256

    255

    R

    VRIV F

    IN

    INF1OUTOUT

    ==

  • 154 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    You usually use PC hardware mon-itors to keep a close eye on power-supply voltage levels, the speed ofsystem cooling fans, and even the tem-perature of the CPU. Until fairly recent-ly, this level of system monitoring was re-served for high-end servers runningmission-critical applications. However,now that low-cost hardware monitoringASICs are available, advanced hardwaremonitoring has become a standard fea-ture in most new PCs. And hardwaremonitors are now finding their way intodiverse applications, such as weather sta-tions (Figure 1).

    IC1

    has two external temperature-measurement channels. One channelconnects to a resistive humidity sensor,and a second channel uses a 2N3906transistor to sense the outdoor tempera-ture. The internal temperature sensormeasures the indoor temperature. One ofthe tachometer inputs connects to theoutput of a wind-speed meter. For each

    of the measurement inputs, you can setlimits that warn the user of changingweather conditions. IC

    1uses a switching-

    current-measurement scheme, so youcan mount the sensors hundreds of feetfrom the IC and still maintain a highSNR.

    IC1

    connects to a parallel printer portusing a 74HC07 open-drain noninvert-ing buffer. Pin 2 of the parallel port is theserial clock. Pin 3 writes configurationdata into IC

    1, and Pin 13 reads data from

    IC1.

    The necessary software is simple, andthe parallel-printer port is easily accessi-ble using freeware drivers and DLLs thatyou can find on the Internet.You can bit-bang the SCL and SDATA lines using aprogramming language such as VisualBasic or Visual C++.

    The temperature-measurement chan-nels use a thermal diode, such as that onIntels Pentium processors (PII1), or adiscrete npn or pnp transistor. These

    channels use a two-wire scheme that sup-plies switching current levels to the tran-sistor. IC

    1measures the difference in V

    BE

    between these two currents and calculatesthe temperature according to the follow-ing well-known relationship:

    DVBE

    5KT/q x ln(N),

    where K is Boltzmanns constant, q is thecharge of an electron, T is the absolutetemperature in Kelvin, and N is the ratioof the two currents.

    You can also use the CPU temperature-monitoring channels to measure changesin resistance, making them useful formost resistive sensors, including photodiodes, photo resistors, gas sensors, andresistive-humidity sensors.

    WIND SPEED

    FREQUENCYOUTPUT

    PARALLEL-PRINTER PORT(36-PIN CENTRONICS)

    +

    74HC07

    5V

    10 mF 0.1 mF

    18

    17

    14

    13

    TEMPERATURE

    STANDARDPNPTRANSISTOR

    D+

    D2

    HUMIDITY

    RESISTIVE-HUMIDITY

    SENSOR

    HUMIDITY-CALIBRATION

    TRIM POT

    SDA

    SCL

    FAN1

    SERIALBUS

    3

    4

    5

    8

    9

    12

    5VNTEST_IN/AOUT

    VCC

    VCC

    IC1ADM1024

    10k

    13

    3

    2

    GNDD

    F igure 1

    PC hardware monitor reports the weatherSean Gilmour, Analog Devices, Limerick Ireland

    A PC hardware-monitor IC can also monitor weather-station characteristics.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

  • 156 edn | January 18, 2001 www.ednmag.com

    Design Idea Entry Blank

    ideasdesign

    Entry blank must accompany all entries. $100 Cash Award for allpublished Design Ideas. An additional $100 Cash Award for thewinning design of each issue, determined by vote of readers.Additional $1500 Cash Award for annual Grand Prize Design,selected among biweekly winners by vote of editors.

    To: Design Ideas Editor, EDN Magazine275 Washington St, Newton, MA 02458

    I hereby submit my Design Ideas entry. (Please print clearly)

    Name

    Title

    Phone

    E-mail Fax

    Company

    Address

    Country ZIP

    Design Idea Title

    Entry blank must accompany all entries. (A separate entryblank for each author must accompany every entry.)Design entered must be submitted exclusively to EDN,must not be patented, and must have no patent pending.Design must be original with author(s), must not havebeen previously published (limited-distribution houseorgans excepted), and must have been constructed andtested. Fully annotate all circuit diagrams. Please submittext, software listings and all other computer-readable doc-umentation on IBM PC disk or in plain ASCII by e-mail [email protected].

    Exclusive publishing rights remain with CahnersBusiness Information unless entry is returned to author, oreditor gives written permission for publication elsewhere.The author must be willing to sign and return our publica-tion agreement if the Design Idea is accepted for publica-tion and must complete a W-9 tax form (W-8 for non-USresidents) before payment can be processed.

    Signed

    Date

    Your vote determines this issues winner. Vote now atwww.ednmag.com/ednmag/vote.asp.

  • www.ednmag.com January 18, 2001 | edn 143

    ideasdesign

    For VCRs, TVs, and other equipmentthat requires a standby mode, youmust supply power to a mP whenother components are asleep to receiveand interpret any wake-up signal fromthe remote control or from the broad-casting company. These types ofsystems have rather low powerconsumption, and classical switch-modepower-supply ICs represent a clearoverkill for less-than-1W output levels.Any active power-supply circuit alsoneeds to be more cost- effective than thestandard structure using a metallic trans-former. The circuit in Figure 1 reducesthe cost by eliminating the use of the op-tocoupler.

    IC1

    directly drives an external 600VMOSFET. The lack of an auxiliary wind-ing greatly simplifies the overall applica-tion circuitry; the controllers integrateddynamic self supply provides V

    CC. IC

    1

    works as a peak-current PWM controller,combining fixed-frequency operation at40, 60, or 100 kHz and the skip-cyclemethod for low standby-power con-sumption. IC

    1regulates the peak current

    and allows operation over universalmains. Because the circuit operates atconstant output power, the following for-mula determines the necessary peak cur-rent:

    With an internal error amplifier that

    +

    +FB

    CS

    GND

    HV

    VCC

    DRV

    L1

    N

    4.7 mF/400V

    NCP1200P40

    2

    3

    4

    8

    6

    5

    6.8 RSENSE

    100 nF

    1:0.08 1N5819

    1N4007

    12V/1.3W

    10V AT 90 mA

    470 mF/16V

    R118k

    MTD1N60E

    IC1

    LP=2.7 mH

    NOTE: THE TRANSFORMER IS AVAILABLE FROM ELDOR ([email protected], REF 2262.0058C) AND FROM COILCRAFT ([email protected] REF Y8844-A).

    F igure 1

    10.610.410.2

    10

    9.89.69.49.2

    100 150 200 250 300INPUT VOLTAGE (V AC)

    OUTPUTVOLTAGE

    (V)

    F igure 2

    Open-loop power supply delivers as much as 1WChristophe Basso, On Semiconductor, Toulouse, Cedex, France

    IC1 regulates the peak current and allows this 1W supply to operate from universal mains.Open-loop power supply delivers as much as 1W ............................................143

    Four-way remote control uses series transmission ......................................144

    Analyze LED characteristics with PSpice ....................................................150

    Programmable-gain amplifier is low-cost ......................................................152

    PC hardware monitor reports the weather ..................................................154

    Edited by Bill Travis and Anne Watson Swager

    The input-voltage rejection stays within 1V from 130 to 260V ac.

    .FL

    P2I

    OSCP

    OUTP

    =

  • 144 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    clips at 1V maximum, RSENSE

    is equal to1/I

    P(maximum). In this example, a 40-

    kHz circuit and a 6.8V sense element de-liver as much as 1W of continuous pow-er with L

    P52.8 mH. You can recompute

    RSENSE

    for lower or higher output-powerrequirements. The 12V zener diode pre-vents the circuit from generating over-voltages. R

    1deactivates the internal short-

    circuit protection, which normally reactsupon feedback-path loss.

    Thanks to its avalanche capability, theMTD1N60E requires no clipping net-work, which further eases the design. Theefficiency measured 64% (low line,P

    OUT5866 mW) and 61% (high line,

    POUT

    51.08W). Figure 2 plots the input-voltage rejection, which stays within 1V

    from 130 to 260V-ac mains. This figureillustrates current modes inherent audiosusceptibility.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    Asimultaneous four-way remote-controlsystem adheres to size,cost, and reduced-complex-ity constraints and uses aseries transmission to driveparallel loads (Figure 1).You can use this system aslong as the time constant ofthe load is much larger thanthe total transmission timefor all data. With these con-siderations, this design candrive any object with foursimultaneous controls asmotors.

    The design uses a 9-bitdata packet. The emitterside of the designconverts 4 data bitsand a 5-bit ID code fromparallel to serial. The datapacket continuously trans-mits, and the total informa-tion arrives at the HF 433-MHz emitter. The receiver side convertsthe 9-bit serial data to parallel data. Then,the design compares the received ID codeto the local code. The comparison resultclocks the 4 data bits for the D latch. Thisconfiguration actually controls a small,battery-powered boat with two-way, re-mote-control switches. The switches aremom-off-mom types, which give front-stop-rear and left-center-right com-mands. The boat has two dc motors for

    propulsion and direction. The transmis-sion uses two 433-MHz, AM-radio mod-ules for the HF link.

    Power consumption is 10 mA duringemission, so the emitter circuit can use a9V battery (Figure 2a). D

    1protects the

    device against polarity inversion. S1

    andS

    2are three-position, mom-off-mom

    switches. Only the center, or null, posi-tion is static. The user must push theswitch in one direction and maintain it to

    keep the desired action. When released,the switch returns to its null position.With no action on S

    1and S

    2, the logic lev-

    els on data inputs D6

    to D9

    of IC1

    are lowdue to R

    3to R

    6.When an action occurs on

    S1

    or S2, the corresponding data input of

    IC1

    is close to 5V. You can activate S1

    andS

    2at same time. Voltage-divider pairs R

    1

    and R3

    or R1

    and R4

    and R2 and R

    5or R

    2

    and R6

    produce acceptable levels for IC1

    inputs.

    PARALLEL TO SERIAL 433-MHzEMISSION

    433-MHzRECEPTION

    SERIAL TO PARALLEL

    COMPARISON

    4D LATCH

    9-BIT DATA PACKET

    9-BIT DATA PACKET

    CLOCK

    CLOCK

    DATA (4 BITS)

    DATA (4 BITS)

    DATA (4 BITS)

    ID CODE (5 BITS)

    ID CODE (5 BITS)

    LOCAL ID CODE

    DATA CLOCKS AFTERTHREE IDENTICAL TRANSMISSIONS

    EMITTER

    RECEIVER

    F igure 1

    Four-way remote control uses series transmissionJM Terrade, Clermont-Ferrand, France

    The emitter converts 4 data bits and 5 ID-code bits to serial data and continuously transmits the resulting datapacket. The receiver compares the received ID code with the local code three times before clocking in new data.

  • 146 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    In the emitter circuit, two three-position switches, S1 and S2, determine the voltage on C1 (a) and the voltage levels of data bits D6 to D9 of IC1 (b).

    Diodes D2

    to D5

    permit C1

    to chargethrough R

    7. Then, Q

    1conducts, and Q

    2

    is on. D6

    acts as a power-on indicator.The voltage drop across D

    6, R

    9, and zen-

    er-diode D7

    results in a 5V supply for IC1

    and IC2. C

    1continuously charges until S

    1

    and S2

    return to the null position. Then,C

    1discharges through R

    8, and Q

    1switch-

    es off after approximately 8 to 10 sec(Figure 2b).

    Inputs A1

    to A5

    of IC1

    are three-stateinputs: low, high, and unconnected lev-

    el. Thus, 243 combinations (35) are pos-sible. However, three-state DIP switchesare expensive, and 64 possibilities areenough for many applications. If Pin 6 ofS

    3provides a low level, A

    1to A

    5can be ei-

    ther low levels or unconnected. If Pin 6of S

    3provides a high level through R

    10, A

    1

    to A5

    can be either high levels or uncon-nected. This arrangement gives 64 com-binations.

    R11

    , R12

    , and C2

    form the local oscilla-tor. The output of IC

    1at Pin 15 provides

    the 9-bit data packet to the HF emitter,IC

    2. The HF module uses amplitude

    modulation. The antenna is a 17-cm wirethat attaches directly to the pc board.When the power is on, transmission al-ways occurs. After a user releases S

    1and

    S2, the emitter continues to transmit the

    null-position information until powergoes off, which takes approximately 8 sec.

    On the receiver side (Figure 3a), theantenna is also a 17-cm wire attached di-rectly to the pc board. The incoming sig-

    + +

    REAR

    RIGHT

    LEFT

    FRONT2

    2

    MS-500

    MS-500

    R310k

    R1S1

    S3

    S2R2

    D21N4148

    D11N4148

    R710k

    R8470k

    R910k

    D6LED

    10k

    4.7k

    C110 mF

    10 mFD7

    BZX55-5V1

    D3

    VCC

    DOUT

    VCC

    VCC

    A1

    A2

    A3

    A4

    D6D7

    D8D9

    A5

    D4 D5

    R10

    R410k

    R510k

    R610k

    1N4148

    1

    2

    3

    4

    5

    1

    2

    2

    3

    3

    1

    4

    4

    5

    6

    1

    2

    3

    4

    5

    6

    12

    11

    10

    9

    8

    7

    TECTC

    RTC

    RS

    GND

    C24.7 nF

    R11100k

    R1247k

    ST2

    IN-VCC8V

    IC2TX-433-SAW

    IC1MC145026

    15

    13

    11

    100 nF

    100 nF

    GND47k

    10k

    14

    6

    7

    9

    10

    15

    11

    12

    13

    16 8

    ANTENNA

    9V BATTERY

    9V

    0V

    +

    2100 nF

    4.7k

    4.7k

    1

    3

    1

    3

    Q1UN10KM

    Q22N2907

    D6

    VC1

    S1: FRONTS2: RIGHT

    S1: FRONTS2: CENTER

    VCC

    0 0 0 01 0 1 01 0 0 00 0 0 0

    D7D8D9

    POWER IS ON. LED D6 IS ON.ALL DATA BITS TRANSMIT CONTINUOUSLY.

    '8 SEC

    5V

    5V

    2.5V

    NOACTION

    NOACTION

    TIME

    TIME

    BITS A1 TO A5=ID CODE.

    (a)

    (b)

    ON

    F igure 2

  • 148 edn | January 18, 2001 www.ednmag.com

    ideasdesign

    nal arrives at the HF module, IC1, which

    has a stable 5V power source. The 9-bitdata packet is available at the output, orPin 14, of the module. Just as for theemitter, DIP switch S

    1provides as many

    as 64 possibilities for the ID code, and thesetting must be the same combination asthe emitter.

    The 4 data bits are available at outputsD

    6to D

    9of IC

    2. When a valid transmis-

    sion arrives at the receiver, Pin 11 of IC2

    goes high. But each time a user changesthe position of the commands on theemitter, the Valid-T signal goes low until

    the new transmission is valid. Three cor-rect transmissions are necessary. There-fore, the design needs a stable RX_OKsignal, and, for this reason D

    1, R

    1, R

    2, and

    C1

    create a time constant. The RX_OKsignal goes low only when the transmis-sion stops or when the ID code is invalid,which can happen if the emitter has nosupply and stops emitting or if anothertransmitter is in the same area (Figure3b).

    The internal D latch, IC2, clocks new

    output levels only when the circuit re-ceives a new data packet. In this way,

    when only one transmitted bit changes,the other bits keep their previous level.When the ID code is not valid or whenthe HF link is lost, which implies that thedistance between the emitter and the re-ceiver is too long, D

    6to D

    9keep their pre-

    vious levels. However, RX_OK goes lowafter 70 msec and forces D

    6to D

    9 to go

    low.

    C110 mF

    R233k

    R11k

    D11N4148

    VCC

    D9

    D8D7

    D6

    A1

    A2

    A3

    A4

    R1

    C1

    A5

    1

    2

    3

    4

    5

    1

    2

    3

    4

    5

    9

    6

    1

    2

    3

    4

    5

    6

    12

    11

    10

    9

    8

    7

    D-IN VALID-T

    R2C2

    GND

    100 nF

    10k

    6

    7

    12

    13

    14

    15

    11

    10

    16 8ANTENNA

    9V BATTERY

    +

    2100 nF

    OUT

    TEST

    VCC

    VCC

    VCC

    VCC-HF VCC-BF VCC-OUT

    IC1RF290-A5S

    IC2MC145027

    GND GND

    IN

    1 10 15

    3

    2 7 11

    13

    14

    TEST

    +47 mF+

    180k

    RX_OK

    22 nF

    47k

    D'9

    D'8

    D'7

    D'6

    78LO5ACZ

    GNDV0 VI

    100 nF

    1

    2

    3

    S1

    D6

    D7 TO D9

    RECEIVED DATA AT PIN 9 IC2

    VALID-TRANS(PIN 11 IC2)

    RX_OK

    LOGIC LEVEL FORAND GATES

    D'6

    D'7 TO D'9

    LOW LEVEL FORCE D'6 TO D'9 LOW

    TIME

    TIME

    TIME

    TIME

    TIME

    TIME

    TIME

    TIME

    '70 mSEC

    '2.5V

    THREE IDENTICAL DATAPACKETS'45 mSEC

    KEEP EMISSION ALIVEFOR '8 SEC

    9-BIT DATA PACKET

    HIGH INPUT LEVEL: DATA IS ENABLED

    (a)

    (b)

    ON

    F igure 3

    In the receiver (a), three correct transmissions must occur before Pin 11 of IC2 goes high (b).

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

  • When you design a transformer forany power converter, youface several compromises.You must trade off core size against thenumber of primary turns and flux den-sity. Another trade-off is the number ofturns and winding resistance versus theassociated losses. After making thesetrade-offs, you usually arrive at a goodcompromise that involves the primaryand secondary turns. However, if the con-verter has more than one output, you facea new set of compromises. For high-power, low-output-voltage converters,the number of secondary turns is oftenvery low. In a forward-converter topolo-gy, it is common for a 3.3V transformerto have one turn in its main secondarywinding. This one-turn configuration isideal for lowering winding resistance andassociated power losses. For this design,the average output voltage is 3.3V perturn. So, if you need another output fromthe converter, that output is a multiple of3.3V. For a multiple-output power con-verter, the ratio between the output volt-

    ages is often not a whole number (a prob-lem known as turns granularity). Re-ferring to this example, if the main out-put is 3.3V and the desired auxiliaryoutput is 5V, two secondary turns yield6.6Va 32% error. A linear regulatorcould drop 6.6 to 5V but with the penal-ty of a power loss. Figure 1 shows an ap-proach to solving the granularity prob-lem if the regulation requirement is notparticularly tight (5 to 15%).

    Transformer T1

    is a normal forwardtransformer. Each secondary winding hasone turn. The control loop regulates themain output, V

    OUT1, to 3.3V. The objec-

    tive is for the auxiliary output to be 5.5V.With only one secondary turn, that out-put will also be 3.3V. Consequently, youneed a simple way to increase the voltage.You can add another transformer, T

    2,

    dubbed a delta transformer, to the sec-ondaries (Figure 1). The primary of the

    delta transformer is parallel with theV

    OUT1winding, and the secondary of the

    delta transformer is in series with theV

    OUT2winding. This connection has the

    effect of adding a portion of the mainoutput voltage, V

    OUT1, to the auxiliary

    output, VOUT2

    . (The turns ratio deter-mines the portion.) In the exampleabove, suppose that the main trans-former operates at a 50% duty cycle, andassume that the rectifiers have 0.6V for-ward voltage drop. Then, the equation re-lating V

    OUT1and the transformer second-

    ary voltage, VT1

    , during the on time is:3.35(V

    T120.6)(0.5)2(0.6)(0.5). Thus,

    VT1

    57.8V.Now, you need to solve for the desired

    total VT

    (VT2

    ) of the slave output, VOUT2

    :55(V

    T220.6)(0.5)2(0.6)(0.5). Thus,

    VT2

    511.2V. VT2

    is the sum of the main-transformer secondary voltage and thedelta-transformer secondary voltage. The

    www.ednmag.com February 1, 2001 | edn 121

    ideasdesign

    Method sets voltage in multiple-output converters ........................................121

    Circuit forms constant-current SCR..........122

    555 makes handy voltage-to-time converter ........................................................124

    Program predicts VSWR-mismatch RF uncertainties............................................124

    PC monitors two-way RS-232 transmission ..................................................126

    Passive filters fill the bill at audio frequencies ........................................128

    Watchdog timer assumes varied roles....................................................130

    One microcontroller serves multiple external interrupts ......................132

    Edited by Bill Travis and Anne Watson Swager

    VOUT2

    MBR2030CTL

    10T

    T2T1 1T

    VOUT1

    MBR2030CTL

    1T

    6T 5T

    23T

    CONTROLLERMC33023

    FEEDBACK

    MURS120T3

    MTP20N20E

    VBUS

    MAIN TRANSFORMER DELTA TRANSFORMER

    F igure 1

    Method sets voltage in multiple-output convertersRobert Bell, On Semiconductor, Phoenix, AZ

    A delta transformer eliminates the problem of turns-ratio granularity.

  • 122 edn | February 1, 2001 www.ednmag.com

    ideasdesign

    desired delta-transformer secondaryvoltage is 11.227.853.4V. Because theprimary voltage of the delta transformeris also 7.8V, the turns ratio of the deltatransformer must be 7.8/3.452.3. In thisexample, you can use 10 and 23 turns forthe delta transformer. The main-trans-former secondary output delivers currentonly during its on time, and an internal

    resistive-voltage drop exists in the sec-ondary output. Therefore, the volt-timeproduct of the main transformers sec-ondary output is not exactly zero, whichis a required condition for the deltatransformers primary to reset. So, youshould make the primary winding of thedelta transformer resistive to add a smallvoltage drop in the forward direction or

    use a small core gap. You can use this ap-proach in all buck regulators to fine-tunean auxiliary output.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

    Atypical SCR (silicon-controlledrectifier) requires a triggercurrent, which causes theSCR structure to latch on. Once the de-vice latches, the current through the SCRis solely a function of external compo-nent values. The SCR has no inherentability to limit the current flow once itlatches on. Current continues to flow, aslong as the current exceeds a minimal val-ue known as the holding current. The cir-cuit in Figure 1 is similar to an SCR, be-cause it also requires a trigger current tolatch into its on state. However, oncelatched, the circuit conducts a constantcurrent. The constant current continuesto flow, as long as the external circuitrycan provide it, and the minimum com-pliance voltage of the SCR circuit is sat-isfied. When these conditions are nolonger valid, the circuit latches off. Thecircuit in Figure 1 provides a constant-current pulse to drive an LED with cur-rent sourced from a capacitor. You trig-ger the circuit with a narrow,negative-going pulse. The pulse, coupledthrough R

    1and D

    2, turns Q

    3on. Q

    3pro-

    vides base drive to Q1. As Q

    1turns on,

    current begins to flow through the LEDand current-sense resistor R

    2.

    When 0.6V develops across R2, the cur-

    rent-limiting transistor, Q2, begins to

    turn on and shunt base current from Q1,

    through diode D1. Q

    2thus maintains the

    current through R2

    at a constant level(~0.6V/R

    2) by controlling the base cur-

    rent to Q1. At the same time, because the

    collector voltage of Q2must be one diode

    drop lower than the base voltage of Q1

    while in constant-current mode, Q2

    alsodraws current through R

    3. Q

    2thus main-

    tains Q3

    in the on state (providing basecurrent to Q

    1), even after the trigger pulse

    disappears. The circuit maintains theconstant-current mode, with Q

    1drawing

    a constant current through the LED, thestorage capacitor C

    1, and R

    2until Q

    1can

    no longer sustain the constant current.This situation occurs when the voltageacross C

    1drops low enough to be unable

    to maintain 0.6V across R2. Then, Q

    2be-

    gins to turn off, which allows Q3

    to turnoff, thereby depriving Q

    1of base current.

    Q1

    turns off, which results in a constant-current (flat-topped) pulse through theLED with sharply rising and falling edges.

    By choosing the proper values of R2

    andC

    1, you can easily control pulse width and

    amplitude.An apt application for this circuit is

    constant-current battery charging. Onceyou trigger the circuit, it provides con-stant current to charge a battery. Whenthe battery charges to a point where thecharging current falls below the constant-current level, the circuit latches off. Notethat the circuit does not provide a con-tinuous trickle charge, which could over-charge some batteries.

    5V

    LED

    C11000 mF

    16V

    R230

    1k

    10k

    100

    1k

    1k

    R31k

    R11k

    Q12N3904

    Q32N3906

    Q22N3904

    +

    1

    1N4148D2

    1N41485V

    0V

    CCOMP0.01 mF

    TRIGGERPULSE

    D1

    F igure 1

    Circuit forms constant-current SCRRobert Buono, Ringwood, NJ

    Resembling an SCR, this circuit provides a constant current of controlled pulse width and amplitudeto a load.

    Is this the best Design Idea in this issue? Vote at www.ednmag.com/ednmag/vote.asp.

  • 124 edn | February 1, 2001 www.ednmag.com

    ideasdesign

    Hewlett-Packard (now Agi-lent Technologies) once of-fered a useful little cardboardslide rule for calculating the uncer-tainty in RF measurements stem-ming from VSWR (voltage-stand-ing-wave-ratio) mismatch. Unfor-tunately, this handy device is nolonger available. A Visual Basic pro-gram accomplishes the same func-tion on a PC, however. You candownload the executable programand its associated setup utilities ona blind page at www.sonic.net/~shageman/vswr.html. Mismatchuncertainty is one of the most commoncalculations an RF engineer makes whendetermining the uncertainty of RF pow-er measurements. The source and loadVSWR interact along an unknown lengthof line to produce some uncertainty inthe power measurement. This uncertain-

    ty stems from the fact that, at high fre-quencies, the length of a transmissionline connecting a source and load may besufficient to transform the impedance atone end of the line to another value at theother end.

    System specifications usually include

    the VSWR values, which lack phaseinformation. So, one certaintyabout a measurement is that it liesbetween some range of values. Inreality, even the connectors and thetransmission line in the measure-ment path add uncertainty becausetheir true electrical length and,hence, phase is unknown. So, thetrue power at the load may be high-er or lower than the measured val-ue. The conservative way to accountfor this error is to assume that thephase is unknown and assume theworst case: The incident and re-

    flected signals interact in the worst pos-sible wayin other words, at the peaksand valleys. You express this scenario asVSWR5E

    MAX/E

    MIN, where E

    MAXand E

    MIN

    are the maximum and minimum voltagesalong the line. VSWR is a common spec-ification in data sheets for RF devices,

    Program predicts VSWR-mismatch RF uncertaintiesSteve Hageman, Agilent Technologies, Santa Rosa, CA

    Given the source and load VSWRs,the VSWR Calc program quickly cal-

    culates RF measurement uncertainties.

    F igure 1

    The circuit in Figure 1 is asimple, low-cost volt-age-to-time converterusing the ubiquitous 555 timerchip.You can use the ICs mono-stable multivibrator as a voltage-to-time converter by connectingthe analog-voltage input to thecharging resistor, R, instead ofconnecting R to V

    CC. With this

    modification, the timer chipsoutput-timing cycle, t

    P, is pro-

    portional to the input voltage,V

    IN. When you apply an input

    voltage, the voltage across capac-itor C charges exponentially ac-cording to the formula V

    C=

    VIN

    (12et/RC), where RC is the

    time constant of the circuit, withC in farads and R in ohms. Dur-ing one time constant, the voltageacross the capacitor changes byapproximately 63% of V

    IN. The

    output timing of the monostablemultivibrator is t

    P51.1 RC. By

    keeping RC constant with fixed Rand C values and varying the in-put voltage, V

    IN, you obtain vari-

    able output timing. The outputpulse width in this circuit is in-versely proportional to the inputvoltage.

    NE 555

    TRIGGER

    tP

    3

    2 7

    6

    5

    4 8

    OUTPUT

    0.01 mF

    C

    RVIN

    VCCF igure 1

    555 makes handy voltage-to-time converterJ Jayapandian, IGCAR, Tamil Nadu, India

    A voltage-controlled monostable multivibrator makes a handyvoltage-to-time converter.

    Is this the best Design Idea inthis issue? Vote at www.ednmag.com/ednmag/vote.asp.

  • 126 edn | February 1, 2001 www.ednmag.com

    ideasdesign

    The goal of monitoring trans-mission in a data linkis obvious: You want

    to know the contents of the data, whenit was sent, and by whom. If one of thecommunicating parties is a PC or an-other user-programmable controller,then you can modify parameter settingsor, at worst, change transmission rou-tines to generate log files or perform oth-er actions. This approach, however, maybe inconvenient or impossible to applyin some cases. As an alternative ap-proach, you can use a PC with two seri-al ports and a monitor program to ob-serve the link itself. The method inFigure 1a needs no access or knowledgeof the communicating devices. A C pro-gram opens two COM ports and installsinterrupt-service routines for IRQ4 andIRQ3. Upon the reception of an inter-rupt, the routine stores a byte in a com-mon circular buffer with the COM iden-tifier and error flags. The main programdisplays the contents of the buffer, indi-cating time intervals in milliseconds be-tween consecutive transfers. Although

    the program simplifies the time meas-urement, it preserves the original byte or-der and correctly reflects time relation-ships as long as the main program keepsup with transmission speed. If you needgreater precision, you can easily modifythe program to record time stamps,

    along with the data and status bytes, inthe circular buffer.

    Unfortunately, not all PCs offer twoCOM ports. This deficiency is a commondrawback of notebook computers, whichuse a second UART controller for IrDAcommunication. But you can use even

    162738495

    162738495

    162738495

    A TO B B TO A GND A TO B B TO A GNDCOM1

    COM2

    RxD

    RxD

    GND

    1N4148

    1N4148 RxD

    RI

    GNDC0Mx

    (a) (b)

    F igure 1

    PC monitors two-way RS-232 transmissionJerzy Chrzaszcz, Warsaw University of Technology, Poland

    You can eavesdrop on RS-232 transmissions by using two COM ports (a); a simple modification (b)adapts the method to PCs with only one COM port.

    such as amplifiers, sources, and powermeters.VSWR relates to the absolute val-ue of the reflection coefficient g in the ex-pression

    and, in turn g relates to the return lossin decibels in the expressionR

    L5220log

    10g. Because the source and

    load each have a VSWR, the product ofthe two gives the maximum VSWR:VSWR

    MAX5VSWR

    1VSWR

    2. The two

    VSWRs produce a combined return loss,as follows:

    The uncertainty in the total measure-ment stemming from the source and loadVSWRs is Uncertainty(1)520log

    10

    (11g1g

    2) dB, and Uncertainty(2)5

    20log10

    (12g1g

    2) dB.

    As a result, you have a range of eitherplus or minus uncertainty. At smallVSWRs, the plus and minus converge tothe same value. At higher VSWRs, theplus and minus uncertainties diverge, soyou need to calculate both. As an exam-ple, consider a Hewlett-Packard ESG-3000 microwave source operating at 900MHz. Its VSWR is specified at 1.4 to 1.Then, assume that you measure thesources output power with a Hewlett-Packard E4412A power sensor that has aspecified VSWR of 1.15 to 1. If you in-put these figures into the VSWR Calcprogram, you obtain the screen shown inFigure 1. The Copy to Clipboard func-

    tion transfers the VSWRs and the calcu-lated data to the Windows clipboard sothat documenting the calculations is easyin any Windows application. (The card-board slide rule cannot perform thisfunction.) Figure 1 shows the clipboarddata of this example. The uncertainty inthe example is 10.100 to 20.102 dB.Youshould know the measurement uncer-tainty, because it is relatively easy to ob-tain totally uncertain measurements athigh frequencies if the VSWRs are un-controlled or unknown. The VSWR Calcprogram is a Microsoft Visual Basic 32-bit application that runs on Windows 95,98, and NT 4.

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    ,VSWR1

    VSWR1

    += 1

    .dB12VSWR1VSWR

    12VSWR1VSWRLOG

    20RCOMBINED L

    +

    =

    1

    1

  • 128 edn | February 1, 2001 www.ednmag.com

    ideasdesign

    Low-frequency filters, par-ticularly at audio frequencies,usually take the form of active filters.These filters eliminate expensive induc-tors with windings of many turns. Bothanalog and digital active filters are mostcompatible with large-scale integration atthe subsystem and system levels. Howev-er, passive filters remain a viable optionwhen you quickly need low-cost proto-types and test pieces (Reference 1). Thesefilters use no external dc excitation andrequire no complex pc boards. You caneasily wind some filter inductors usingmanual techniques. Moreover, inductorscan handle greater power levels thansmall-signal active devices. You can con-struct a simple lowpass filter with a 3-dBcutoff frequency of 10 kHz; a source/loadimpedance of 50V; five poles; and 0.02-dB-ripple, Chebyshev response. Figure 1shows the filters schematic; Table 1 pro-vides the parts list.

    Table 2 shows the measured frequencyresponse with 50V source and load im-pedances. The extremely low passband-insertion loss indicates that the inductorsunloaded Q is greater than 100.You coulduse smaller inductors, such as toroids with0.5- or 0.625-in. diameters with accept-able insertion losses (Reference 2). Notethat expensive Litz wire is unnecessary.Lowpass filters need much lower inductorunloaded Q values than do most bandpassfilters. At very low frequencies, both in-ductors and capacitors can become large.By using moderate filter-impedance lev-els, such as 50 or 75V at kilohertz fre-quencies, inductor values can be lowerthan 10 mH. With high-permeability in-

    ductor cores, fewer turns are required, andhand-winding is usually feasible. Howev-er, capacitors become large for lower fil-ter impedances. For the traditional 600Vimpedance used at audio frequencies, in-ductors are larger by an order of magni-tude. If you reduce the cutoff frequencyfrom 10 to 1 kHz, the inductor values alsoincrease by an order of magnitude.

    AcknowledgmentI acknowledge Ed Wetherhold (An-

    napolis, MD) for three decades worth ofsignificant work on low-frequency pas-sive filters and related circuits.

    References1. Wetherhold, Ed, Audio Filters for

    EN 55020 Testing, Interference EngineersMaster, 1998.

    2. DeMaw, MF, Ferromagnetic Core De-sign and Application Handbook, Chapter3, Prentice-Hall, 1981.

    0.33 mF 0.33 mF 0.33 mF 0.33 mF

    1.32 mH 1.32 mHLL

    F igure 1

    Passive filters fill the bill at audio frequenciesRichard Kurzrok, Queens Village, NY

    A five-pole passive lowpass filter yields sharpcutoff characteristics and low ripple.

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    TABLE 1PARTS LIST FOR FIVE-POLE LOWPASS FILTERFunction Value Realization QuantityInductors 1.32 mH 28 turns No. 26 on Fair Rite toroid Two

    No. 597700601-0.825-in. outer diameter330.525330.25 in. thick

    Capacitors 0.33 mmF Polypropylene with 2% tolerance FourConnectors BNC female Four-hole panel receptacle TwoEnclosure Aluminum box Hammond 1590B/Bud CU-124 OneBoard Cut by hand Vector board 169PP44C1 OneStandoffs Male/female Amatom 9794-SS-0440 Six

    TABLE 2MEASURED FREQUENCY RESPONSE FOR LOWPASS FILTERFrequency (kHz) Insertion loss (dB) Frequency (kHz) Insertion loss (dB)

    1 0.1 11 6.53 0.1 13 155 0.1 15 22.67 0.15 20 36.58 0.25 30 Greater than 509 0.6 To 1 MHz Greater than 50

    10 3.1

    these computers with another version ofC to monitor the bidirectional link, pro-vided that the transmission is not full-duplex. A simple interface mixes bothdata streams onto the receiver input (Fig-ure 1b). One channel connects to the RI(ring indicator) input of the UART.Whatever the byte value, the start bitguarantees that the RITD (ring-indicatortrailing edge) bit in the modem-status

    register is set. The interrupt-service rou-tine reads the register, clears the RITDflag, and stores its value in a buffer. Thus,the interface is ready for another byte tocome from an arbitrary direction. Themain program can identify the datasource by checking respective bits. Youcan download the C listings and exe-cutable files from EDNs Web site,www.ednmag.com. Click on Search

    Databases and then enter the SoftwareCenter to download the file for DesignIdea #2661. The programs are simple andaccept 9600, 8, E, and 1 transmission pa-rameters. You can easily adapt the pro-grams to other formats.

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    ideasdesign

    The MAX6369-74 seriesof pin-selectablewatchdog timersare designed to supervise mPactivity and indicate when asystem is working improper-ly. During normal operation,a mP should repeatedly tog-gle the WDI (watchdog in-put) before the selectedwatchdog-time-out periodelapses to indicate that thesystem is properly executingcode. If it fails to do so, thesupervisor IC asserts awatchdog output WDO tosignal that a problem exists.The cited family ofwatchdog supervisorsare available in SOT23-8packages and have selectablewatchdog-time-out periodsand delays of 1.7 msec to 104sec in seven steps. The ICsalso have selectable output-pulse widths of 1.7 or 170msec, depending on part se-lection and the state of the:Set 0, Set 1, and Set 2 pins.You can use these devices forgeneral-purpose timingfunctions, especially whenlow current consumption isimportant. The ICsconsume only 8 mAtypical and 20 mA maximumover temperatures from a 2.5to 5.5V supply. With WDIconnected to ground or V

    CC,

    the internal timer cycles,pulsing WDO low upontime-out. In addition to thelower current (20 versus 120mA), the watchdog-timer ICtakes less board space anduses no timing resistors orcapacitors. The following cir-cuits represent a few exam-ples.

    The circuit in Figure 1

    uses a MX6373 to pulseWDO low for 170 msec every5.2 sec. The load is a front-panel power-on LED with a1-kV current-limiting resis-tor. By pulsing the LEDrather than powering it con-tinuously, the average currentdecreases by a factor of 30 (88mA versus 2.4 mA). The LEDthus indicates that the equip-ment is on while minimizingbattery drain. By changingthe Set pins to Set 050V, Set15Set 25V

    CC, you can ex-

    tend the off time to 17 sec,thus reducing the averagecurrent to 32 mA. The circuitin Figure 2 is similar to theone in Figure 1 but uses aMAX6371 to turn on a loadfor 170 msec every 104 sec.The load can be a battery-powered monitoring circuitthat remains idle, savingpower and then wakes up tomake a measurement. Thecircuit in Figure 3 uses aMAX6373 with its Set inputsconfigured for timer dis-abled. If you hold Set 1 lowfor longer than the watchdogperiod (5.2 sec), then WDOpulses low. You can use thiscircuit in applications inwhich a reset button is on afront panel, for example. Youmust deliberately depress thebutton for at least 5.2 sec totrigger a reset. This featurecan prevent an accidental re-set when someone inadver-tently presses the button.

    WDI

    WD0GND

    GND

    NC

    SET 0

    VCC

    VCC

    R11k

    SET 2

    SET 1

    MAX6373

    8 mA

    F igure 1

    WDI

    WD0GND

    GND

    NC

    SET 0

    VCC

    VCC

    SET 2

    SET 1

    MAX6371

    8 mA

    100k

    LOAD

    F igure 2

    100k 100k

    WDI

    WD0GND

    GND

    NC

    SET 0

    VCC

    VCC

    SET 2

    SET 1

    MAX6373

    8 mA

    RESET

    RESET (PRESS FOR 5.2 SEC TO RESET)

    F igure 3

    Watchdog timer assumes varied rolesTerry Millward, Maxim Integrated Products, Lambourn Hungerford, UK

    A blinking LED allows a 30-to-1 average-current reduction in a power-onindicator.

    This circuit wakes up every 104 sec to turn on a load for 170 msec.

    You must press the reset button for at least 5.2 sec for the reset to takeeffect.

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    ideasdesign

    In designing mC-basedsystems, you oftenface a situation inwhich the mC has to respondto an external event happen-ing at an uncertain momentin time. One example is re-ceiving an echo from an ob-ject in a pulse-range measur-ing system. In these situa-tions, you would usually usean external interrupt. Unfor-tunately, low-end, small, in-expensive mCs have only oneexternal-interrupt vector ad-dress, so the mC can executeonly one interrupt-serviceroutine. What do you do ifthe design objectives call forthe mC to react to several in-

    IRQ

    pA0

    pA1

    pA2

    pA3

    RESET

    OSC1

    OSC2

    pA5

    pA4

    S3

    S2

    R2

    R4

    R3

    S1

    R1100k 100k

    MC68HC705KJ1CERAMIC

    RESONATOR 4 MHz

    1

    2

    3

    6

    7

    10

    11

    510

    510

    REDLED

    GREENLED

    5V

    C10.1 mF

    16

    15

    14

    13

    12

    F igure 1

    One microcontroller serves multiple external interruptsAbel Raynus, Armatron International, Melrose, MA

    You can use an inexpensive mmC to handle multiple external interrupts.

    LISTING 1MULTIPLE-INTERRUPT TEST ROUTINE

  • 134 edn | February 1, 2001 www.ednmag.com

    ideasdesign

    terrupts coming from different sourcesand to process each of them in a differ-ent way? Figure 1 shows a design tech-nique that solves the problem. Themethod is applicable to any mC, such asthe 16-pin OTP MC68HC705KJ1 fromMotorola. This mC has two options forhandling external interrupts: via the IRQpin triggered by a negative edge or via thepins pA0 to pA3 triggered by a positiveedge. You can choose these options aswell as the capability to have edge oredge-and-level triggering by setting theproper bits in the MOR (mask-optionregister).

    When you set pins pA0 to pA3 as ex-ternal-interrupt inputs, they connect in-side the mC as an OR gate. Hence, youcan trigger this mC from five external-in-terrupt sources. If the number of sourcesexceeds five, you can wire them throughan OR gate to any of the external-inter-rupt pins. To illustrate the method in thesimplest way, assume only three inter-rupt sources, represented by pushbutton

    switches S1

    to S3 (Figure 1). You can sim-

    plify the interrupt-service routines tooperate with only two LEDs. The use ofthe LEDs provides the opportunity to vi-sualize and verify the interrupt process.After initialization, both LEDs turns off.The system waits for the first interruptfrom S

    1. As a result of the interrupt, the

    green LED turns on. The system againwaits for the next interrupt from S

    2, and

    the red LED turns on. During the wait-ing period, the mC can perform somefunction, which can differ for differentprojects. Service routines in real applica-tions are much more complicated thanjust lighting LEDs. But those details are unimportant for illustrating thismethod.

    The third external interrupt from S3

    switches off both LEDs, and the mC againwaits for an interrupt from S

    1. The limi-

    tation of this method is that the sequenceof incoming interrupts must be known,but this constraint is unproblematic formost applications. Listing 1 shows the

    mC program. The key to the method is toprepare the number-address of the in-terrupt-service routine for the next ex-pected interrupt in the special registerDisp (dispatcher). In this case, the mC ex-ecutes every external interrupt with itsown individual interrupt routine. Theroutine adds a delay of 200 msec for de-bouncing the switches; you can eliminatethe delay if it is unnecessary for the in-terrupt signals. You can download List-ing 1 and associated assembly softwarefrom EDNs Web site, www.ednmag.com.Click on Search Databasesand then en-ter the Software Center to download thefile for Design Idea #2650.

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  • When you include a power opamp, such as PA05 from Apex Mi-crotechnology, in your design, it isdesirable to minimize the supply-to-out-put differential to a minimum to reducepower dissipation and to fully exploit theamplifiers output range. Our goal was todesign a power amplifier to yield 70V p-p output at 10A with a fixed gain of 10and a frequency of 30 Hz to 100 kHz. Toobtain 635V swing entailed dc suppliesof approximately 638V and two 65Vsupplementary supplies. To derive thefull 10A at lower voltage, youmust reduce the supply voltage inproportion to the output voltage to de-crease dissipation. In this case, the gainis fixed at 10. So, you can control the dcvoltage proportional to the input voltage(Figure 1). SMPS1 and SMPS2 are iden-tical voltage-programmed supplies (ex-cept for the 65V supplementary sup-plies). The precision rectifier generates dcoutput proportional to the ac-input am-plitude. To obtain approximately 66Vwhen no input signal is present, the cir-cuit adds offset voltage to the signal.

    As the input increases, theSMPS