EDN Design Ideas 2004

7/21/2019 EDN Design Ideas 2004

1/155www.edn.com January 8, 2004 | ed n 59

ideasdesign

Edited by Bill Travis

Auxiliary power of 3.3Vis replacingthe 5V auxiliary power that silverboxessupply in most computer sys-

tems, but some circuits still require a 5V

supply. Such systems impose the messytask of creating a central 5V auxiliarysupply from the 3.3V auxiliary supplyand then routing 5V power throughoutthe motherboard. An alternative exists,however, for systems in which only a fewICs need 5V: Employ inexpensive chargepumps as low-power 3.3V-to-5V con-verters and place them directly at the 5Vloads. Regulated charge pumps do thisjob,but they are uncommon, and they of-ten command a premium price. You canbuild a regulated charge pump by com-

bining an unregulated charge pump witha low-dropout regulator that reduces thevoltage to 5V. Unfortunately, that methodrequires a low-dropout regulator rated

for at least 7V, because an unregulated

charge pump can deliver 7V when its3.3V input goes to the upper limit of tol-erance. That fact eliminates the possibil-ity of using the latest low-cost, low-

dropout regulators, whosesmall geometry limits theirmaximum input to 6.5V.

You can reverse the orderby placing the low-dropoutregulator in front of thecharge pump, thereby re-ducing the 3.3V to 2.5V be-fore doubling it. That ap-

proach allows the use of alow-cost, low-voltage, low-dropout regulator, but thecharge-pump output im-pedance then becomes anissue. A low-cost chargepump, such as the MAX-1683, operating with 1-Fcapacitors exhibits a typicaloutput impedance of 35,making it unusable at cur-rents above a few milliamps.The circuit of Figure 1

shows a better way to cas-cade the charge pump with a

voltage regulator. The low-dropout reg-

ulator, IC1, reduces the 3.3V input to alower value, and the unregulated chargepump, IC

2, doubles that value to 5V. To

cancel the voltage drop that charge-pump output impedance causes, the cir-cuit feeds the 5V output back to the low-dropout regulator, which alters its outputto maintain output regulation. The avail-able headroom of at least 1V allows out-put currents to approximately 30 mA oreven higher with larger capacitors. Al-though it requires two ICs instead of asingle regulated charge pump, this ap-

proach can be cheaper because high-vol-

SHDN OUT

3

2

1 4

C1+

C1

OUT

4

1

5

3

2

5SET

1 or 3 F

1 or 3 F

1 or 3 F

1 or 3 F

30k

10k

5V AT30 OR45 mA

IN

3.3VINPUT

IC1MAX8863

IC2MAX1683

IN

F igure 1

5V power supply teamslow-dropout regulator, charge pump

Jim Christensen, Maxim Integrated Products, Sunnyvale, CA

This 5V supply, which you obtain by reducing the 3.3V input

with a low-dropout regulator and doubling that output with a

charge pump, minimizes the charge-pump output impedance

by feeding 5V back to the regulator.

TABLE 1POWER-SUPPLY PARAMETERS WITH ALL 1-F CAPACITORSV

OUTIOUT

POUT

IIN

at VIN

=3.3V PIN

Efficiency VOUT

low-dropout VRIPPLE

(V) (mA) (mW) (mA) (mW) (%) regulator (V) (mV p-p)

5.06 10 50.6 20.9 68.8 73.5 2.71 358

5.01 20 100.2 41.1 135.6 73.9 2.86 3124.9 30 147 62.2 205.3 71.6 3.02 420

TABLE 2POWER-SUPPLY PARAMETERS WITH ALL 3-F CAPACITORSV

OUTIOUT

POUT

IIN

at VIN

=3.3V PIN

Efficiency VOUT

low-dropout VRIPPLE

(V) (mA) (mW) (mA) (mW) (%) regulator (V) (mV p-p)

4.99 10 49.9 20.37 68.8 74.2 2.63 154

4.99 20 99.8 40.4 133.3 74.9 2.76 104

4.98 30 149.4 60.6 200 74.7 2.89 154

4.93 40 197.2 80.5 265.7 74.2 3.02 192

4.9 45 220.5 90.5 298.7 73.8 3.09 214

5V power supply teams low-dropout

regulator, charge pump ..............................59

Four-quadrant power supply provides

any-polarity voltage and current ..............60

Simple circuit controls

stepper motors................................................64

Simple dc/dc converter increases available

power in dual-voltage system ....................66

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What s Up sect ion a t www.edn .com.

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ume applications use unregulated chargepumps and low-current, low-voltage,low-dropout regulators. Furthermore,

because the low-dropout regulator andcharge pump are available in SOT-23packages, the overall footprint of the cir-cuit in Figure 1 is comparable to that of

a regulated-charge-pump circuit.Table 1 demonstrates the circuits abil-

ity to maintain output-voltage regulation

and deliver currents as high as 30 mA;theinput, output, and flying capacitors areall 1F. Similarly, Table 2 shows the reg-ulation for output currents to 45 mA; all

capacitors are 3 F. As you can see, loadcurrent does not affect efficiency, whichis approximately equal to the output volt-

age divided by twice the input voltage.Capacitor values affect the ripple voltageand available output current but have lit-tle effect on efficiency.

Aconventional power supply oper-ates only in the first quadrant; posi-tive-voltage output and current are

sourced to a load or, with a deliberatelymiswired output,statically in the thirdquadrant as a mi-nus supply. Theconventional supplycannot,however,op-erate in either thesecond quadrant as

an adjustable loadfor a minus supply,for example, or thefourth quadrant as adischarge-testing abattery with a specif-ic constant current,for example. It alsocannot transitionseamlessly betweenthe various modes asa function of loadcondition or control

input. The circuit inFigure 1 achieves fullfour-quadrant capa-bility with an outputtopology simi-lar to that of anordinary audio pow-er amplifier by usinga complementary pass-transistor con-figuration. The complementary sectionmay be the basic op-amp output in low-er current designs or use external powerMOSFETs in cases involving higher pow-

er. Controlling the output in the variousmodes is a simple matter when you use

the LT1970 power op amp to manage theoperation, thanks to its built-in, closed-loop, current-limiting features.

The four-quadrant supply provides at

least16V adjustability with as much as2A output capability. Figure 1 showsthe basic LT1970-based regulator section.Figure 2 shows the user-control analogsection, using an LT1790-5 reference and

an LT1882 quad-precision op amp. Theentire circuit operates from a preregulat-

ed17V bulk power source (not shown).You configure the user-control poten-tiometers, V

SETand I

LIMIT, to provide

buffered command signals: VCONTROL

and

ICONTROL

, respectively (Figure 2). You canadjust V

CONTROLfrom5 to5V, and the

LT1970 regulator circuit amplifies it toform the nominal16.5V output range.You can adjust I

CONTROLfrom 0 to 5V; 5V

represents the maximum user current-limit command. The V

CSNKand V

CSRC

17V

17V

CURRENT-LIMIT LED 1.5k

10 F35V

10 F35V

10

100BAV99TA

100

261

220 pF

330 pF

1 nF

0.1 F

0.1 F

0.1 F2 F

4.7 F50V

47 pF

0.11W

10k

10k

10k

10k

9+

13

12

8

715

16 1719

24

6

5

SS+

VV+ 3

10k

1, 10,11, 20

3.01k

CW

CW

150 1 nF

IRF9540

IRLZ24

TO VOLTAGEDIGITAL PANEL METER

+VIN

CURRENTDIGITAL PANEL METER

VIN

VOLTAGE DIGITALPANEL METER VIN

CURRENT DIGITALPANEL METER +VIN

ICONTROL

VCONTROL

VCSRC10k

VCSNK10k

VCSNKVCSRC

ISRCISNK

VEE

VCC EN

FILTER

COMMON

OUTPUT

RETURN

+

+

+

3.01k

LT1970CFE

F igure 1

Four-quadrant power supply providesany-polarity voltage and current

Jon Munson, Linear Technology, Milpitas, CA

You can obtain four-quadrant power-supply operation by using a power op amp in the output section.



ideasdesign

trimmers attenuate the ICONTROL

signal toset the precise full-scale currents for sinkand source modes,respectively (Figure 1).

A 0.1 resistor in the load return sens-es the output current and provides theLT1970 with feedback during current-limiting operation. With this sense re-sistance, setting the current-limit trim-mers to 100% would allow the LT1970 tolimit at approximately5A,but,becausethis application requiresa 2A maximum current,you set the trimmers toapproximately 40% ro-tation when calibrated.To prevent internal con-

trol contention at lowoutput current, the LT-1970 sets a minimum-current-limit thresholdthat corresponds to ap-proximately 40 mA forthe sense resistance.An-other nice feature of theLT1970 is the availabili-ty of status flags, which,in this case, provide asimple means of drivinga front-panel LED to in-

dicate when current-limiting is active. TheLT1970 featuressplit power con-nections that allow youto power the internaloutput section inde-pendently from the ana-log-control portion.Theflexibility of this config-uration allows directsensing of the op amps output currentvia resistance in the V (Pin 19) and V

(Pin 2) connections. This feature gives aconvenient means of establishing ClassB operation of the MOSFET-output de-vices using a current-feedback method,in which the op-amp output current isconverted to a gate-drive potential, there-by having the MOSFETs turn on only tothe extent needed to help the op ampprovide the output demand.

Because power supplies inherentlymust drive heavy capacitive loadsnamely, circuits with high-value bypasscapacitorsand any overvoltage could

damage the circuit, pay careful attention

to compensating the op amp for minimalovershoot under all loading conditions.As with most op amps, the LT1970s in-

ner- and outer-loop feedback accomplishcapacitive-load tolerance. In this situa-tion, the op amp itself is resistively de-coupled from the load. The dc feedbackfor the LT1970 uses differential voltagesensing to eliminate the regulation errorthat would otherwise occur with the cur-

rent-sense and lead resistances in serieswith the load. You can connect a pair of

inexpensive digital panel meters to theoutput to monitor the output conditionsin real time (Figure 1). (The two digitalpanel meters do not share commoncon-nections, which may complicate theirpowering.) Note that the selected current-sense resistance optimizes a digital-pan-el-meter display with the usual200-mVfull-scale sensitivity to present as much as1.999A, for example. One word of cau-tion: When you use this supply in placeof a conventional single-quadrant supplyto power sensitive electronics, its good

practice to connect a reverse-biased

Schottky diode, such as a 1N5821 cath-ode, to the more positive connection, tothe output binding posts. Alternatively,

you could use a disconnect relay and pow-er sequencer in the design to protect theload from any energetic reverse transientsduring turn-on and turn-off of the mainbulk supply.

An adjustable power supply is an in-dispensable tool in any electronics lab. It

can be even more useful in many circum-stances if it provides the ability to adjust

continually through 0V to the polarity,adjustably limit current, or both in eitherthe source or the sink directions. Theseadditional capabilities provide convenientmethods of driving or loading circuitsthat are under development or test thatmight otherwise require very special orcustom equipment, such as active-loadunits or dc-offset generators. You canreadily obtain these features if you basethe linear-regulator design on the versa-tile LT1970 power op amp, which includesbuilt-in adjustable- closed-loop current-

limiting functions.

1/4

LT1882_

+ 1/4

LT1882

_

+1/4

LT1882

_

+ 1/4

LT1882

12

13

14

11

0.1

F

1 F 1 F

0.1 F

1 F

1k17V

5V

REFERENCE

17V1k

4

49.9k 49.9k

3

1

2

VSET100k

10-TURN

CW

CW

1k

1k50k

ILIMIT10

9

8

100k

100k

ICONTROL

VCONTROL7

5

6

_

+

LT1790-517V2k 4 6 5V REFERENCE

1 2F igure 2

The user-control section allows you to set the voltage range and current-limit parameters for the output section in

Figure 1.



ideasdesign

Stepper motors areuseful in many con-sumer, industrial,

and military applica-tions. Some, such as per-sonal-transportationsystems, require precisespeed control. Stepper-motor controllers can besimple (Figure 1), butthey require a variable-frequency square wave

for the clock input. TheAD9833 low-powerDDS (direct-digital-syn-thesis) IC with an on-chip,10-bit DAC is idealfor this task,because youneed no external com-ponents for setting theclock frequency (Figure2). The de-vice containsa 28-bit accumulator,which allows it to gener-

ate signals with 0.1-Hzresolution when you operate it with a 25-MHz MCLK (master clock). In addition,the circuit can easily stop the motor if youprogram a 0-Hz output frequency.

Figure 3 shows the complete sys-tem.The most significant bit of the on-chip DAC switches to the V

OUTpin of the

AD9833, thus generating the 0-to-VDD

square wave that serves as the clock inputto the stepper-motor controller. Writingto the frequency-control registers via asimple, three-wire interface sets the clock

MOTOR

WINDING

35 2 7 8

15

16

16

11

10

4

9

12

13

J

J

K

K

Q

Q

Q

Q

STEP 5V 12V

7

45

6

10

5V

148

9 IC2

IC2

12

13

5V

GND

2

1

IC1

IC1

IC1

IC1

3

11

NOTES: IC1: SN74HC86.

IC2: SN74LS76A.

14

F igure 1

Simple circuit controls stepper motorsNoel McNamara, Analog Devices, Limerick, Ireland

A stepper-motor controller requires only a few logic circuits.

FULL-SCALE

CONTROLCOMPARATOR

ONBOARD

REFERENCE

10-BITDAC

200

SERIAL INTERFACE

AND CONTROL LOGIC

FSYNC SCLK SDATA

CONTROL REGISTER

PHASE0 REG

PHASE1 REGVOUT

MULTIPLEXER

MULTIPLEXER

MULTIPLEXER

MULTIPLEXER

MSB

DIVIDE

BY 2

AD9833

SINROM

1228-BIT PHASEACCUMULATORFREQUENCY 0 REGISTER

FREQUENCY 1 REGISTER

MCLK REGULATOR

2.5V

AVDD/

DVDD

AGND DGND VDD CAP/2.5V

F igure 2

The AD9833 DDS IC generates frequencies with 0.1-Hz resolution.



ideasdesign

frequency. Writing a 0 to the frequencyregister stops the clock,thereby stoppingthe stepper motor.When you are not us-

ing the DAC, you can power it down bywriting to a control register. This pow-er-down action results in the AD9833sdrawing only 2 mA from the supply. Re-ducing the MCLK frequency can furtherreduce the supply current. The AD9833is available in a tiny,10-lead pack-age, so you can assemble thecomplete control system on a very smallpc board.

MICROCONTROLLER AD9833

FSYNC

SCLK

SDATA

MCLK

VOUT

STEPPER-

MOTOR

CONTROLLER

STEPPER

MOTOR

VDD

OV

The complete stepper-motor controller uses a DDS IC to generate the variable frequencies

for the circuit in Figure 1.

F igure 3

The schematic in Figure 1 shows away to increase the power availablefrom a current-limited 5V supply by

adding power from a 5V supply. Thedc/dc converter generates a single 12V,150-mA (1.8W) output from two regu-

lated and current-limited input sourcesat 5V, 300 mA (1.5W) and5V, 300 mA(1.5W). Because the input usesdifferent-polarity voltage sources,the design uses a flyback dc/dc convert-er to avoid a system-grounding prob-lem. Level-shifted feedback sensing us-ing a pnp transistor, Q

1, references the

feedback signal to the negative inputvoltage. You calculate the feedback-re-sistor divider by using the formulaR

1R

4(V

OUTV

BE)/V

REF, where R

1con-

nects to the emitter of Q1, R

4connects

to the collector of Q1, VBE is the base-emitter voltage of Q

1, and V

REFis the

feedback reference voltage of the switch-ing regulator.

To simplify the circuit,the flyback con-verter in Figure 1 uses an LT1946 mono-lithic switching regulator. The voltagerating of the monolithic regulator has tobe greater than the maximum switchingvoltage of the flyback converter, calculat-ed by [(V

IN1|V

IN2|)

MAXV

OUT(MAX)/(T

1

turns ratio)]VSPIKE

. The maximumswitching voltage is approximately 25V

for the circuit in Figure 1. Note also that

the input capacitor and dc/dc regulatorinput must be able to handle a maximuminput voltage of 10V, resulting from thecalculationV

IN1(MAX)|V

IN2(MAX)|. In

an event of fault-current conditions, suchas shorted input or output,a zener diode,D

2, creates the undervoltage-lockout

threshold to turn off the LT1946 when-ever either input source is in current lim-it or the input voltage (V

IN1|V

IN2|)

drops below 6V to help the input supplyrecover when the fault condition is re-

moved. In a system with two available

current-limited power supplies, you canconvert the two supplies into a single sup-ply that has more power-handling capa-bility than either of the two inputs.A fly-back topology based on an LT1946monolithic converter offers a simple ap-proach to the grounding problem and thefeedback-sensing problem inherent in adual-input power supply. Sharing thepower between two input sources notonly adds output-power capability, butalso increases the overall flexibility of the

system.

VIN SW

GND

FBSHDN

SS VC

COMP

LT1946

D26V ZENER

R2100k

R315k

R41.24k

C24.7 F

D1MBRS140

C42.2 nF

R111.3k

C14.7 F

Q1FMMT3906

C3100 nF

8

4 7

6 5

4

3

1

2

2

31

5V,

300-mA

INPUT

5V,

300-mA

INPUT

12V,

150-mA

OUTPUT

5V INPUT

N=1:1

F igure 1

Simple dc/dc converter increasesavailable power in dual-voltage systemDavid Kim, Linear Technology, Milpitas, CA

Combining two opposite-polarity power supplies can increase the available power from a flyback

regulator.


6/155www.edn.com January 22, 2004 | ed n 79

ideasdesign


Digitally controlled gain is aneveryday analog-design element.You frequently find this element in

an op-amp-based, transimpedance cur-

rent-to-voltage converter. When you de-sign digital gain control into such a con-verter, the usual scheme is to arrangethings such that a digital multiplexer se-lects the appropriate feedback resistor foreach gain figure. In Figure 1, op amp IC

1

is connected in a typical topology butwith a twist. The normal way to arrange

the gain-setting multiplexer would be totake the converters output directly fromthe op amps output pin (IC

1, Pin 6).The

trouble with this method is that the on-

resistance of the multiplexer would thenbe effectively in series with the selectedfeedback resistance. In cases such as thisone, in which the feedback resistanceranges as low as a few hundred ohms orless, the resulting gain error can be large.For example, the on-resistance of theHC4052 in Figure 1 can exceed 100.

15V

15V

5.1k

390

1k

5V

220 F6V

220 F6V

GAIN

1248163264128

S1

OCOCOCOC

S2

CCOOCCOO

S3

OOOOCCCC

O=OPEN=OFF.C=CLOSED=ON.

NOTES: *=1% METAL FILM.5V

+

+ +

+

++

+

+

+

+

+

+

2.4k

GREENLED

15V

_

+

_

+

+

+

_

+

_

+

7915

DETECTOR

MCT

100

47 F25V

220 F16V

220F6V

220 F16V

24V

220F6V

220 F16V 22 F

16V 20k

22 F

16V

22 F6V

6.49k*

1620*

402*

43

3

0.1F

0.1F

75V

13

9

10

5V

2k

3

2

2

1

1

0

MCT4052

0

C

C

A

B

8 6 6 5 4

G0

G1

13 2 1k

9 10 1311 12 1k8

5VHCT14

390 pF200 kHz

4.22k*

+15OP37

10 F6V

GP

1k* 1k*

1k

1k*

15V

8

4

7

15V15V

7

15V

47OUT

2

3

1

3.01k*

14

7

5

1

11

15

14

12

2

100*47 F25V

15V 10k 10k

15V

OP37GPOR

LT1028CN8

MULTIPLEXER

7

4

6

2

2k

13k*

Q12N4403

Q22N3094

IC1

IN914

IC4

IC3

LF353N

IC2

2

6

43

VE

S2

5

6

S1

S3

4

2

16

1.33k*

66.5*

VD7815 15V

39

200*

15V

BIAS

3

15V

24V

GND

221

LF353NHEAT SINK

F igure 1

Force/sense connection eliminatesmultiplexer on-resistance errorStephen Woodward, Marine Sciences, Chapel Hill, NC

In this programmable-gain circuit, the on-resistance of the gain-setting multiplexer plays no role in the determination of gain.

Force/sense connection eliminates

multiplexer on-resistance error ..................79

Analog multiplexer uses

flying capacitors ............................................80

FPGA-configuration schemeis flexible ..........................................................82

Add fault protection to

a 4- to 20-mA loop supply ..........................84

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ideasdesign

That figure is equal to that of the lowestgain-setting resistor and, therefore, thesource of 100% error. The obvious ap-proach, using larger resistors, works

poorly when you need high-frequencyperformance. The resulting RC delayproducts can cause frequency peaking,ringing, and, sometimes, outright oscil-lation.

This Design Idea offers an approachthat makes the current-to-voltage con-verter gain independent of multiplexerresistance. The idea is to use two multi-plexers in a force/sense topology suchthat the output comes from the forceend of the selected gain resistance, ratherthan directly from the op amps output.

Assuming that that the load presented tothe senseoutput is reasonably high,the

result is a gain product that is insensitiveto on-resistance. The remainder of thecircuit surrounding IC

1comprises a

high-performance bias and preamplifier

circuit for a cryogenic (liquid-nitrogen-cooled),mercury-cadmium-telluride in-frared detector. These broadband, pho-toconductive optical sensors are popularin IR spectrometers.They are particular-ly popular in Fourier-transform-typespectrometers. Their popularity stemsfrom their low noise, wide optical-wave-length responsivity, and electrical re-sponse of faster than 1 MHz.

Notable features of the circuit in Fig-ure 1, besides the force/sense gain-set-ting topology, include dynamic biasing

(via Q1 and Q2) of the MCT detector, 64-to-1 (36-dB) digitally programmable

gain, 128-to-1 (42-dB) manual-switch-settable gain, approximately 200-kHzbandpass response, and approximately700-nV rms input-referred noise of less

than 1 nV/Hz). One trick that helpsachieve this noise performance, otherthan the use of the superquiet LT1028 opamp for IC

1, is the cascaded-inverter

HCT14 structure. The HCT14s serve nopurpose other than to block entry ofnoise, which might be present on thedigital gain-setting lines, into the gain-setting-multiplexer circuitry. Withoutthese inverters, any such digital noise, acommon cause of gremlins in high-gain,computer-controlled analog circuitry,could easily become capacitively coupled

to the ac signal path.

This Design Idea describes away to increase the number ofanalog inputs to your micro-

controller for cases in whichadding an analog-multiplexer chip

or upgrading to a microcontrollerwith more inputs might be im-practical. If the microcontrolleryoure using has some spare I/Opins and at least one of them isbidirectional or is amenable totristating,you can configure a sim-ple analog multiplexer usingswitched capacitors. Figure 1shows a two-input multiplexer. Atypical switched-capacitor multi-plexer completely disconnects thecapacitor from the sensed voltage

before sampling the voltage acrossthe capacitor.

To use a typical microcon-trollers I/O ports, one terminal ofthe capacitor remains connectedto the input source through aresistor. During most of theoperating time, pins 12, 14,and 15are configured as output pins andare held at logic 0. Diodes D

1and

D2

do not conduct, so capacitorsC

1and C

2charge to the values of the in-

put voltages V1

and V2, respectively. To

sample the voltage stored in the capaci-

tors, pin 12 becomes an input, and thepin associated with each channel switch-

es high while the microcontrollers com-

parator compares the voltage on Pin 12with the reference voltage. Listing 1,

which is available on the Web version of

PB0/COMP

COMP

PB4

PB5

VDD

5V

5V

0.33 F

20

17

16

13

10

4.7k

4.7k

ATMEL

AT90S1200A

PB2

PB3

15

14

12

D21N916

C20.01 F

C10.01 F

R2

R1

100k

100k

V2

V1

D11N916

REFERENCE

VOLTAGE

50k

LED1

LED2

GND

+

F igure 1

Analog multiplexer uses flying capacitorsDick Cappels, Mesa, AZ

The LEDs in this circuit indicate when the sampled input voltages are above the reference voltage on

Pin 13.



ideasdesign

this Design Idea at www.edn.com, gives the code frag-ment that samples the inputs.

The voltage on Pin 12 isVPIN12

VDDV

DIODEV

IN,

where VPIN12

is the voltage ap-plied to the analog input ofthe comparator; V

DDis the

power-supply voltage (5V inthis example); V

DIODEis the

voltage across thediode, and V

INis

the voltage applied to input ofthe RC filter. During the sam-pling of one input, the voltageon the positive terminals of

the capacitors exceeds VDD;thus, D1

and D2

are in serieswith microcontroller pins 14and 15 to block voltages aboveV

DDand prevent C

1and C

2

from discharging into thepower supply. Also duringsampling, C

1and C

2are in se-

ries with the filter resistor ofthe input undergoing sam-pling, causing the capacitorsto discharge through the re-sistor. For this reason, it is im-

portant to keep the RC timeconstant with respect to thesampling period. The worst-case voltage error occurs inthe second channel to be sam-pled,when both V

1and V

2are

at 0V: where TSAMPLE

is the time one of thediodes anodes switches to V

DD(3 sec

in this example). This sampling timeuses the assumptions R

1R

2, C

1C

2,

and the fact that the sampling periodsfor each channel are the same.

With the 1-MHz con-troller in Figure 1, sam-pling time is a total of 6

sec for the two channels;using a 16-MHz controller,the total sampling timewould be only 375 nsec.When you expand the cir-cuit for more inputs (forexample, using the four-in-put multiplexer in Figure2a), you must take the ex-tra sampling time into ac-count. To maintain a lowduty cycle and thus allowthe RC filters to charge to

the full input voltage, thesoftware should infre-quently call the samplingroutine. An interrupt every2048 clock cycles calls thesampling routine in thisexample. The voltage at Pin12 in Figure 2a is inverted,and, because of the isola-tion diodes, the maximuminput voltage is a diodedrop below V

DD(approxi-

mately 4.4V). If you mul-

tiplex both inputs, the cir-cuit compensates for boththe polarity and the diodedrop (Figure 2b). Listing 2in the Web version of thisDesign Idea (www.edn.

com) gives the microcontroller assem-bly code for the multiplexer scheme. Youcan download the software from theWeb version of this Design Idea atwww.edn.com.

A

A+

A

B

B

B+

5V

12 +

(a)

A

B

C

D

5V

12 +

(b)

F igure 1

The technique lends itself to variations, such as switching sets of inputs (a)

and expanding to more than two inputs (b).

FPGA-configuration scheme is flexibleZhe Lou, Ghent University, Ghent, Belgium

FPGAs are popular in circuit designbecause of their flexibility and effi-ciency. You need to program an

FPGA by loading configuration data intodesignated configuration memory. Be-cause most FPGAs have no internal non-volatile memory, you must store the con-

figuration files in external devices. Whenyou use many FPGAs in a design, it is in-

advisable to put a large amount of exter-nal memories near the FPGAs. Thememory consumes a lot of area and in-creases the difficulty of the pc-board lay-out. Consider Xilinx (www.xilinx.com)FPGAs. Xilinx offers daisy-chainingtechniques to program multiple FPGAs

from a single source. However, whenyou want to change only one FPGAs

functions and keep others unchanged, itis unwise to reprogram all FPGAs, be-cause it takes a lot of time and can causeunexpected problems in the related cir-cuits. This Design Idea describes how toindividually program multiple FPGAswith limited resources. It uses a serial

port of the Analog Devices (www.analog.com) ADSP21065L to arbitrarily



ideasdesign

program four FPGAs (Figure1).

A DSP processor, the AD-

SP21065L, serves as a micro-controller to program the FP-GAs. The configuration busconsists of the Clk, Data, Pro-gram, Init, and Done signals.The output data from theADSP21065L is syn-chronous with the Clksignal, and the Pro-gram (output), Init (input),Done (input),and two controlsignals (output) are theADSP21065Ls I/O flags. The

rest of the circuit comprisesfour FPGAs from Xilinx. The arrows tothe FPGAs represent the configurationbus. The trick is in the so-called switch-board, which traces the configuration busto an FPGA according to the ADSP-21065Ls control signals. At first thought,

some bidirectional buffers, for example,74LVT16245s, would seem suitable forthis requirement by linking the controlsignals to OE and T/R pins of the buffers.

But after taking a closer look at the sit-uation, this approach would be difficult

because the Init and Doneare output signals from theFPGAs, which you cannot

merge together. Therefore,the buffer you are look-ing for should have multi-plexing or demultiplexingcapabilities. This designuses the 74FST3253 dual4-to-1 multiplexer/demul-tiplexer bus switch fromOn Semiconductor (www.onsemi.com) to imple-ment this function. Byconnecting two controlsignals to the two select in-

puts, S0 and S1, you cancause I/O Signal A to connect to I/O linesB1, B2, B3, or B4, respectively, if the val-ue of the two control signals are 00, 01,10, or 11.

ADSP21065L

CLK

DATAPROGRAM

INIT

DONE

CONTROL

LOGIC

SWITCHBOARD

(74FST3253)

FPGA 1

FPGA 2

FPGA 3

FPGA 4

A

S0

S1

B1

B2

B3

B4

74FST3253

CLK

F igure 1

Separately programming

FPGAs sometimes makes

more sense than using a

daisy-chain technique.

A4- to 20-mA current loop consistsof a power source and a current-measuring device at the control end

and a field transmitter that sensesprocess-variable information, such astemperature or pressure, and converts itto a current (Figure 1). Most such indus-trial current loops are powered by 24V dc,but that voltage can range from 12 to 36V.The loop voltage in older systems can beeven higher. Many such applications re-quire current limiting, fault protection,

or both. For example, a short circuit oranother high-current fault in one of sev-eral loops powered by a single sourcecan produce a power-supply failurethat disables all transmitters powered bythat source. Intrinsically safe loops,on theother hand,include a barrier module thatlimits current and voltage to the trans-mitter. Fault-protected sources can addanother level of system safety. Setting acurrent limit on each loop lets you accu-rately size the power supply without over-specifying it. Figure 2 shows one form of

flexible fault protection for the 24V pow-

er supply of a 4- to 20-mA loop.It also in-cludes circuitry for recovering a digitalsignal superimposed on that loop. IC

1, a

high-side current-sense amplifier withcomparator and reference,senses the loopcurrent in R

1as an 8- to 40-mV voltage

and amplifies it by 100, producing an out-

put-voltage range of 0.8 to 4V. That out-

put,VOUT

, can directly drive external me-ters, strip-chart recorders, and A/D-con-verter inputs.

The R2-R

3voltage divider sets the se-

lected fault-current trip point for IC1s

first internal comparator at 0.6V. Settingthe trip point for a 50-mA fault, for in-stance,establishes the following relation-ship between R

1and R

2: R

2/(R

1R

2)

0.6V/(R1100I

FAULT), so R

115.67R

2.

When faults occur, the COUT1

output as-sumes a high-impedance state and is

pulled high by R3. The noninverting cas-caded-transistor pair Q

2-Q

3provides an

interface to the high loop voltage andpreserves a proper logic polarity for con-trolling the gate of Q

1. Q

1is held in the off

state until pushbutton PB1or another re-

set signal resets IC1s first comparator.(To

disable this comparators latched output,tie the Reset# pin to ground.) Zenerdiode ZD

1protects Q

1s gate-source junc-

tion from overvoltage.IC

2and its associated circuitry can re-

cover any digital information imposed on

the 4- to 20-mA loop current by modu-

_

+

4- TO 20-mA

FIELD TRANSMITTER

CURRENT-

SENSE

RESISTOR

24V

DC

STRIP-CHART

RECORDER

4 TO20 mA

0 TO

100

Add fault protection to a 4- to 20-mA loop supplyMark Pearson, Maxim Integrated Products, Sunnyvale, CA

Industrial applications widely

use the basic structure of a 4-

to 20-mA current loop.

F igure 1



ideasdesign

lation. The High-way-AddressableRemote Transduc-

er Protocol, for in-stance, typicallyuses FSK (fre-quency-shift key-ing) of 1200 to2400 Hz to modu-late the loop cur-rent between the0.5mA levels.(For this circuit,the modulat-ed signal atV

OUT(Pin 2 of IC

1)

is 0.1V.) VOUTfrom IC1

is capac-itively coupled toIC

2and amplified

by that device torecover such digital signals. IC

1includes

a second comparator with inverting in-put, which you can use to cancel the in-

version in IC2s digital-signal output.

Though not essential, this comparatoroutput (C

OUT2) can also present the re-

covered digital signal as a clean rectan-gular waveform for driving external cir-cuitry.

_

+IC2MAX4322

5V

10k

R2

154kR

3

10k

2.2k 102k

10k

10k

5V

10k

10k

2.6k

10k

ZD15.1V

Q32N3904

Q1RFD10P03L

Q22N3904

PB1FAULT RESET

5V

0.1 F

9

2

3

4

5

10

1

6

7

8

RS

VOUT

CIN1

CIN2

GND

RS

+VCC

RESET#

COUT2

COUT1

IC1MAX4375

2

R1

5V

4 TO 20mA LOOP24V DC

LOOP RETURN

TO PROCESS-INDICATOR PANEL OR ADC

DIGITAL-SIGNAL OUTPUT

TO FIELD TRANSMITTER

This circuit provides fault protection and digital-signal recovery for a 4- to 20-mA current loop.

F igure 2


11/155www.edn.com February 5, 2004 | ed n 69

ideasdesign


You can effectively double thesample rate of a DAC by interleavingtwo DACs into a single unit. Updat-

ing each DAC on an alternating basis andswitching to the appropriate output dou-

ble the effective throughput of the over-all system. It is essential to overall per-formance that you use a high-quality,high-speed switch in the multiplexing ofthe DACs outputs. The current-modeDACs in this Design Idea allow for cur-rent-steering implementation of the out-

put switch. Current steering uses two dif-ferential-transistor pairs cross-coupled inthe form of a four-quadrant multiplier(Figure 1). In this topology, the satura-tion voltages of the transistors are mini-mal, voltage swings are small, and switch-ing speeds are high.

The 2.5-GHz AD8343 mixer containsa complete four-quadrant-multiplierstructure that you can use as a high-speed, current-mode switch. The bias

circuitry internal to the AD8343 sets thedc voltage at the emitters to approxi-mately 1.2V, which in turn sets the com-pliance voltage necessary at the DAC

SEL SEL SELSEL

INP INN

OUTP

OUTN

Double DAC rate by using mixers as switchesRandall Carver, Analog Devices, Greensboro, NC

You can use cross-coupled

differential transistor pairs as

current-mode switches.

F igure 1

DATA BUS A

DATA BUS B

IC1AD9731

10-BIT,

170M-SAMPLE/SEC

DAC

D0-D9

CLK

RSET

IOUT

IOUT

REF_IN

CA_OUT

CA_INREF_OUT

CLK

1.96k

50

IC2AD9731

10-BIT,

170M-SAMPLE/SEC

DAC

D0-D9

CLK

RSET

IOUT

IOUT

REF_IN

CA_OUT

CA_INREF_OUT

CLK

1.96k

50

INPINN

LOP

LON

INPINN

LOP

LON

OUTP

OUTN

IC5AD8343

2.5-GHz MIXER

OUTP

OUTN

IC6AD8343

2.5-GHz MIXER

5V

5V

50

50

10CLK

10CLK

IC390LV027A

IC490LV027A

OUT

F igure 2

Ping-ponging the outputs of two DACs effectively doubles the throughput rate.

Double DAC rate by using mixers

as switches ......................................................69

DDS IC plus frequency-to-voltage converter

make low-cost DAC........................................70

Low-noise ac amplifier has digital control

of gain and bandwidth ................................72

1-kV power supply produces

a continuous arc ............................................76

Publish your Design Idea in EDN. See the

What s Up sect ion at www.edn.com .


www.edn.com


12/15570 edn | February 5, 2004 www.edn.com

ideasdesign

outputs. With only a minimal drive sig-nal at the base connections,the emittersappear as a virtual ac ground. The re-

duced voltage swing at these nodes min-imizes the effect of any parasitic capac-itances. This Design Idea uses twoAD8343 mixers as high-speed switchesto multiplex the differential output cur-rents derived from two AD9731 DACs(Figure 2). On the output side of themixers, the termination resistors allowfor a dc path to the supply, provide forthe current-to-voltage conversion, and

present a single-ended back-termina-tion impedance of 50. This configura-tion allows the circuit to drive a re-

motely located, 100, differential loadvia two 50 coaxial cables. The low-lev-el clock signals at the LO inputs comefrom high-speed LVDS buffers termi-nated in resistances of 10. The ap-proximate 3.5-mA p-p drivers pro-duce roughly 70-mV p-p drive atthe LO inputs. Figure 3 showsthat the circuit provides output rise andfall times faster than 200 psec.

F igure 3

The circuit in Figure 2 produces outputs with

less-than-200-psec rise and fall times.

Precision DACs are es-sential in many con-sumer, industrial, and

military applications, buthigh-resolution DACs canbe costly. Frequency-to-voltage converters havegood nonlinearity specifi-

cationstypically, 0.002%for the AD650and are in-herently monotonic. ThisDesign Idea shows how youcan use a frequency-to-voltage converter and aDDS (direct-digital-syn-thesizer) chip for precisedigital-to-analog conver-sion. The DDS chip gener-ates a precision frequencyproportional to its digitalinput. This frequency

serves as the input to a volt-age-to-frequency converter,thereby generating an 18-bit analog voltage pro-portional to the origi-nal digital input. Figure 1shows how the AD650 isconfigured for frequency-to-voltage con-version. With R

1R

320 k and

COS620 pF, a full-scale input frequency

of 100 kHz produces a full-scale outputvoltage of 10V. (See Analog Devices(www.analog.com) application note AN-

279 for more details on using the AD650as a frequency-to-voltage converter.)

Resolution of 18 bits requires a pro-grammable clock source with a frequen-cy resolution of 0.38 Hz (100 kHz/262,144). The AD9833 low-power DDSIC with on-chip 10-bit DAC is ideal forthis task, because setting the clock fre-

quency requires no external components.The device contains a 28-bit accumula-

tor, which allows it to generate signalswith 0.1-Hz resolution when you operateit with a 25-MHz master clock. Figure 2shows a block diagram of the AD9833DDS chip. Figure 3 shows the completesystem. The most significant bit of the

on-chip DAC switches to the VOUT pin ofthe AD9833, thus generating the 0V-to-

R3

CINT

VOUT

R1 _

+

ONE

SHOT

IN

OUT

0.6V

_

+

VS

VS15V

1

6

7

2

4

14

9

8

13

11

OP

AMP

3

5

S1

fIN0.1 F

0.1 F

FREQUENCY

COS

OUT

1 mA

COMPARATOR

AD650

12

10

20k

250k

15V

ANALOG

GROUND

2k 500

500

5V

1N914

560 pF

INPUT

OFFSET

TRIM

F igure 1

DDS IC plus frequency-to-voltage convertermake low-cost DACNoel McNamara, Analog Devices, Limerick, Ireland

This circuit shows the AD650 in a frequency-to-voltage configuration.



ideasdesign

VDD

square wave that serves as the clockinput to the AD650 voltage-to-frequen-cy converter. Writing to frequency-con-trol registers via a simple three-wire in-terface sets the clock frequency,

thus programming the voltage out-put.

FULL-SCALE

CONTROLCOMPARATOR

ONBOARD

REFERENCE

10-BIT

DAC

200

SERIAL INTERFACEAND CONTROL LOGIC

FSYNC SCLK SDATA

CONTROL REGISTER

PHASE0 REG

PHASE1 REGVOUT

MULTIPLEXER

MULTIPLEXER

MULTIPLEXER

MULTIPLEXER

MSB

DIVIDE

BY 2

AD9833

SIN

ROM12

28-BIT PHASE

ACCUMULATOR

FREQUENCY0 REGISTER

FREQUENCY1 REGISTER

MCLK REGULATOR

2.5V

AVDD/

DVDD

AGND DGND VDD CAP/2.5V

F igure 2

This DDS chip generates signals with 0.1-Hz resolution from a 25-MHz clock.

MICROCONTROLLER AD9833

FSYNC

SCLK

SDATA

MCLK

VOUT fINAD650

VOLTAGE-

TO-FREQUENCY

CONVERTERDDS

VOUT=0 TO 10V,

18-BIT RESOLUTION

F igure 3 This DAC system delivers 0 to 10V output with 18-bit resolution.

I

n low-noise analog circuits,a high-gain amplifier serves at the input to

increase the SNR. The input signallevel determines the input-stage gain;low-level signals require the highest gain.It is also standard practice in low-noiseanalog-signal processing tomake the circuits bandwidthas narrow as possible to pass only theuseful input-signal spectrum. The opti-mum combination of an amplifiers gainand bandwidth is the goal of a low-noisedesign. In a data-acquisition system,dig-ital control of gain and bandwidth pro-vides dynamic adjustment to variations

in input-signal level and spectrum. Fig-ure 1 shows a simplified circuit for an ac

_

+

_

+

_

+

_

+GAIN-CONTROL PGA(GAIN A)

BANDWIDTH-CONTROL PGA(GAIN B)

VINC1

C2

R1

R2

VOUT

GAIN=1

NOTES:

VOUT=(GAIN A)VIN.

1

2R1C1

1

2 R2

C2



ideasdesign

VOUT1VINVOUT2VINVOUT5VINVOUT10VINVOUT20VINVOUT50VINVOUT100VIN

GN2 GN1 GN0

0 0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

BANDWIDTH1 TO 10 Hz

BANDWIDTH1 TO 20 Hz

BANDWIDTH1 TO 50 Hz

BANDWIDTH1 TO 100 Hz



BANDWIDTH1Hz TO 1 kHz

BW2 BW1 BW0

0 0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

LTC6910-1 LT1884

1 8

7

6

5

2

3

4

GAIN

CONTROL

LTC6910-1

1 8

7

6

5

8

7

6

5

2

3

4

1

2

3

4

BANDWIDTH

CONTROL

0.1 F

VIN

V V V

C1

10 F

R1 R2

15.8k 15.8k

C2

1 F

V

0.1 F

V

0.1 F

V

0.1 F

0.1 F0.1 F

R4

R3

15.8k

15.8k

IC3IC2IC1

VOUT

F igure 2

This detailed implementation of the circuit in Figure 1 operates with dual power supplies.

amplifier with control of

both gain and bandwidth.The amplifiers input is aPGA (programmable-gainamplifier) providing gaincontrol (Gain A). Followingthe input PGA is a first-or-der highpass filter formedwith capacitor C

1and input

resistor R1

of an integratorcircuit. Inside the integra-tors feedback path, the gainof a second PGA (Gain B)multiplies the integrators

3-dB frequency, thus pro-viding bandwidth control.

Figure 2 shows a com-plete circuit implementa-tion using two LTC6910-1digitally controlled PGAsand an LT1884 dualop amp. The inputLTC6910-1, IC

1, provides

digital gain control from 1 to 100 usinga 3-bit digital input to select gains of 1,2, 5, 10, 20,50, and 100.The circuits low-er3-dB frequency is fixed and set to 1

Hz. A second LTC6910-1, IC3, is insidean LT1884-based (IC

2) integrator loop.

The integrators digital gain control be-comes digital bandwidth control, whichprovides an upper 3-dB frequencycontrol of 10 Hz to 1 kHz. The circuits

low-noise LT1884 op amp and LTC6910-1 (9 nV/Hz for each device) combine

to provide high SNR. For ex-

ample, the SNR is 76 dB fora 10-mV peak-to-peak signalwith a gain of 100 and 100-Hz bandwidth or 64 dB fora 100-mV peak-to-peak sig-nal with a gain of 10 and 1-kHz bandwidth. With anLT1884 dual op amp (gain-bandwidth product of 1MHz), the circuits upperfrequency response can in-crease to 10 kHz by reducingthe value of C

2. (The lower

3-dB frequency increasesby reducing the value of C

1.)

The circuit in Figure 2 oper-ates with5.5V dual powersupplies. You can convert itto a single-supply 2.7 to 10Vcircuit by grounding Pin 4 ofIC

1, IC

2, and IC

3; connecting

a 1-F capacitor from Pin 2of IC

1to ground; and connecting Pin 2

of IC1

to pins 3 and 5 of IC2and Pin 2 of

IC3. Figure 3 shows the frequency re-

sponse of the circuit in Figure 2 with

unity gain and three digital bandwidth-control inputs.

The frequency response of Figure 2s circuit shows unity gain

and three digital bandwidth-control inputs.

1 10 100

FREQUENCY (Hz)

BW2 BW1 BW0

BW2 BW1 BW0

0 0 1

BW2 BW1 BW0

1 0 0

1k 10k 100k

F igure 3

70

80

60

50

40

30

20

10

0

10

GAIN

(dB)



ideasdesign

Designing a high-voltage switch-ing power supply that can producea sustained arc can be challenging.

This compact and efficient design deliv-ers 1 kV at 20W and can withstand a con-tinuous arcing, or short-circuit, condi-tion (Figure 1). It uses standard, com-mercially available components. R

1sets

the LTC1871 switching-regulator con-troller for a nominal operating frequen-cy of 120 kHz. The circuit operates as a

discontinuous flyback structure, produc-ing 333V across C1. The diode/capacitor

charge-pump multiplier triples this volt-age to create 1000V at the output. Figure2 shows the switching waveforms.Whenthe primary switch, Q

1, is on, the output

rectifiers are reverse-biased, and energy isstored in the transformer, T

1. When Q

1

turns off, energy transfers to the second-ary winding, and C

2and C

3pump up the

output voltage through the rectifiers.Theprimary voltage goes high and is clamped

through the transformerand rectifier, D

1, by the

voltage across C1. The

transformer is well-cou-pled, so the leakage in-ductance creates littlevoltage spike.A small RCsnubber across the pri-mary winding damps theringing and reduces EMI(electromagnetic inter-

ference).For current-limit pro-tection, the circuitin Figure 1 containstwo active circuits andone passive element. Thevoltage across the cur-rent-sense resistor, R

2,

limits peak primary cur-rent to 7.5A. Q

2provides secondary-side

current limit. Notice the bump on theleading edge of the current ramp of Trace

2 in Figure 2. This bump coincides withthe positive excursion of the voltageacross R

3in Trace 4, which is the refresh

10

3

9

4

8

5

7

6

2

1112

1

Q2VN2222

Q1Si7456DP

D1

C2 C3

D2 D3 D4 D5

0.022 F500V

0.022 F500V

T1

0.022 F500V

C10.022 F500V

220 pF200V

331/4W

R31.5

0.022 F500V

0.01 F1500V

0.01 F1500V

1 kVOUT

6.8 nF

4.7 F

33k

12.4k

4.99M

4.99M

68.1k

12.4k

SENSE

VIN

INTVCC

GATE

GND

1

2

3

4

5

RUN

ITH

FB

FREQ

MODE

10

9

8

7

6

IC1LTC1871

100

R1220k

1 nF

10 F25V

10 F25V

10 F25V

VIN 9 TO 18V DC

WARNING: LETHAL VOLTAGE POTENTIALS!

R20.02

R4100

5W

NOTES:D1, D2, D3, D4, D5: MURS160.

T1: COPPER VP5-0155.

F igure 1

1-kV power supply produces a continuous arcRobert Sheehan, Linear Technology, Milpitas, CA

This circuit delivers 1 kV from a low-voltage input and can produce continuous arcing.

These are the switching waveforms for the circuit

in Figure 1. Channel 1is the primary-switch volt-

age at T1, Pin 12; Channel 2 is the primary-switch current into Q

1

drain (10A/division); Channel 3 is the secondary-switch voltage

at T1, Pin 2 (200V/division); Channel 4 is the voltage across R

3.

(Secondary-switch current=2V/1.5=1.33A/division.)

F igure 2



ideasdesign

current for C2

and C3.

When the circuit is over-loaded, this slug of cur-

rent becomes highenough to enhance Q2,

folding back the load cur-rent (Figure 3). A hardshort circuit results in rel-atively low power dissipa-tion.Omitting Q

2for the

secondary-side currentlimit results in substan-tially increased short-cir-cuit current and internalpower dissipation, resulting in failure ofthe primary switch Q

1. R

4provides a load

impedance for the power supply.This load helps to limit the peak-cur-rent stress in the multiplier capacitorsand diodes. Dont skimp on the powerrating for R

4, because dissipation during

a continuous arc can be substantial.Should R

4fail open, the feedback circuit

forces a full duty cycle with catastrophicresults. Too low a value for R

4can result

in charred circuits and hours of debug-

ging. (Yes, a hearty explosion elicits around of applause from the lab crew.)

Arcing is the most stressful condition,and the output capacitor constantlycharges and discharges (Figure 4). As afinal figure of merit, the circuit is effi-cient (Figure 5). The efficiency reaches87.3% at 12V input and a full load of20W and increases to 87.7% with anoverload of 24W.

So what is this circuit good for? A bat-tery-operated bug zapper,perhaps. And,

like raking a live wireacross a grounded file,this is a great tool for be-

fuddling the AM-radiolisteners on the produc-tion floor. The circuitprobably doesnt deliverenough energy for use asan ion generator for aplasma cutter, thoughone engineer I knew waswilling to give it a try. Aprevious version of thecircuit used a monolith-ic switcher, and with theright materials for ba-

nana jack and plug, cre-ated a bright orangeglow and enough heat toraise thoughts about thefire extinguisher (plentyof ozone, too). Id stayaway from using this cir-cuit as a cat trainer or anelectric fence. The cir-cuit does generate alethal voltage potential,and lawsuits can be quitecostly.Prototype this cir-

cuit at your own risk.

1000

800

600

400

200

00 0.01 0.02 0.03 0.04

VOUT

(V)

IOUT

(A)

12VIN

The circuit in Figure 1 has a foldback

current-limiting characteristic.

F igure 3

POUT

(W)

EFFICIENCY(%)

12VIN

90

85

80

75

70

65

600 5 10 15 20 25

The conversion efficiency of the

circuit in Figure 1 is well over 85%.

F igure 5

These waveforms represent the output

voltage of the circuit in Figure 1 when arcing occurs.

F igure 4


17/155www.edn.com February 19 , 2004 | ed n 83

ideasdesign


Figure 1 shows the propulsion sys-tem of an electric vehicle.It includesan electric motor, drive electronics,

a mechanical transmission, vehicle con-trol/power management, a charging sys-

tem, and a battery. The long-term per-formance of the electric vehicle dependson ensuring the electrical health ofthe battery and its charging system.The battery system in an electric or a hy-brid-electric car comprises a series con-nection of 75 to150 individual 2V cells.This series connection generates a po-tential voltage of 150 to 300V. The meas-urement of an individual cells terminalvoltage creates a testing dilemma. Thehigh electrical potential precludes the useof standard differential op amps con-

nected across each cell. The measurementof each cells voltage entails using aswitching network that interconnects anisolated or floating A/D converter be-tween the two terminals of each cell in thestring. A measurement method alsoneeds a switching system to sequence thisvoltmeter across each of the 150 cells.

The functional block diagram is an ex-ample of an electric cars battery system(Figure 2). The battery comprises a seriesconnection of 150 2V cells. This config-uration provides a combined potential of

300V. This high dc potential requires theuse of an isolated voltage-measurementsystem.A microcontroller-based isolatedvoltmeter and isolated switch controllerdo not provide this function. The cell-

measurement system comprises a switch-ing array of 151 of Fairchild Semicon-ductors (www.fairchildsemi.com) HSR-412 SSRs (solid-state relays), which pro-vide an off-state blocking voltage of 400V.Each relay is an SPST (single-pole, single-throw), NO (normally open), opticallyactivated switch. As little as 3 mA, or 5mW, of LED-drive current energize theserelays. This low turn-on power con-sumption eliminates the need for relay-driver ICs.

The first step in measuring the cells

potential is to connectthe isolated voltmeteracross each cell.A clos-er look at Figure 2 re-veals how to effect thisconnection. The inputto the isolated volt-meter connects to atwo-wire measure-ment bus. The termi-nals of this bus are des-ignated A and B. Thetest points across the

various battery cells aredesignated SSR(N) and

SSR(N1), where (N) is the cell numberyou are currently measuring. You makeCell 1s voltage measurement by closingSSR

1and SSR

2and leaving all the re-

maining 149 relays off, or open. Closure

of the two SSRs connects Cell 1s positivepotential to Node A of the absolute con-verter through the output of SSR

1, and

the cells negative potential to Node Bthrough SSR

2. You measure the second

cell in the stack by opening SSR1and clos-

ing SSR3

while SSR2

remains on (closed).This sequence connects Cell 2s positivepotential to Node B through the outputof SSR

2and the cells negative potential

to Node A through the output of SSR3.

The process then repeats until all cellshave been measured. At this time, the

CHARGING

300V,100A

BATTERY

VEHICLECONTROL

BRAKING

MOTORDRIVE

MOTOR TRANSMISSION

ACMAINS

OPERATOR

WHEEL

F igure 1

Solid-state relays simplifymonitoring electric-car battery voltageRobert Krause, Fairchild Semiconductor, San Jose, CA

The components of a typical electric vehicle include an electric motor, drive electronics, a mechani-

cal transmission, vehicle control/power management, a charging system, and a battery.

TABLE 1THE ALTERNATING POLARITY OF THE A ANDB NODES AS THE INDIVIDUAL CELLS ARE MEASURED

SSR on SSR onCell (positive cell (negative cell Voltage at Voltage atnumber terminal terminal) Point A Point B

1 1 2 1 2

2 2 3 2 1

3 3 4 1 2

4 4 5 2 1

5 5 6 1 2

* * * * *

* * * * *

148 148 149 1 2

149 149 150 2 1

150 150 151 1 2

Solid-state relays simplify

monitoring electric-car battery voltage ....83

Scheme provides high-side current sensing

for white-LED drivers ....................................86

Simple technique makes low-cost

pc-board shields ............................................86

Lowpass filter has

improved step response ..............................88

Fault-latch circuit

protects switchers ..........................................90

Publish your Design Idea in EDN. See theWhat s Up sect ion a t www.edn .com.


www.edn.com


18/155

voltmeter returns to Cell 1 andrestarts the process.

Table 1 shows the alternat-

ing polarity of A and B wires asthe cells are measured. Tomeasure the voltage of an in-dividual cell (N), SSR(N) andSSR(N1) are energized andall other SSRs are off, or open.The alternating polarity of themeasurement lines requires theaddition of an absolute-valueconverter between the bus linesand the microcontrollers ana-log-to-digital input. The mi-crocontroller controls the se-

quence of measurementevents. To measure a cell, themicrocontroller sends out adiscrete 8-bit digital addresscorresponding to the cell beingmeasured.This address goes toa decoding block composed of11 74HC154 multiplexers. Thedata is transmitted through anarray of eight channels of high-speed HCPL2631 optocou-plers. The optocouplers pro-vide the common-mode vol-

tage isolation between the300V battery voltage and thechassis ground. The dual-channel density of the HCPL-2631 optoisolator reducescomponent count in the blockto four. The system addressesthe individual cells every 3msec. This time is how long ittakes to turn on and turn offthe HSR412 SSR. A cell-voltage measurement takesplace 600sec after the cell has

been addressed. The SSRs turn-on timeis less than 500 sec, thus permitting a100-sec acquisition time for the micro-controllers 10-bit A/D converter. Thesum of the turn-on and -off times of anSSR times the number of cells measureddetermines the cycle time.When you usethe HSR412, the measurement time for150 cells is less than 450 msec.

When you measure an individual cell,the V(N)-to-V(N1) bus potential is ap-proximately 2V. This figure is the differ-ential-mode voltage. The V(N)-to-

V(N1) potential to chassis ground

ranges from 2 to 300V, depending on thecell under measurement. This 300Vcommon-mode voltage is well within the400V off-state blocking voltage of theHSR412. The switch-matrix-control cir-cuits must also be able to accommodatethis 300V common-mode voltage. TheSSR easily solves this problem. The LED-to-SSR switch isolation voltage is 4 kVrms, which is more than adequate for a300V system. The 300V common-modevoltage requires that an isolated dc/dcconverter powers the microcontroller.

The microcontroller records the absolute

value of the cell voltage and stores thisvalue and cell number in its onboardmemory. At the conclusion of an entiremeasurement cycle, the microcontrollerformats the data to comply with a stan-dard automotive serial-bus format. Anexample is CAN Bus. Once formatted,thedata routes to the vehicle-control com-puter via a bidirectional, optically isolat-ed link. This link uses two high-speedHCPL-0600 logic-compatible optocou-plers. Once that data is received and ac-knowledged, the measurement cycle can

repeat.

84 ed n | February 19 , 2004 www.edn.com

ideasdesign

SSR(N)

HSR412

SOLID-STATE-RELAY MATRIX

ISOLUTED VOLTMETER

SSR(N+1)

+

2VV

1

+

2VV

2

+

2VV3

+

2VV

148

+

2VV

149

+

2VV

150

_

+

_

+

ABSOLUTE CONVERTER BLOCK

A

B

ADC

MEMORY

I/O PORTS

CELLADDRESS

MICROCONTROLLER

5VISOLATED

POWER SUPPLY

EIGHT CHANNELS

HCPL2631

TWO CHANNELS

HCPL0600

11 TIMES74HC154

DECODING BLOCK

DATA CAN BUS

151

8 2

NOTE: N=CELL BEING MEASURED.

An SSR-based switch matrix allows you to measure individual cells in an electric cars battery.F igure 2


19/15586 ed n | February 19 , 2004 www.edn.com

ideasdesign

White LEDs find

wide use in back-lighting color-LCD

screens in most portabledevices, such as cel-lular phones,PDAs,and MP3 players. MultipleLEDs often connect in se-ries to ensure that the same

current flows through everyLED. To forward-bias theseLEDs,a voltage of 10 to 16Vcomes from an inductor-based boost regulator, suchas an SP6690. However,white LEDs are behind thedisplay, whereas boost reg-ulators are on the main pcboard, and it is important to minimizethe number of interconnects.You can ob-tain the best results if you implementhigh-side and differential-current sens-

ing. In this case,the boost regulators out-put looks like a high-voltage true currentsource. Of course, LEDs need to connectto ground at some point, but it is unim-portant where they connect. For exam-ple, the display itself can locally pick upground. This approach allows you to ef-

fect a single-wire connection.The sim-ple circuit in Figure 1 shows the imple-mentation of the idea.

R1

acts as a current-sense resistor. The

diode-connected Q2 level-shifts the volt-age at Node 1 and applies it to the baseof Q

1. These transistors come in one

package and provide closely matched VBE

voltage when they operate at the samecurrent. Because the V

BEvalues match, the

emitter of Q1

is at the same voltage as

Node 1. As a result, thevoltage across resistor R

2

matches the drop acrossR

1and produces Q

1emit-

ter current that equalsV

R1/R

2. This current

flows to Q1s collector

and creates a voltagedrop across R

3. The

boost-regulator SP6690regulates the voltageacross R

3at 1.22V, the

ICs internal referencevoltage. R

4provides cur-

rent bias for Q2. The val-

ue of R4allows the Q

1and

Q2

collector currents tomatch. You calculate the

value of R1

as follows: R1R

3(V

OUT

VINV

BE)/1.22, where V

OUTis the com-

bined LED forward voltage. The outputcurrent is I

OUT0.3A/R

1. The circuit in

Figure 1 sets IOUT at 20 mA, but you canadjust it by using a different R

1value.

Note that you could return R4

to ground,but it instead connects to V

IN. This con-

nection removes quiescent currentthrough the resistor and Q

1/Q

2when the

SP6690 is in shutdown mode.

Q1

VIN

R3

133k

1%

R2

33.2k

1%

R1

15

1%

R4

1M

Q2

MMDT3906

2.2 F

10 H

NODE 11

5

3

4

2

SW

VFB

GND

VIN

SP6690

2.7 TO 5.5V

SHDN

PWM

DIMMING

F igure 1

Scheme provides high-side current sensing

for white-LED driversDimitry Goder, Sipex Corp, San Jose, CA

This circuit provides high-side current sensing for driving a string of white LEDs.

Many pc-board assemblies requireshields to reduce susceptibility tointerference from electromagnet-

ic fields. A classic example is a radio re-ceiver, in which the front end usuallyneeds high isolation from the tuning syn-thesizer. Historically, shields for low-vol-ume or low-cost applications involvetrade-offs. You cant justify the cost of acustom-cast shield,and shields machinedfrom aluminum burn through money asfast as the end mills go dull.You can makea simple shield for just a few dollars by us-

ing commonly available die-cast alu-minum project boxes, such as those

from Hammond Manufacturing (www.hammondmfg.com). These boxes comein sizes from 22 in. to more than74 in. You turn the project boxinto a shield by sandwiching the pc boardbetween the top and the bottom of thebox, thus completely enclosing the sen-sitive circuitry.

The basic idea is to choose a box thatis big enough to fit the sensitive circuit-ry that you want to shield. Then, lay outthe circuit in such a way that you cansandwich the board between the cover

and the body of the project box. To havea continuous ground around the lip of

F igure 1

Simple technique makes low-cost pc-board shieldsSteve Hageman, Windsor, CA

You should place a ground track on the top and

the bottom of the pc board where the project-box shield sits.


20/15588 ed n | February 19 , 2004 www.edn.com

ideasdesign

the box, place a 1/8- to 1/4-in.-wide groundtrack all the way around the area wherethe box will sit on the top and the bot-

tom sides of the board. Then, addmounting holes in the corner so that youcan assemble the box around the pcboard and screw it together (Figure 1).To get signals into and out of the shieldon a multilayer board is easy: Just use theinner layers and go under the groundtrack. On a double-sided board, you canbreak the track for traces, orbetteryetyou can use a 0.25W resistor tobridge the track. The 0.25W-resistormethod serves two purposes. First, it al-lows a signal to get over the ground track

without cutting it. Second, it is a perfectplace to add impedance to the signal lineand hence obtain high-frequency filter-ing. This method can help to preventstray signals from getting into the sensi-tive circuitry you are trying to protect.

For both the methods mentioned, you

need to notch the boxs body with a millor file (Figure 2) to provide clearance tothe resistor or traces. Note,however,

that this notch acts as a waveguidefor RF signals, so keep the following inmind: The longest dimension of any gapshould be much less than one-quarter ofa wavelength at the highest frequency ofinterest. In high-performance shieldingwork, strive to keep the gaps below one-twentieth of a wavelength. If you want tofill upthe gap, you can buy conductivefoam or metal gaskets from 3M and WLGore (www.3m.com and www.gore.com); you can use these gaskets to fill inany gap to make it electrically smaller.

Likewise, any gaps in the box-to-pc-board contact as it sits on the groundtrack also act as waveguides. Dependingon the required frequency of operation,these gaps may or may not cause a loss ofshielding effectiveness (Reference 1).Asa side benefit, you can also use the shield

as a heat sink. By placing TO-220 regu-lators outside the box, you can attach theregulators heat sink to the enclosure.

Thus, you have not only a shield, but alsoa heat sink (Figure 2).

Reference

1. Ott, Henry, Noise-reduction tech-niques in electronic systems, Wiley-Inter-science, 1988, ISBN 0-471-85068-3.

F igure 2

You can mill small notches in the shield to pro-

vide signal access. As a side benefit, you can use

the shield as a heat sink for TO-220 regulators.

Acommon problem that arises whenyou design lowpass filters for signalconditioning is the filterseffect on the

systems time-domain response. Becausepushing the cutoff frequency lower slowsthe step response, the system may fail torecognize significant changes within a rea-sonable amount of time.The circuit in Fig-ure 1 accommodates lower cutoff fre-quencies without sacrificing the step-response time. A window comparatormonitors the delta (difference) betweenthe filters input and output. When the

delta exceeds50 mV, the filter increasesits slew rate by increasing the cutoff fre-quency by an order of magnitude. Theswitched-capacitor filter,IC

1,normally op-

erates as a self-clocked device. CapacitorsC

1and C

2set the cutoff frequency at 0.1

Hz, and other circuitry forms a dynamicwindow comparator. Transistorpairs Q

1-Q

2and Q

3-Q

4form a

complementary current mirror whoseoutput flows through R

2and R

3, creating

a delta of50 mV. Connecting the outputvoltage to the center tap of the two resis-

tors centers the delta on the output voltage.You therefore set the window comparators

upper threshold at VOUT50 mV and the

lower threshold at VOUT50 mV.

R4 and C3 provide lowpass-filtering tothe original input signal, producing a

312-Hz cutoff frequency that reducessensitivity to momentary glitches. The fil-

tered input drives the window compara-tors input. If that input is outside the

R1

33k

R510k

C5

0.1 F

C4

0.1 F

R2

430

C3

1 nF

C1

27 nF

C2

270 nF

R4

510k

R3

430

J1

BNC

IC1

IC2A

MAX966

Q2

2N3904

Q5

2N3904

Q1

2N3904

Q3

2N3906

Q4

2N3906

+

+

Vcc

Vcc

Vcc

IC2B

MAX966

Vcc

Vcc

6

5

31

1

2

8

4

2

2

7

7

COM

IN

GND

VDD

CLK

SHDN

OS

OUT

8

7

6

5

1

2

3

4

Vcc

MAX7409

J2

BNC1

2

F igure 1

Lowpass filter has improved step responseJohn Guy and Robert Nicoletti, Maxim Integrated Products, Sunnyvale, CA

This lowpass filter maintains a fast step response by dynamically adjusting its cutoff frequency.


21/155

50-mV window, comparator IC2A

orIC

2Basserts its output low. The low out-

put drives Q5into cutoff, causing its col-

lector to assume a high impedance. Be-cause Q5s collector no longer grounds

capacitor C2, the filters cutoff frequency

increases by a factor of 10. When the sys-tems output changes to within 50 mV ofthe input, the cutoff frequency throttlesback to its quiescent state. Figure 2s os-cilloscope photo shows the effect. Thetop trace is a step from 1.5 to 2.5V, themiddle trace is the output with opti-mization circuitry enabled, and the bot-

tom trace shows the filters unmodifiedresponse. The optimized response in-cludes a slight perturbation during the

cutoff-frequency transition, but is fivetimes faster than that of the unmodifiedcircuit. The circuit in Figure 1 is config-ured for low cutoff frequencies,butyou can rescale it for higher fre-quencies by changing C

1and C

2. You can

also modify R2

and R3for different win-

dow values,for which the delta equals theresistance multiplied by 115 A. Thecomparator must be an open-draintype.

www.edn.com

ideasdesign

These traces show the time-domain response for

the circuit in Figure 1 with optimization circuitry

(middle trace) and without it (bottom trace).

400 mSEC/DIV

2.5V

1.5V

F igure 2

Many power-supply designers liketo have a regulator latch off in theevent of an overcurrent situation or

other fault condition. Yet, many PWMcontrollers do not internally support thislatch-off function. Most do, however,have a power-good output and an enablefunction. The circuit in Figure 1 adds thatlatch-off capability at low cost in little ad-

ditional space.The design is based on theLMS33460, which is a power-supplymonitor in a tiny, five-lead SC-70 pack-age.You just need to combine it with a fewsmall passive parts,and the circuit is com-plete. When the Enable Input signal goeshigh, the voltage at the top of C

1rises

quickly to 5V. Because the output voltageis not yet alive, P

GOODstays low, charging

C1through R

1. Because the voltage on C

1

is zero at the instant of turn-on, Pin 5 ofIC

1pulls up to 5V and begins to drop at

a time constant that C1, R

1, and R

2deter-

mine.If the output does not reachits normal operating voltage be-fore the Pin 5 voltage drops to lessthan 3V, IC

1pulls its output low

and latches the regulator off.If, however, the output comes

into regulation before the latchtimes out, P

GOODgoes high and C

1

begins to discharge, raising the

voltage on Pin 5 and keeping thesupply enabled.R

2provides a cou-

ple of volts to IC1

to keep the ICalive in the event of a latch condi-tion,and D

1pulls down on the

PWMs Enable when the sys-tem-enable command switcheslow. C

1can be a small tantalum or

ceramic capacitor. If you use a ce-ramic unit, choose a good dielec-tric,such as X5R.Also,the 5V sup-plys rising in less than 1 msec orso may eliminate the Enable, and

the whole circuitsimply runs from the5V supply. Figure 2shows a normal start,and Figure 3 showsstart-up with the sec-ond output of a two-output regulatorshorted. In bothcases, the top trace isthe system-enablesignal, the second trace isIC

1s Pin 5, the third trace is

the PWM Enable at IC1s Pin4, and the bottom trace is the

regulators output voltage. You can see inFigure 3 that IC

1s Pin 5 decays to 3V, at

which point it pulls the PWM Enable low,latching off the regulator.

PWM

ENABLEINPUT

IC1

LMS33460MG

PGOOD

ENABLE

4

VOUTVIN

5

2 3

DI

1N4148

R23k

R1

1k

C1

22 F

F igure 1

Fault-latch circuit protects switchersCraig Varga, National Semiconductor, Phoenix, AZ

This circuit adds a latch-off function to PWM controllers lack-ing this feature.

These traces represent start-up with

the second output of a two-output

regulator shorted.

This circuit shows a normal start-up

sequence for the circuit in Figure 1.

90 ed n | February 19 , 2004

F igure 2

F igure 3

5 mSEC5V

1

5 mSEC5V

2

5 mSEC2V

3

5 mSEC2V

4

5 mSEC5V

1

5 mSEC5V

2

5 mSEC2V

3

5 mSEC2V

4

5 mSEC BWL1 0.5V DCX102 0.5V DCX103 0.5V DCX104 0.5V DCX10

2 DC 2.4V

1 mSEC/SEC

STOPPED

2 DC 2.4V

1 mSEC/SEC

NORMAL

5 mSEC BWL1 0.5V DC102 0.5V DC103 0.5V DC104 0.5V DC10


22/155www.edn.com M arch 4 , 2004 | ed n 69

ideasdesign


As Moores Law plunges us into therealm of multigigahertz processorsand PCs with gigabytes of RAM, en-

gineers face the task of removing theheat that these state-of-the-art compo-nents produce. Cooling such systems

poses a dilemma.If you optimize the fansize and speed for nominal operating

conditions, the system is susceptible tofailure when conditions deteriorate. If,on the other hand, you select the fan tomaintain acceptable operating temper-atures under worst-case conditions, thefan may produce an annoying level of

sound. Controlling fan speed is the ob-vious solution. If the system includes asystem-management bus, you can addone of the many available sophis-ticated ICs for controlling fanspeed. But if such a bus is unavailable,you need a stand-alone fan-speed con-troller (Figure 1).

Power comes from the 12V supply,and a dc/dc converter, IC

1, steps down

the input voltage to an intermediate volt-age for powering the fan. The transferfunction of this voltage is a function of

resistors R1 and R2 and thermistor RT1.The thermistor is an NTC (negative-temperature-coefficient) type, so theoutput voltage increases with increasingtemperature. The output voltage is ap-proximately 5.5V at room temperature

and increases to 12V at approximately47C (Figure 2). You can easily select theratio of resistors R

1, R

2, and RT

1by us-

ing a spreadsheet. Note that thermistormanufacturers tables of resistance ratioversus temperature are easier to use than

are the cumbersome equations for ther-mistor resistance.

Because the circuit in Figure 1 does notmonitor fan speed or current, it includesR

3, C

1, and D

1to ensure that the fan starts

turning during start-up. The time con-

1234

12

345678

1615

14131211109

12V

39 F16V

OSCON180 FOSCON

16V

0.1F

0.1F 1F 0.1F

100F

0.01F

15 pF

33HDT3316

+

+

+

ALUMINUMELECTROLYTIC

12V

R315k

D11N4148

IC1MAX1685

CVHAIN

INCVLAGNDREFFBCC

PGNDSHDN

LXLX

BOOTSTBYILIM

SYNC

L1

R127k

R247k

MBRS130

10kNTC

0.1F

123

BEAD

0.1F

1

23

BEAD

0.1F

123

BEAD

0.1F

123

BEADC1

6V

RT1

F igure 1

Circuit provides efficient fan-speed controlJohn Guy, Maxim Integrated Products, Sunnyvale, CA

To control fan speed, thermistor RT1

adjusts the output voltage of this dc/dc converter.

Circuit provides

efficient fan-speed control ..........................69

Simple circuit forms

multichannel temperature monitor ..........70

PWM controller drives LEDs

from high-voltage lines ................................72

Circuit forms satellite-dish

command decoder ........................................72

Use a microcontroller

to design a boost converter ........................74

Publish your Design Idea in EDN. See theWhat s Up sect ion a t www.edn. com.

OUTPUT

VOLTAGE

(V)

TEMPERATURE (C)

14

12

10

8

6

425 30 35 40 45 50 55 60

Output voltage for the circuit in

Figure 1 varies with temperature.

F igure 2


www.edn.com


23/15570 ed n | M arch 4, 2004 www.edn.com

ideasdesign

stant of R3

and C1

serves that purpose bycausing IC

1s output to overshoot during

the first few seconds of operation. After

the fan starts, it easily sustains rotationat the lower operating voltages. An im-

portant criterion in selecting a dc/dc con-verter is the ability to operate at 100%duty cycle. IC

1satisfies that requirement

and offers the convenience of an internalpower MOSFET. IC1

supplies as much as

1A output current, which is enough todrive one to four standard fans. As anadded benefit, its high efficiency helps to

minimize the heat that the circuit re-moves.

Y

ou can use an ADT7461 single-channel temperature monitor, an

ADG708 low-voltage, low-leakageCMOS 8-to-1 multiplexer, and threestandard 2N3906 pnp transistors tomeasure the temperatures of three sepa-rate remote thermal zones (Figure 1).Multiplexers have an inherent-resistanceon-resistance; the channel matching andflatness of this resistance normally resultsin a varying temperature offset. TheADT7461 temperature monitor inthis system can automatically can-cel resistances in series with the externaltemperature sensors. The resulting sys-

tem is a multichannel temperature mon-itor. The resistance is automatically can-celled, so on-resistance flatness andchannel-to-channel variations have noeffect. Resistance associated with the pc-board tracks and connectors is also can-celled, thus allowing you to place the re-mote temperature sensors some distancefrom the ADT7461. The system requiresno user calibration; therefore, you canconnect the ADT7461 directly to themultiplexer.

The ADT7461 digital

temperature monitor canmeasure the temperatureof an external sensor with1C accuracy. The re-mote sensor can be a sub-strate-based or discretetransistor and normallyconnects to the D andD pins on the ADT-7461. In addition to theremote-sensor-measure-ment channel, theADT7561 has an on-

chip sensor. The diode-connected transistors with

their emitters connected together con-nect to the D input of the ADT7461,and each of the base-collector junctionsconnects to a separate multiplexer input(S1 to S3). You effect the connection ofthe selected remote transistor to the Dinput by addressing the multiplexer,which is digitally controlled by addressbits, A2, A1, and A0. The ADT7461 thenmeasures the temperature of whichevertransistor connects through the multi-plexer.

The ADT7461 measures the tempera-ture of the selected sensor without inter-ference from the other transistors. Figure2 shows the results of measuring the tem-perature of three remote temperaturesensors. The sensor at address 000 is atroom temperature, the sensor at address001 is at a low temperature, and the sen-sor at address 010 is at a high tempera-ture. When you select no external sensor,the open-circuit flag in the ADT7461register activates, and the Alert interrupt

output asserts. You can

expand the system to in-clude as many externaltemperature sensors asyou require. The limitingfactor on the number ofexternal sensors is thetime available to measureall temperature sensors. Ifyou require two-wire seri-al control of the multi-plexer, you can use anADG728 in place of theADG708.

2N39062N39062N3906

ADG708

S1

S2

S3

S4

D

A2 A1 A0

MULTIPLEXER CONTROL

D+ ALERT

SDA

SCL

D

TO HOST

TO HOST

VCC

ADT7461

F igure 1

Simple circuit formsmultichannel temperature monitorSusan Pratt, Analog Devices, Limerick, Ireland

This system measures the temperatures of three remote thermal zones.

1 18 35 52 171 188 205 222 239 256 273 290

200

150

100

50

0

50

100

TEMPERATURE

(C)

ADDRESS =000

ADDRESS =001

ADDRESS =010

ADDRESS CHANGED HERE

REMOTE TEMPERATURE LOCAL TEMPERATURE

69 86 103 120 137 154

The ADT7461 measures the temperature of the selected sensor

without interference from the other transistors with these results for ambient-,hot-, and cold-temperature measurements.

F igure 2


24/15572 ed n | M arch 4 , 2004 www.edn.com

ideasdesign

By decoding the commands sentby a direct-broadcast satellite re-ceiver that uses the DISEQC (digi-

tal-satellite-equipment-control) proto-col, you can troubleshoot the com-

mands or simply listen in. Eutelsat Corp(www.eutelsat.com) offers the DISEQC

protocol. The technique uses only thecoaxial cable between the receiver andthe dish to send commands for actionssuch as changing the low-noise-blockfrequency range or switching between

dishes for multisatellite reception. TheDISEQC protocol specifies a bit time of

1.5 msec and bit values as shown in Fig-ure 1, the timing diagram of bit modu-lation on the coaxial cable. The signalsac portion is a 22-Hz burst whose am-plitude ranges from 300 to 600 mV. A

voltage-doubler circuit detects the 22-Hz portion, producing a pulse stream in

Circuit forms satellite-dish command decoderMark Giebler, Oakdale, MN

Powering LEDs from a widedc rangesay, 30 to 380Vwithout wasting a lot of

power in the regulating block, isa difficult task when theLED current needs to beconstant. Dedicated LED driversare available,but they usually im-plement boost structures and arethus inadequate for high-voltageinputs. The NCP1200A, a high-voltage controller from On Semi-

conductor (www.onsemi.com),can serve as a constant-currentgenerator if you add a simple coilin series with a power MOSFET.If you insert diodes between thecoil and the MOSFET, the circuitbecomes an economical lightgenerator. Furthermore, there isno need for a transformer or any kind ofexternal supply, because the controller di-rectly connects to the rectified high volt-age and thus supplies itself (Figure 1).

The circuit forces a current to build up

in the L1 coil and the LEDs until the volt-age developed across R

3reaches V

FB/3.3V.

At this point, power switch Q1

turns off,and the magnetizing current keeps circu-lating in the coil and LEDs,thanks to free-wheeling diode D

1. To maintain a clean

current in the LEDs, L1

must be largeenough to keep the ripple

EDN Design Ideas 2004

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