EDN Design Ideas 2006

142
Applications ranging from fre- quency counting and synthesis to sensor signal conditioning require conversion of RF signals to digital-logic levels. In such situations, designers typ- ically use a high-speed voltage com- parator to perform the RF-to-digital conversion. Due to their high gain, voltage comparators typically exhibit good sensitivity but also present some drawbacks. High-speed comparators are expensive, difficult to find off the shelf, and prone to rapid obsolescence. For frequencies as high as 180 MHz, the circuit in Figure 1 offers an attrac- tive approach. The IC in the design, a 74LVCU04 very-high-speed CMOS hex inverter, is available off the shelf and from many sources. Furthermore, many applications may already include three unused inverters. A single in- verter, IC 1A , operating as a linear pre- amplifier, forms the converter’s input stage. Biasing resistor R 3 forces the inverter into its linear region by equal- izing its input and output voltages at one-half of the power-supply voltage, V O1 V I1 (V DD /2). Because the ac gain of a very-high-speed CMOS inverter is relatively low at RF (V O1 / V I1 )7, addi- tional gain stages follow the preampli- fier. One self-evident approach—a cas- cade of additional inverters—presents poor stability at low frequencies and at dc when no RF source is present. The circuit in Figure 1 eliminates this drawback thanks to a topology based on a Schmitt trigger and ampli- fier circuit, IC 1B and IC 1C , that includes a frequency-dependent positive-feed- back network comprising R 1 , R 2 , C D1 , and C D2 . Depending on the input fre- quency, the network exhibits two behaviors: At high frequencies, the decoupling-capacitor pair, C DC1 and C DC2 , short-circuits feedback resistor R 1 , canceling the time constant intro- duced by the positive-feedback net- work, R 1 and R 2 , and the input capac- itance of inverter IC 1B . Consequently, at high frequencies, the three inverters, IC 1A , IC 1B , and IC 1C , behave as three cascaded, high-speed amplifiers that allow the best performance in input- signal bandwidth. At dc and low fre- quencies, the influence of coupling- capacitor pairs C D1 and C D2 is negligi- ble, and inverters IC 1B and IC 1C and the positive-feedback network, R 1 and R 2 , act as a Schmitt-trigger circuit. The choice of the high- and low-threshold voltages, V TH and V TL , at the Schmitt READERS SOLVE DESIGN PROBLEMS CMOS inverters convert RF to digital signal EDITED BY BRAD THOMPSON AND FRAN GRANVILLE design ideas Figure 1 Three high-speed CMOS inverters and a few passive components form an RF-to-logic converter. Francis Rodes, Eliane Garnier, and Guillaume Zingone, ENSEIRB, Talence, France JANUARY 5, 2006 | EDN 79 RF SOURCE 50 NOTE: ALL COMPONENTS ARE SURFACE-MOUNTED DEVICES. V S V I1 V O1 C D1 680 pF C D1 680 pF C 1 3.6 pF C DC2 10 nF V DD 3.3V I DD C DC1 680 pF R 1 5.6k R 3 56k R 2 56k C D2 10 nF C D2 10 nF IC 1A 74LVCU04AD IC 1B 74LVCU04AD IC 1C 74LVCU04AD L 1 100 nH DATA OUT DIs Inside 82 Instrumentation amplifier extends DSO 84 Virtual instrument determines magnetic core’s B-H-loop charac- teristics What are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to edndesignideas@ reedbusiness.com.

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Collector of EDN Design Ideas 2006

Transcript of EDN Design Ideas 2006

Applications ranging from fre-quency counting and synthesis

to sensor signal conditioning requireconversion of RF signals to digital-logiclevels. In such situations, designers typ-ically use a high-speed voltage com-parator to perform the RF-to-digitalconversion. Due to their high gain,voltage comparators typically exhibitgood sensitivity but also present somedrawbacks. High-speed comparators areexpensive, difficult to find off the shelf,and prone to rapid obsolescence.

For frequencies as high as 180 MHz,the circuit in Figure 1 offers an attrac-tive approach. The IC in the design, a74LVCU04 very-high-speed CMOShex inverter, is available off the shelfand from many sources. Furthermore,many applications may already includethree unused inverters. A single in-verter, IC1A, operating as a linear pre-amplifier, forms the converter’s input

stage. Biasing resistor R3 forces theinverter into its linear region by equal-izing its input and output voltages atone-half of the power-supply voltage,VO1VI1(VDD/2). Because the ac gainof a very-high-speed CMOS inverter isrelatively low at RF (VO1/ VI1)7, addi-tional gain stages follow the preampli-fier. One self-evident approach—a cas-cade of additional inverters—presentspoor stability at low frequencies and atdc when no RF source is present.

The circuit in Figure 1 eliminatesthis drawback thanks to a topologybased on a Schmitt trigger and ampli-fier circuit, IC1B and IC1C, that includesa frequency-dependent positive-feed-back network comprising R1, R2, CD1,and CD2. Depending on the input fre-quency, the network exhibits twobehaviors: At high frequencies, thedecoupling-capacitor pair, CDC1 andCDC2, short-circuits feedback resistor

R1, canceling the time constant intro-duced by the positive-feedback net-work, R1 and R2, and the input capac-itance of inverter IC1B. Consequently,at high frequencies, the three inverters,IC1A, IC1B, and IC1C, behave as threecascaded, high-speed amplifiers thatallow the best performance in input-signal bandwidth. At dc and low fre-quencies, the influence of coupling-capacitor pairs CD1 and CD2 is negligi-ble, and inverters IC1B and IC1C and thepositive-feedback network, R1and R2,act as a Schmitt-trigger circuit. Thechoice of the high- and low-thresholdvoltages, VTH and VTL, at the Schmitt

READERS SOLVE DESIGN PROBLEMS

CMOS inverters convert RF to digital signal

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

Figure 1 Three high-speed CMOS inverters and a few passive components form an RF-to-logic converter.

Francis Rodes, Eliane Garnier, and Guillaume Zingone, ENSEIRB, Talence, France

JANUARY 5, 2006 | EDN 79

RFSOURCE

50

NOTE:ALL COMPONENTS ARE SURFACE-MOUNTED DEVICES.

VS VI1 VO1

CD1680 pF

CD1680 pF

C13.6 pF

CDC210 nF

VDD3.3V

IDD

CDC1680 pF

R15.6k

R356k

R256k

CD210 nF

CD210 nF

IC1A74LVCU04AD

IC1B74LVCU04AD

IC1C74LVCU04AD

L1100 nH

DATAOUT

D Is Inside82 Instrumentation amplifierextends DSO

84 Virtual instrument determinesmagnetic core’s B-H-loop charac-teristics

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

trigger’s input, VO1, stems from a com-promise between input sensitivity at VSand ensuring unconditional stability ofthe comparator’s output. Equations 1and 2 set the high and low thresholdvoltages, respectively:

To counteract a roll-off of sensitivi-ty at higher frequencies, add a low-Qimpedance-matching network com-prising L1 and C1 at the comparator’sinput. Given the design objective ofobtaining acceptable sensitivity at fre-quencies as high as 160 MHz, the net-work matches the 50 RF source andIC1A’s input impedance, ZI1, at 150MHz. Unfortunately, manufacturers ofdigital ICs typically do not specify logicdevices’ input impedances. Whendesigning the matching network, thefirst task involves using an Agilent(www.agilent.com) vector-networkanalyzer to measure the first inverter’sinput scattering parameter, S11, atIC1A’s input, VI1. Figure 2 shows aSmith-chart plot of the inverter’s S11parameter.

Knowing that

with ZC50, you can use the data inFigure 2 to extract the first inverter’sinput impedance at the frequency ofinterest. At 150 MHz, this yields ZI1=106.1j 116.7 (at Marker 4 in Fig-ure 2). To determine values for thematching network’s components, youcan use any of several software tools(references 1 and 2). If you are unfa-miliar with Smith-chart computa-tions, you can also proceed analytical-ly with the following method:

1. Use series-to-parallel transforma-tion formulas (equations 4 and 5) totransform the first inverter’s inputimpedance into a parallel form:

Applying these formulas at 150 MHzyields: RP233, and XP213.(At 150 MHz, XP represents an inputcapacitance, CP5 pF.)

2. Compute an initial version of thematching network to perform a matchbetween the real part of the first invert-

er’s input impedance, RP, and the 50RF source. Solving equations 6 and 7yields values for the matching network’selements (Reference 3):

designideas

Figure 3 An input-level-versus-frequency plot of the RF-to-digital comparatormeasured from the RF source’s reference plane to a clean logic outputreveals less-than-100-mV sensitivity at 160 MHz and usable output to 200MHz.

80 EDN | JANUARY 5, 2006

Figure 2 An Agilent N3382A vector-network analyzer obtained this S-param-eter plot, which shows S11 measured at the first inverter’s input for a sourcepower level of 6 dBm.

0

50

100

150

200

250

10 20 40 60 80 100 120 140 150 160 170 180 190 200

FREQUENCY (MHz)

INPUTVOLTAGE(mV RMS)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

To determine the specificationsof a solar-generating plant, I

needed to accurately measure the loadcurrent a product consumed. The prod-uct switched several internal devices onand off during an interval of several sec-

onds. An ammeter showed that the cur-rent transitions occurred too quickly forvisual logging, and my managers hadrequested an oscilloscope photo of thecurrent waveform’s peaks. I rolled outour company’s cart-mounted DSO (dig-

ital-storage oscilloscope), inserted alow-value resistor in series with theproduct’s positive-power-supply input,and attempted to make a differential-voltage measurement (Channel Aminus Channel B) across the current-sampling resistor.

Unfortunately, RF noise from a localFM-broadcast station swamped thesmall-load-induced fluctuations in thevoltage developed across the samplingresistor, and increasing its resistance

Applying these formulas at 150 MHzyields L1100 nH, and C1 CP 8.7pF.

3. Subtract the inverter’s inputcapacitance, CP 5 pF, from Equation7 to calculate a value for C1:

To build the circuit, use standardcomponent values that fall closest to

the computed values: L1100 nH, andC13.6 pF. As the plot of input fre-quency versus sensitivity in Figure 3shows, the circuit’s increased sensitiv-ity for 100- to 170-MHz frequenciesclearly demonstrates the impedance-matching network’s effectiveness. Youcan optimize the circuit’s sensitivity inany other frequency band of interest byapplying this method at the chosen fre-quency. The RF-to-digital-logic con-verter’s power consumption does notchange significantly for input signals of

10 to 180 MHz. Under worst-case con-ditions, the current drain does notexceed 58 mA for a supply voltage of3.3V.EDN

R E F E R E N C E SSmith tool, Ansoft Corp,

www.ansoft.com.Ansoft Designer: Student Version,

Ansoft Corp, www.ansoft.com.Bowick, Chris, RF Circuit Design,

HW Sams & Co, Indianapolis, IN,1988.

Instrumentation amplifier extends DSO

designideas

Figure 1 Improve your oscilloscope’s performance in high-RF-noise environments by adding an instrumentation-amplifierfront end. For best results, package the circuitry in a metal enclosure.

82 EDN | JANUARY 5, 2006

+

BENCHTOPPOWERSUPPLY

NC

TRIM

OFF/ON

12VDC OUT

VINVIN

GND

COM

C4100 nF

C5100 nF

C6100 nF

C2100 nF

+ C710 F

C810 nF

C9100 nF

C101 F

C1110 F

R2475

R4121

R3121

R515k

+

+

+

+

+C15

10 F

C12100 pF

C13100 pF

C14100 nF

C161 F

C17100 nF

C3150 F

C1150 F

+

C1810 F

C19100 nF

F1

R125

NC

UNIT UNDERTEST (UUT)

RG-174COAXIALCABLE

_

+ TOLECROY

DSO

TO 15VISOLATED

TO 15VISOLATED

15VISOLATED

15VISOLATED

IC2

RG

V+

V

IC1

RG

REF

Bob Perrin, Sacramento, CA

1

2

3

(8)

To design an inductive compo-nent that contains a magnetic-

core material, an engineer must accu-rately measure the material’s charac-teristics. A magnetic core’s dynamichysteresis loop, or “B-H curve,” con-tains valuable information about corelosses and other magnetic parameters.Unfortunately, commercially availablemagnetic-loop-analysis instrumentsare expensive and thus impractical forsmall-scale research labs and manufac-turers. This Design Idea describes a vir-tual instrument that uses a desktop ornotebook computer with an analogdata-acquisition card and NationalInstruments’ (www.ni.com) LabViewsoftware (Version 7.1 or above). Inoperation, the software extracts B-H-loop information, core losses, and othermagnetic parameters at a reasonablecost per measurement.

Figure 1 shows the test fixture for amagnetic-core-based device. The de-vice, T1, comprises a sample of corematerial and two windings with equal

numbers of turns. A precision current-sensing resistor, R1, samples the exci-tation current that induces a magnet-ic field in the core. The voltage dropacross R1 is proportional to the excita-tion current and the magnetic field, H.A network comprising resistor R2 andcapacitor C1 integrates the voltageinduced in the secondary winding. Thevoltage across C1 is directly propor-tional to the flux density, B, in the core.In practice, R2’s value should be muchlarger than capacitor C1’s impedance atthe operating frequency. (Textbook

descriptions of the circuit suggest a ratioof 100-to-1.)

Components’ tolerances and charac-teristics affect measurement accuracy.Use a noninductive, 1, 1%-toleranceresistor of appropriate wattage rating for R1, and select a low-leakage, low-dielectric-absorption, polyester- orpolypropylene-film capacitor withtight tolerance for C1. To acquire andview the data, you can use a dedicatedvirtual instrument using a NationalInstruments PCI-6024E data-acquisi-tion card and LabView. The softwarefeatures NI’s Express VI (virtual-instrument) technology that greatlysimplifies the creation of user-designeddata-acquisition and -manipulationfeatures. This application uses only two

introduced an unwanted voltage dropon the product’s power-supply rail.Finally, the 12V supply rail introduceda voltage offset that limited the oscil-loscope’s ability to accurately resolvethe small differential signal that I wasattempting to measure. I disconnectedthe oscilloscope’s ac ground to “float”the scope with respect to the samplingresistor, but the RF noise visible on thetrace increased significantly. I brieflyconsidered using an older analog (non-storage) scope, but the DSO’s storagefeature would allow me to capture andprint the waveforms required for myreport.

In frustration, I scoured the work-bench for stray parts and assembled acircuit that solved the problem. Bychance, the parts collection includedan instrumentation amplifier, IC1,which does an excellent job of extract-

ing small signals from high-frequencybackground noise. The amplifier’sinherently slow response attenuates RFnoise but doesn’t affect amplification oflower frequency signals. Adding RClowpass filters to the amplifier’s inputsand output further attenuates lower fre-quency noise induced by nearbyswitched-mode power supplies and dig-ital logic or microprocessors.

Normally, I avoid using noise-emitting dc/dc converters as power supplies for analog circuits. However, in this case, IC2, a dc/dc converter, provided an expedient and technical-ly sound approach (Figure 1). In gen-eral, dc/dc converters produce morenoise as their load currents increase,but, in this circuit, the sole load com-prises the instrumentation amplifierthat draws only a few milliamperes.Adding a few filtering components

provided additional noise suppression.Under normal operation, the current

that the product draws fluctuates fromapproximately 300 to 800 mA. To min-imize the voltage drop induced in thepower-supply loop, I used a 520-mm,10A, 250V fuse, F1, as a current-sam-pling resistor. Voltage drop across thefuse is approximately 1 mV per 100 mAof current, and operating the fuse at asmall fraction of its nominal ratingavoids introducing nonlinearities in themeasurement.

With a 475 gain-setting resistor, R2,the instrumentation amplifier, anAnalog Devices (www.analog.com)AD620, provides a gain of 105V/V anddelivers an output of approximately 1V,which corresponds to 1A of currentflowing through the shunt. CapacitorsC12 and C13 provide low-impedancepaths for high-frequency noise.EDN

Virtual instrument determines magnetic core’s B-H-loop characteristics

designideas

Michael Nasab, Circuit Mentor, Boulder Creek, CA

Figure 1 The test fixture for a basic hysteresis-loop analyzer requires fewcomponents.

84 EDN | JANUARY 5, 2006

VACVARIABLE-VOLTAGE

SINUSOIDAL AC-EXCITATION SOURCE

TO DATA-ACQUISITIONCHANNEL 0 (X-AXIS)

INPUT

R1

T1

C1

R2

1-TO-1 TURNSRATIO

TO DATA-ACQUISITIONCHANNEL 1 (Y-AXIS)

INPUT

data-acquisition analog-input chan-nels: Channel 0 acquires magnetic-fieldreadings (H) for display on an x-ychart’s x axis in units of ampere-turnsper meter, and Channel 1 captures fluxdensity (B) in tesla units for the y-axisdisplay.

At low frequencies, the core’s hys-teresis losses predominate, whereaseddy-current losses become moreapparent at higher frequencies. Awattmeter-style algorithm calculatescore losses, but you can easily substituteyour own mathematical expression intothe VI block diagram’s formula node.LabView also can save the data andexport results in Microsoft’s (www.microsoft.com) Excel-spreadsheet for-mat or into other programs for furtheranalysis.

You can use another of the data-acquisition card’s eight differential ana-log-input channels to determineinductance. To do so, measure the volt-age across the device’s primary windingand calculate its rms value. The ratioof the voltage to the rms current asmeasured through R1 determines themagnitude of the winding’s scalarimpedance, XL. Then, you can calcu-late the inductance from the followingequation: LXL/2f, where f denotes

the frequency of the applied excitationvoltage.

Figure 2 shows a hysteresis curve fora 3B7-mixture ferrite-pot core preparedwith 100-turn primary and secondarywindings and measured at 60 Hz. Forcomparison, Figure 3 displays the 60-Hz hysteresis curve for a 100W powertransformer wound on a toroidal corecomposed of grain-oriented steel. Thetoroidal core’s wider loop indicatesgreater hysteresis, a characteristic thatsaturable-core power inverters exploit.To apply 60-Hz excitation, you candrive the device’s primary winding froma stepdown (isolation) transformerpowered by an adjustable-output auto-transformer, such as a GenRad (www.ietlabs.com) Variac. While observingthe B-H curve display, graduallyincrease the primary voltage until theflattening of the hysteresis loop’s upperand lower portions indicates core sat-uration. No calibration is necessary ifyou use precision. However, when eval-uating core materials, you may need toexperiment with different numbers ofturns to obtain the windings’ ampere-turns value for optimum results.

For tests at 60 Hz, use a 267-k, 1%-tolerance resistor for R2 and a 1-Fpolyester-dielectric capacitor for C1 in

the integrator network. Depending onthe number of turns and the currentnecessary to obtain a usable outputvoltage, a few volts of ac excitation isusually sufficient to run the test. Forcore measurements at higher frequen-cies, use a signal generator connectedto a power amplifier and alter the RCintegrator’s component values forproper operation at the frequency ofinterest. Although the application doesnot use an analog output from the data-acquisition card, this output can serveas a sinusoidal-signal source for thepower amplifier.

Review the electrical specificationsof the card you plan to use and avoidexceeding the card’s peak-to-peak dif-ferential- and common-mode inputvoltages. If the excitation voltageapproaches or exceeds the card’s rat-ings, add a 10-to-1 resistive-voltagedivider to limit the applied voltage andcompensate for the attenuator’s lossesby adding a factor-of-10 gain multipli-er in the software.

You can download a copy of the VIthat this Design Idea describes fromwww.circuitmentor.com/services.htm.You can also obtain a trial version ofLabView from NI’s Web site at www.ni.com.EDN

designideas

Figure 3 This grain-oriented-steel toroidal core’s B-Hloop exhibits saturation at a lower excitation value thanthe core in Figure 2.

86 EDN | JANUARY 5, 2006

Figure 2 The virtual instrument’s display shows a 3B7-mixture ferrite-pot core’s B-H loop.

Programmable-logic devices pro-vide a popular method of imple-

menting complex functions in digitaldesigns. Although manufacturers don’tyet offer analog circuits whose com-plexity compares to VLSI digital cir-cuits, field-programmable analog cir-cuits are enjoying extensive use in sig-nal-conditioning and filtering applica-tions. Based on CMOS-operational-transconductance and switched-capa-citor amplifiers, these devices offer aconvenient approach to relativelycomplex design problems. LatticeSemiconductor’s (www.latticesemi.com) ispPAC10 in-system-program-mable analog circuit and its accompa-nying PAC Designer software offer aconvenient method of circuit design

and verification (Reference 1). ThisDesign Idea presents two simple sinu-soidal oscillators based on the isp-PAC10.

Resistors within the ispPAC10 arefixed at a nominal 250 k, and allcapacitors are user-selectable from1.07 to 61.59 pF. Figure 1 shows an isp-PAC10 with its internal blocks 1, 2,and 4 connected as a cascade of threefirst-order lowpass filters to form a clas-sic phase-shift RC oscillator. Alteringthe capacitors’ values produces oscilla-tion frequencies over a range of 18 to130 kHz. Each PAC block’s gain is fixedat a factor of two to obtain a loop gainof 8, which Barkhausen’s conditionfor oscillation requires (Reference 2).Configured from Block 3, a first-order

lowpass filter reduces the THD (totalharmonic distortion) on the oscillator’soutput. The values of capacitors inBlock 3 are optimized for filtering per-formance and thus differ from those ofthe phase-shift stages.

The circuit in Figure 2 describes atwo-integrator loop that forms a clas-sic quadrature-RC oscillator. The cir-cuit’s oscillation frequency spans 12 to126 kHz and depends on the time con-

READERS SOLVE DESIGN PROBLEMS

D Is Inside80 Enhanced, three-phase VCOfeatures ground-referenced outputs

84 Improved current monitor deliv-ers proportional-voltage output

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

Figure 1 Based on a Lattice Semiconductor ispPAC10 programmable analog circuit, this phase-shift sine-wave oscilla-tor and lowpass filter require no external components. The values are for a 30.4-kHz oscillator.

Stefano Salvatori and Paolo Lorenzi, University of Rome, Rome, Italy

JANUARY 19, 2006 | EDN 77

Programmable analog circuits yield single-chip sinusoidal oscillators

IA1

IA2

2

1

OA1

2.5V

36.05 pF

IA3

IA4

2

1

OA2

2.5V

36.05 pF

OUT1

OUT2

PAC BLOCK 1

PAC BLOCK 2

IN1

IN2

IA5

IA6

2

1

OA3

36.05 pF

IA7

IA8

2

1

OA4

2.5V

2.5V

20.91 pF

OUT4

OUT3

PAC BLOCK 3

PAC BLOCK 4

IN3

IN4

UES BITS=00000000.

stants of the integrators that blocks 1and 2 form. In theory, each integrator’sgain should have an absolute value ofunity, but, in practice, ispPAC allowsspecification only of inverting inte-grators, and producing a stable sinu-soidal signal requires a gain of at least

4 in Block 1. The circuit uses a gainof 10. Two additional blocks of theispPAC10 device form a second-orderlowpass filter that decreases the out-put’s THD. In both oscillator circuits,you can alter the lowpass filters’ gainso that the circuit’s outputs deliver

specific voltages, such as 1V p-p, at allfrequencies.

Tables 1 and 2, respectively, containsummaries of the phase-shift andquadrature oscillators’ componentsand output characteristics. CN refers tothe value of the capacitor used in the

designideas

78 EDN | JANUARY 19, 2006

Figure 2 Cascaded dual integrators implement a quadrature sine-wave oscillator, with blocks 3 and 4 forming a low-pass filter. Again, the circuit design uses no external components. The values shown are for a 27.2-kHz oscillator.

IA1

IA2

10

1

OA1

2.5V

25.08 pF

IA3

IA4

1

1

OA2

2.5V

25.08 pF

OUT1

OUT2

PAC BLOCK 1

PAC BLOCK 2

IN1

IN2

IA5

IA6

1

1

OA3

23.26 pF

IA7

IA8

2

1

OA4

2.5V

2.5V

23.26 pF

OUT4

OUT3

PAC BLOCK 3

PAC BLOCK 4

IN3

IN4

UES BITS=00000000.

TABLE 1 PHASE-SHIFT OSCILLATORC1 C2 C3 C4 f0 f (kHz) THD

(pF) (pF) (pF) (pF) (kHz) at 20 dB (dB)5.46 5.46 5.06 5.46 130.1 6 256.92 6.92 5.92 6.92 115.4 6 307.77 7.77 6.92 7.77 109.9 6 309.19 9.19 6.92 9.19 97.8 2.5 32

14.62 14.62 9.19 14.62 67.9 2.5 3920.91 20.91 12.78 20.91 50.1 2.5 4036.05 36.05 20.91 36.05 30.4 1.2 4061.59 61.59 35.25 61.59 17.7 0.6 41

TABLE 2 QUADRATURE OSCILLATORC1 C2 C3 C4 f0 f (kHz) THD

(pF) (pF) (pF) (pF) (kHz) at 20 dB (dB)1.07 1.07 5.06 5.06 125.9 6 273.56 3.56 5.92 5.92 105.1 6 255.92 5.92 7.77 7.77 80.4 2.5 307.77 7.77 9.62 9.62 66.3 2.5 34

14.22 14.22 15.45 15.45 41.7 2.5 4025.08 25.08 23.26 23.26 27.2 1.2 4040.08 40.08 26.29 26.29 18.6 1.2 4250.01 50.01 35.25 35.25 15 0.6 4261.59 61.59 40.98 40.98 12.3 0.6 41

80 EDN | JANUARY 19, 2006

Three-phase VCOs (voltage-controlled oscillators) see serv-

ice in many applications, includingpower inverters and in electronic-musicsynthesis as control and modulationsources. A previous Design Ideadescribes a basis for a simple, three-phase VCO (Reference 1). However,adding a few components enhances thecircuit’s performance. The original cir-cuit delivers an output of only 600 mVp-p and cannot tolerate substantialloading, especially at low operating fre-quencies at which the circuit draws theleast operating current. Providing accoupling for the output signals doesn’twork well at low frequencies and wors-ens the loading problem. Finally, thecircuit’s dc operating point varies withfrequency.

The circuit in Figure 1 elegantlyovercomes these limitations. The orig-inal circuit uses three of six of aCD4069UB hex inverter’s subcircuits.One of the spares, IC1A, senses thecomplete circuit’s dc operating point.Resistor R2 provides linear feedbackaround IC1A, forcing the input voltageat Pin 9 to equal the output transitionthreshold voltage over a range of oper-

ating currents. In other words, the volt-age is proportional to the average dcvalue of the sinusoidal output wave-forms.

A voltage follower, IC2A, buffers theaveraged voltage at IC1A’s Pin 8. Theremaining sections of IC2 buffer theoscillator’s three outputs, equalizing theloading on the oscillator and providinglow-impedance drive to three differen-tial amplifiers: IC3A, IC3B, and IC3C.The differential stages subtract the dcoffset voltage from IC2A from thebuffered three-phase outputs. You canalter the voltage gain of the three dif-ferential amplifiers from its nominalfactor of five to suit other applications.

Zener diode D1 limits the voltage to10V at IC1’s Pin 14. At low frequenciesand currents, the oscillator’s dc operat-ing point can easily exceed the linearrange of IC2’s inputs. You can use rail-to-rail-capable operational amplifiersinstead of LM324-family devices. Notethat the inputs of IC1’s remainingunused inverters connect to IC1’s Pin 7and not to circuit ground per normalpractice.

Adding an exponential currentsource eases the task of adjusting the

circuit over a wide frequency range.Transistors Q1 and Q2 and their asso-ciated components form a simpleexponential voltage-to-current con-verter. For best results, the base-emit-ter voltages of Q1 and Q2 should matchat the circuit’s nominal operating cur-rent—100 A—and you should ther-mally couple both transistors. If yourapplication requires precise thermaltracking, replace R6 with a 2-k tem-perature-compensating resistor with acoefficient of 3500 ppm/C, such as aTel Labs Q81, which is available fromsuch companies as Precision Resistor(www.precisionresistor.com). Placethis resistor in thermal contact withQ1 and Q2. Temperature-compensat-ing resistors are also available fromMicro-Ohm (www.micro-ohm.com),Vishay (www.vishay.com), Ultronix(www.ultronix.com), and KRL Bantry(www.krlbantry.com).

Using the component values in Fig-ure 1, the circuit’s operating frequen-cy spans 0.1 to 26 Hz. Adding the com-ponents in this Design Idea reduces thecircuit’s dc operating-point shift from5.5V to less than 25 mV over the fre-quency range. Most of the frequency

Harry Bissell Jr, Welding Technology Corp, Farmington Hills, MI

Enhanced, three-phase VCO features ground-referenced outputs

designideas

nth PAC block for oscillation at fre-quency f0. The design uses a Tektron-ix TDS1002 digital oscilloscope’s FFTfunction to measure THD and the

spectral line width of each output fre-quency at a level of 20 dB withrespect to the central frequency, f0.

Figure 3 illustrates the application of

a microcontroller to dynamicallyreconfigure an ispPAC-based oscillatorfor specific frequencies. The non-volatile memory stores frequency-spe-cific capacitance and gain values foreach of the ispPAC10’s circuit blocks.Data transfers occur using the IEEE1149.1 JTAG-standard protocolthrough the ispPAC10’s serial test-access-port interface.EDN

R E F E R E N C E SPAC Designer software, www.

latticesemi.com.http://jlnlabs.imars.com/spgen/

barkhausen.htm.

Figure 3 Either ispPAC10 circuit’s implementation can serve as a foundation fora programmable oscillator by adding a microcontroller and nonvolatile storage.

MICROCONTROLLERFREQUENCY

SELECT

EEPROM

IEEE 1149.1JTAG

ISPPAC10 OUT

1

2

(continued on pg 84)

This Design Idea expands thecapabilities of a previously pub-

lished one (Reference 1). The originalversion featured a current transformerwhose secondary winding formed partof an oscillator’s tank circuit. Under

normal conditions, direct current flow-ing through the current transformer’ssingle-turn primary winding kept thecircuit from oscillating until primarycurrent flow ceased. Although the cir-cuit acted as a power-interruption

detector, when you add a few compo-nents, the operating principle lendsitself to measurement applications.This revised circuit delivers an accuratelinear-voltage output that’s propor-tional to direct current flow throughcurrent-sense transformer T1’s primarywinding (Figure 1). In addition, thecircuit also offers possibilities as an accurrent sensor.

To achieve improved performance,the design retains the original oscillat-

error occurs at the low end of the fre-quency range, at which it’s the leastobjectionable.EDN

R E F E R E N C EDutcher, Al, “Inverters form three-

phase VCO,” EDN, Aug 2, 2001,

pg 102, www.edn.com/article/CA149120.

Improved current monitor delivers proportional-voltage output

designideas

84 EDN | JANUARY 19, 2006

Figure 1 Adding differential and buffer amplifiers and an exponential voltage-to-current converter enhances the perform-ance of a low-frequency, three-phase voltage-controlled oscillator.

FREQUENCY-CONTROLVOLTAGE

INPUT15V

15V

15V

15V

NC

R5100k

R62.2k R4

330

Q22N3906

Q12N3904

R3100k

D11N758A

R210k

D21N4148

D41N4148

D61N4148

D31N4148

D51N4148

D71N4148

R11k

R7100k

R8100k

R10499k

R9499k

R11100k

R12100k

R14499k

R13499k

R15100k

R16100k

R18499k

R17499k

C10.1 F

C210 F

C510 F35V

C610 F35V

C310 F

C410 F

15V

15V

IC1E

IC1F

IC1A

IC2A

NOTES:PLACE Q1 AND Q2 IN THERMAL CONTACT.FOR BEST STABILITY, USE NONPOLARIZED CAPACITORS FOR C2, C3, AND C4.DOTTED LINES BETWEEN Q1 AND Q2 INDICATE THERMAL CONTACT.

14

13

11

12

9 8 IC1B1 2 IC1C

3 4 IC1D5 6

2

34 IC2B

6

57

7

10

DIFFERENTIALAMPLIFIER 1

DIFFERENTIALAMPLIFIER 2

DIFFERENTIALAMPLIFIER 3

IC3A

2

31

IC3D

IC22

31

IC2C

9

108

IC3B

6

57

IC2D

13

1214

IC3C

98

10

(SPARE)

OFFSET-VOLTAGEREFERENCE+

+

PIN 4 PIN 4

PIN 11 PIN 11

POWER-SUPPLYINPUT

IC3

CD4069UB

_

+

_

+

_

+

_

+

_

+

_

+

_

+ PHASE 3OUT

PHASE 2OUT

PHASE 1OUT

_

+

Susanne Nell, Breitenfurt, Austria

1

designideas

86 EDN | JANUARY 19, 2006

ing-circuit concept and adds aPLL circuit and one addition-al winding to the currenttransformer whose secondaryforms an LC oscillator’s reso-nant circuit. Integrating a74HC4046, IC1, the PLLmeasures the frequency of anLC oscillator comprising Q1and its associated componentsand compares it with a fixed-frequency internal VCO (vol-tage-controlled oscillator).The PLL’s phase-comparatoroutput drives a current sourcecomprising Q2 and Q3, whichin turn feeds current to anadditional winding on the cur-rent-sense transformer’s core.

Sources of T1’s ferrite coreinclude Epcos (www.epcos.com), which offers the B642-90L 63287-toroid 20107 material N87; Pramet(wwwpramet.com), which of-fers Fonox Type T20 materialH60; Vacuumschmelze (www.vacuumschmelze.com), withthe VAC T60006L2020-W409-52; and other manu-facturers. Depending on theferrite material you use, thecircuit will operate to somedegree with virtually any fer-rite toroidal core. (It is difficultto simulate this circuit usingPSpice or other simulators; for accurateresults, you need a complex model thataccurately portrays the core’s nonlinearbehavior at various current levels.)

The added winding induces magnet-ic flux in the core, decreasing its per-meability and inductance and raisingthe LC oscillator’s frequency. When theoscillator’s frequency matches theVCO (reference) frequency, the circuitreaches an equilibrium state. An in-creasing or decreasing current throughthe compensation coil balances anyadditional magnetic flux that dc cur-rent flowing through the measurementcoil produces.

Within the PLL’s frequency-trackingrange, the current waveform throughthe compensation coil has the sameshape as fluctuations of the measured

current. The turns ratio of 1-to-250,which also represents the ratio of cur-rents in transformer T1, establishes asecondary current of 10 mA for a pri-mary current of 2.5A. If the PLL cir-cuit’s gain is sufficient and the ferritecore’s region of operation avoids satu-ration, the circuit’s closed-loop config-uration maintains the core’s magneticflux at a constant value and thus min-imizes the effects of core-material non-linearities.

Measuring the voltage differenceacross resistor R5 shows that the circuit’soutput voltage is linearly proportionalto the compensation current, and R5’sresistance scales the voltage output. For100 at R5, a 1V output corresponds toa primary-side current of 2.5A. Withzero current flowing in the single-turn

primary winding, calibrate the circuit’srange by adjusting potentiometer R11 toa set operating point. A voltage drop of2V across R5 sets a measurement rangeof 5 to 5A. To accommodate othermeasurement ranges, you can alter T1’sturns ratio or vary the compensationcurrent by using different values for R5and R11. Use a well-regulated powersupply to provide power for the circuit.You may be able to replace the74HC4046 with a software PLL-emu-lation routine that uses a microcon-troller’s spare processing resources.EDN

R E F E R E N C EAckerley, Kevin, “Impedance trans-

former flags failed fuse,” EDN, Dec17, 2004, pg 67, www.edn.com/article/CA486572.

Figure 1 This current sensor uses a variable-frequency oscillator, Q1, and a PLL, IC1,to measure current in an isolated circuit.

IC174HC4046

Q3BC558

Q2BC558

VCOIN VCOUT

CINSIN

C1AC1BR1

R2

INH

VDD

DEMO

P1P2P3PP

C210 nFC1

100 nF

C3100 nF

C92.2 F

C4100 nF

R1047k

R1147k

R7100k

R6100k

R5100k

R947k

R847k

9

5V

3

14

67

11

12

5

16

10

15

213

4

1

5V

5V

5V

5V

R247k

C5100 nF

C622 nF

C747 nF

R36.8k

Q1

R115k

R42.2k

BC548 C847 F

+ 3

4

J2

CON2

J1

CON2

5V

POWER SUPPLY

5V 5V

1

2

VOLTAGEOUTPUT

200 TURNS 50 TURNS

8 6 5

J4

CON1

1CURRENT TO MEASURE

4 11

J3

CON1

ONE TURN

T1TOROIDFERRITE

CORE

I

1

An application required theextension of Ethernet (IEEE

802.3u-1995) service from a home toa garage, a distance of approximately300 ft. Wireless communicationusing IEEE 802.11a/b/g equipmenthad proved unreliable due to thebuildings’ construction, which com-prises stucco over embedded wiremesh. In effect, the buildings’ wallsform Faraday cages that attenuateradiated signals. Straight-line aerialdeployment of the Ethernet cablebetween buildings would have re-quired installation of support poles,and simply laying the cable on the sur-face of the ground would expose thecable to damage from automobiles,hungry pets, and inquisitive children.At first glance, burial of the cableappeared impractical due to the pres-ence of a large concrete surfacebetween the buildings. However, analternate route through an adjacentgarden would avoid tunneling be-neath the concrete slab but wouldexpose the cable to environmentalhazards, such as spade work and bur-rowing animals.

This Design Idea describes how toenvironmentally “harden” a Category5 UTP (unshielded-twisted-pair) cableconforming to EIA/TIA 568B andISO/IEC 11801:1995 that’s terminatedwith RJ-45 connectors (ISO 8877).Without adding repeaters, a Category5 Ethernet cable can extend to 100m,or a little more than 300 ft. In thisapplication, the cable run comprises100 ft of exposed cable, 100 ft of “gar-den-grade” protected cable, and 100 ftmore of exposed cable. To apply theidea, you have to find a way to protectand handle the exposed 200 ft of cable.

Depending on your installation’srequirements, you will need variousnumbers and lengths of the followingparts: a 100-ft-long garden hosewhose fittings conform to the ANSI/ASME B1.20.7-1991.75-11.5 NHthread-form standard; a 4-GbyteSCSI disk drive, which need not befunctional; a continuous, 300-ft-longCategory 5 Ethernet cable terminat-ed in RJ-45 connectors; a 120-ft-long,nylon twine; a 5-in.-long, electrical-grade, adhesive-backed tape; a 2-in.-steel, socket-head-cap, 1/4-20-threadmachine screw (ANSI/ASME B1.1-1989); and two bricks.

To construct the design, uncoil andstretch the garden hose as straight aspossible, perhaps using a driveway asa work surface. Place a brick on eachend of the hose to prevent it from curl-ing. If you use only one length of gar-den hose, cut off and discard the hosefittings. Using Torx or Philips screw-drivers as appropriate, dismantle the 4-Gbyte SCSI disk drive by removing allof the screws that retain the drive’scover. If the cover resists removal, lookfor screws beneath labels. Remove thedrive’s head-positioning magnets,which can exert a strong pull on near-by ferrous objects. Use caution toavoid pinching your fingers betweenthe magnets and the steel surfaces.Discard the remainder of the SCSIdrive.

Securely tie the nylon twine to the1/4-20 steel machine screw and insertthe screw into one end of the hose.Apply the magnet to the hose’s exte-rior to attract the machine screw.Slide the magnet along the hose topull the nylon twine through thehose. When the screw reaches the

hose’s far end, untie the twine andsave the screw for future use. To easemanipulation of the Category 5cable, deploy it from either its origi-nal dispenser box or a spool mountedon a suitable axle so that the cable caneasily unwind. Securely attach thetwine to one end of the Category 5cable. Walk to the far end of the hoseand gently pull the cable through thehose. If you encounter excessiveresistance, investigate the cause andremove any cable kinks or feeder-endsnags.

When the cable appears at thepulling end, stop for a moment. Go tothe other end of the hose and wrap aninch or two of electrical tape aroundthe cable where it’s just about to enterthe hose. Return to the far end of thehose and continue pulling the cablethrough the hose. Stop pulling whenyou see the electrical-tape marker.You now have a 300-ft-long Catego-ry 5 cable whose central 100 feet thegarden hose protects. If you decide toprotect more of the cable, repeat theprocess by feeding the twine througha second length of hose. Use thehoses’ couplings to make a watertightjoint between lengths. If you take thisapproach, make sure that you proper-ly orient the hose segments before youspend too much time threading thetwine through the hose.EDN

READERS SOLVE DESIGN PROBLEMS

D Is Inside76 Shunt regulator improves poweramplifier’s current-limit accuracy

78 Low-power, super-regenerativereceiver targets 433-MHz ISM band

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

FEBRUARY 2, 2006 | EDN 75

Hardened Ethernet cable goes undergroundPhilip Freidin, Fliptronics, Sunnyvale, CA

Adding current-limiting cir-cuitry to a power amplifier’s or a

linear voltage regulator’s emitter-fol-lower output stage protects both theoutput transistor and the downstreamcircuitry from excessive-current dam-

age. Figure 1 shows the classic current-limiter circuit: Transistor Q2 senses theoutput-current-induced voltage dropacross ballast resistor R2 and divertsbase current from Darlington-con-nected transistors Q1 and Q3. Transis-

tor Q2’s base-emitter voltage, VBE, setsthe circuit’s current-limit threshold.Unfortunately, a small-signal transis-tor’s VBE exhibits a temperature coeffi-cient of 2 mV/C, which causes a sub-stantial variation in the current-limit-ing threshold over the circuit’s operat-ing-temperature range.

You can improve the circuit’s per-formance by replacing Q2 with IC1, anadjustable shunt regulator (Figure 2).With an input threshold voltage of0.6V, the MAX8515 allows use of alower value for current-sense resistorR2 and thus helps minimize R2’s powerand thermal losses. Alternative com-monly available shunt regulatorspresent input voltages of 1.25 to 2.5V.In addition, a separate power-supplyinput connection allows the MAX-8515 to maintain accuracy when itsinternal output transistor approachessaturation.

Figure 3 compares current-limit ac-curacy for the circuits of Figure 1 andFigure 2 over an operating-tempera-ture range of 40 to 85C. Neglect-ing the temperature coefficient of senseresistor R2, the shunt-regulator versionmaintains its output current to an accu-racy of better than 2%, and the small-signal-transistor version exhibits a25% current variation over the oper-ating-temperature range.EDN

designideas

Figure 2 Substituting a shunt regulator, IC1, for Q2 in Figure 1 improves theoutput-current-limit accuracy.

76 EDN | FEBRUARY 2, 2006

Shunt regulator improves poweramplifier’s current-limit accuracy John Guy, Maxim Integrated Products Inc, Sunnyvale, CA

Q3

MJL4281A

Q1

2N3904

R2

0.5

Q4

2N3906

10 mA

OUTPUT

15V

VIN

534

12

IC1MAX8515

Figure 3 Output-current-versus-tem-perature plots for the circuits of fig-ures 1 and 2 show improved accura-cy for the shunt-regulated circuit (bot-tom trace) over the discrete-transistorversion (top trace).

TEMPERATURE (C)

CURRENTLIMIT

(A)

1.6

1.5

1.4

1.3

1.2

1.1

1.040 15 10 35 60 85

2N3904

MAX8515

Figure 1 A small-signal transistor, Q2, provides an output-current limit forthis emitter-follower power amplifier.

Q3

MJL4281A

Q1

2N3904

Q2

2N3904

R1

510

R2

0.5

Q4

2N3906

10 mA

OUTPUT

15V

VIN

Designers often choose a super-regenerative receiver—despite

its frequency instability and poorselectivity—for battery-powered, short-range, wireless applications in whichpower consumption is a major issue.Examples include remote-keyless-access systems, automobile alarms, bio-medical monitors, sensor networks, andcomputer peripherals (Reference 1). Asuper-regenerative detector can alsodemodulate frequency-modulated sig-nals through slope detection. Tune thedetector so that the signal falls on theslope of the detector circuit’s selectiv-ity curve. This Design Idea presents asuper-regenerative receiver that con-sumes less than 1 mW and operates inthe license-free, 433-MHz ISM (indus-trial/scientific/medical) band.

In its simplest form, a super-regener-ative receiver comprises an RF oscilla-tor that a “quench signal,” or lower fre-quency waveform, periodically switch-es on and off. When the quench signalswitches on the oscillator, oscillationsstart to build up with an exponential-ly growing envelope. Applying an ex-ternal signal at the oscillator’s nominalfrequency speeds the growth of theenvelope of these oscillations. Thus,the duty cycle of the quenched oscilla-tor’s amplitude changes in proportionto the amplitude of the applied RF sig-nal (Figure 1).

A super-regenerative detector canreceive AM signals and is well-suited

for detecting OOK (on/off-keyed) datasignals. The super-regenerative detec-tor constitutes a sampled-data system;that is, each quench period samples andamplifies the RF signal. To accuratelyreconstruct the original modulation,the quench generator must operate ata frequency a few times higher than the

highest frequency in the original mod-ulating signal. Adding an envelopedetector followed by a lowpass filterimproves AM demodulation (Refer-ence 2).

Figure 2 is a block diagram of thesuper-regenerative receiver circuit inFigure 3. The heart of the receiver com-prises an ordinary Colpitts-configuredLC oscillator operating at a frequencythat the series resonance of L1, L2, C1,C2, and C3 determines. Switching offtransistor Q1’s bias current quenches the

oscillator. (Note that increasing C1 andC2 improves the oscillator’s frequencystability at the expense of increasedpower consumption.) Cascode-con-nected transistors Q2 and Q3 form anantenna amplifier that improves thereceiver’s noise figure and provides someRF isolation between the oscillator andthe antenna. To conserve power, theamplifier operates only during oscilla-tion growth.

Based on a Schmitt-trigger circuit,the quench generator switches theoscillator and RF-amplifier stage. Toimprove sensitivity, the triangularwaveform across C5 quenches the oscil-lator, and the square wave at the out-put of IC1 switches the RF amplifier.The quench generator’s two outputs arephased in quadrature so that the RFamplifier has received power when thedetector’s oscillations start to grow. Thequench frequency of this circuit is 100kHz to allow data transfers at rates ashigh as 20 kbps.

The envelope detector comprises acommon-source amplifier that’s nomi-nally biased to operate in Class B mode.To increase this stage’s gain, you applya small amount of bias current to makeit operate in Class AB mode. To reducethe load on the oscillator’s LC tank cir-cuit, C10 connects to a tap on inductorL1, as inductor L2 shows.

The first stage in the data-recoverycircuit comprises buffer IC2A; amplifi-er IC2B; and a third-order, lowpass fil-ter for suppressing quench-frequencycomponents in the envelope detector’soutput. A dc-coupled Schmitt-triggercircuit, IC3, extracts the transmitteddata from the demodulated signal. Alowpass filter comprising C12 and R16extracts the demodulated signal’s dc

Low-power, super-regenerativereceiver targets 433-MHz ISM band

designideas

Cedric Mélange, Johan Bauwelinck, and Jan Vandewege, Ghent University, Ghent, Belgium

Figure 2 The super-regenerative receiver is considerablysimpler than a superheterodyne circuit.

Figure 1 In a super-regenerative detector, the arrival ofa signal starts RF oscillations sooner than under no-signal conditions.

78 EDN | FEBRUARY 2, 2006

THERMALNOISE

EXTERNALRF SIGNAL

QUENCHSIGNAL

OSCILLATOROUTPUT

IN ITS SIMPLEST FORM,A SUPER-REGENERATIVERECEIVER COMPRISESAN RF OSCILLATOR THAT A “QUENCH SIGNAL,” OR LOWER FREQUENCY WAVE-FORM, PERIODICALLYSWITCHES ON AND OFF.

ANTENNAAMPLIFIER

DATADETECTION

LCOSCILLATOR

ENVELOPEDETECTOR

QUENCH GENERATOR

component and sets the Schmitt trig-ger’s decision threshold. As a conse-quence, the data transmitter must usea dc-balanced coding scheme, such asManchester coding, for modulation.On the receiving end, no additionalactive components are necessary forextracting the data-recovery circuit’sdecision threshold, which helps mini-mize the receiver’s power consumption.

The prototype occupies a compact pcboard measuring approximately 53cm (Figure 4). Using a simple, home-made PRBS (pseudorandom-binary-se-quence) generator that uses Manches-ter coding with a 28-to-1-bit sequence(Reference 3), BER (bit-error-rate)measurements yield the results in Fig-ure 5. These results demonstrate a sen-sitivity of less than 100 dBm for a 10-to-4 BER at 1 kbps. The receiver con-sumes 270 A at 3V for a power con-sumption of 810 W. As a further

designideas

Figure 3 The super-regenerative receiver features relatively few components.

80 EDN | FEBRUARY 2, 2006

Figure 4 A prototype version of a super-regenerative receiver uses mostlysurface-mount components. The large, black, leaded component in the upperright corner is a power-supply-decoupling capacitor. Note the RF-input con-nector in the center of the pc board.

ENVELOPE DETECTOR

ANTENNAAMPLIFIER

QUENCH GENERATOR

LC OSCILLATOR

VCCVCC

VCC

R11500k

R122.2M

C104.7 pF

L218.5 nH

L19 nH

R13390k

R6910k

R8680k

R9250k

R1075

C7200 pF

C8200 nF

L368 nH

R7130k

R5910k

R4910k

R368k

R12.7k

C22.2 pF

C12.2 pF

C36.8 pF

C615 pF

C410 nF

R2510k

C547 pF

Q4BF909

Q3BFR92A

Q1BFR92A

Q2BFR92A

VCC

IC1

ADCMP371

ADCMP371C9

10 nF

C1447 nF

C13180 pF

IC2A

IC3

TLV2763

TLV2763_

+

R171M

R1524kR14

24k R16620k

R212.2M

R194.3k

R20430k

R1843k

_

+

IC2B

_

+

_

+

C11470 pF C12

33 nF

DATA

DATA DETECTION

enhancement to the design, it includesa transmitter circuit based on Maxim’sMAX1472, creating a simple, compact,low-cost, and low-power transceiver forthe 433-MHz ISM band. You can easilyadapt the receiver circuit for recovery ofAM audio or other analog signals byreplacing the Schmitt trigger, IC3, witha conventional audio-output amplifier.Retune the RF oscillator to cover the fre-quency range of interest.EDN

R E F E R E N C E Shttp://intecweb.intec.ugent.be/data/

researchgroups.asp.Insam, Eddie, “Designing Super-Re-

generative Receivers,” ElectronicsWorld, April 2002, pg 46.

Mélange, Cedric, Johan Bauwelinck,Jo Pletinckx, and Jan Vandewege,“Low-cost BER tester measures errors in low-data-rate applications,” EDN,Dec 5, 2005, pg 123, www.edn.com/article/CA6288033.html.

designideas

82 EDN | FEBRUARY 2, 2006

Figure 5 Measurements of bit-error rate versus input RF power highlight theprototype receiver’s sensitivity. The frequency is 433.92 MHz.

INPUT POWER (dBm)

102

0.1

0.01

0.001

0.0001

0.00001

0.000001

101 100 99 98 97 96 95 94 93 92

BIT-ERRORRATE

1 kBPS

2.5 kBPS

5 kBPS

10 kBPS

15 kBPS

20 kBPS

1

2

3

Thanks to its property of apply-ing an equal amount of delay to

all frequencies below its cutoff fre-quency, the Bessel linear-phase filtersees service in audio applications inwhich it’s necessary to remove out-of-band noise without degrading the phaserelationships of a multifrequency in-band signal. In addition, the Bessel fil-ter’s fast step response and freedom fromovershoot or ringing make it an excel-lent choice as a smoothing filter for anaudio DAC’s output or as an antialias-ing filter for an audio ADC’s input.Bessel filters are also useful for analyz-ing the outputs of Class D amplifiersand for eliminating switching noise inother applications to improve accura-cy of distortion and oscilloscope-wave-form measurements.

Although the Bessel filter providesflat magnitude and linear-phase—that

is, uniform group-delay—responseswithin its passband, it has worse selec-tivity than Butterworth or Chebyshevfilters of the same order, or number ofpoles. Thus, to achieve a given level ofstopband attenuation, you need todesign a higher order Bessel filter,which, in turn, requires careful selec-tion of amplifiers and components toachieve the lowest levels of noise anddistortion.

Figure 1 shows a schematic for a high-performance, eighth-order, 30-kHz,lowpass Bessel filter. This design usesstandard values for 1%-tolerance resis-tors and 5%-tolerance ceramic capaci-tors. As an alternative, you can use 10%-tolerance capacitors at the expense ofincreased group-delay variance withinthe passband. For best results, use tem-perature-stable capacitors.

In this application, the filter process-

es audio signals that swing above andbelow ground, and its amplifiers drawpower from positive and negative2.5V supplies. Rail-to-rail outputcapability helps achieve maximum out-put-voltage swing at these low supplyvoltages. To achieve a high SNR inhigh-quality audio service, the ampli-fiers must exhibit unity-gain stabilityand low inherent noise. For example,Analog Devices’ AD8656 low-noise,precision-CMOS dual op amp meets allof these requirements.

Connecting the amplifiers as invert-ing-gain stages maintains constantinput-common-mode voltage andhelps minimize distortion. Using less-than-1-k resistors throughout the cir-cuit reduces the resistors’ thermal-noisecontributions. Each AD8656 amplifiercontributes less than 3 nV/Hz ofnoise across a 30-kHz bandwidth, andthe total noise over a 30-kHz band-width measures less than 3.5 V rms.For a 1V-rms input signal, the circuityields an SNR of better than 109 dB,and, for a 1-kHz, 1V-rms input signal,the circuit yields a THDN (total-har-monic-distortion-plus-noise) factor ofbetter than 0.0006%.

Figure 2 shows the filter’s measuredmagnitude response for a 1V-rms inputsignal. The filter’s passband gain of 0 dBis flat within 1.2 dB for frequencies as

READERS SOLVE DESIGN PROBLEMS

Lowpass, 30-kHz Bessel filter offers high performance for audio applications

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

Figure 1 Two dual op amps and a handful of passive parts implement a high-performance, eighth-order, 30-kHz, lowpass Bessel filter.

Troy Murphy, Analog Devices, San Jose, CA

FEBRUARY 16, 2006 | EDN 83

_

+

FILTERINPUT

FILTEROUTPUT

R1383

R2383

C23.3 nF

IC1AAD8656C1

10 nF

R3698

2.5V

2.5V

3

2

4

81

1

_

+

R4665

R5665

C42.2 nF

C36.8 nF

R6845

5

67

5

67

_

+

R7422

R8422

C62.2 nF

IC2AAD8656C5

12 nF

R9649

2.5V

2.5V

3

2

4

8_

+

R10549

R11549

C81 nF

C715 nF

R12715

IC1BAD8656

IC2BAD8656

D Is Inside

84 Use a PWM fan controller in an EMI-susceptible circuit

88 PC’s parallel port and a PLDhost multiple stepper motors andswitches

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Microchip Technology (www.microchip.com) offers a family of

cooling-fan speed controllers that oper-ate in PWM mode for use with brush-less dc fans (Reference 1). To controlfan speed using the PWM waveform’sduty cycle, you can use either an exter-nal NTC (negative-temperature-coef-ficient) thermistor or one of Microchip’sPIC microcontrollers and its SMBus

serial-data bus. Figure 1 illustrates a typ-ical application that the data sheetdescribes for the TC664 and TC665controllers (Reference 2). Using a fre-quency-control capacitor, CF, with avalue of 1 F, fan-controller IC1 gener-ates a PWM pulse train with a nominalfrequency of 30 Hz and a temperature-or command-dependent duty cycle thatvaries from 30 to 100%.

Although using the controller inPWM mode reduces power dissipationin transistor QA, which drives the fan,the 100-mA, square-wave motor-drivecurrent can cause unwanted interfer-ence in a nearby high-sensitivity audiocircuit. The circuit in Figure 2 solvesthe problem. An additional driver tran-sistor, Q1, and an RC network com-prising C3 and R3 form a simple PWM-to-linear converter. You can also useanother PWM-to-linear-conversioncircuit, such as an integrator based onan operational amplifier.

Figure 3 shows a graph of the dc volt-age at Q2’s collector versus IC1’s PWM

high as 20 kHz. With its 3-dB pointat 30 kHz, an eighth-order Bessel pres-ents a theoretical attenuation of 110dB at 300 kHz, decreasing at 160dB/decade at higher frequencies. Thischaracteristic provides sufficient at-tenuation of repetitive noise thatswitched-mode power supplies andother sources induce, which typicallyoccurs at frequencies of 300 kHz andhigher.

Figure 3 illustrates the filter’s phaseshift and its group delay, which remainsrelatively constant at roughly 17 sec,even for frequencies as high as 40 kHz.Note the linear scale on Figure 3’s fre-quency axis, which clearly illustratesthe filter’s linear-phase behavior with-in the passband. The following equa-tion defines group delay as the negativepartial derivative of phase shift withrespect to frequency:

Group delay /f.At dc, resistor R1 sets the filter’s input

resistance at 383. If your applicationrequires higher input impedance, youcan insert a unity-gain buffer ahead ofthe filter at the expense of increaseddistortion and noise. For applicationsthat require operation from 15Vpower supplies, replace the AD8656with a higher voltage amplifier, such asAnalog Devices’ AD8672 low-distor-tion, low-noise (3.8-nV/Hz), dualoperational amplifier.EDN

Use a PWM fan controller in an EMI-susceptible circuit

designideas

84 EDN | FEBRUARY 16, 2006

Figure 2 The measured amplitude-versus-frequency response of the circuit inFigure 1 shows a change of scale on the right vertical axis.

0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

20

0

20

40

60

80

100

12010 100 1000 10,000 100,000 1,000,000

FREQUENCY (Hz)

MAGNITUDE ZOOM

(dB)

MAGNITUDE (dB)

MAGNITUDE

MAGNITUDE ZOOM

Figure 3 Measured within the passband of dc to 30 kHz, the Bessel filter’sphase-shift and group-delay characteristics display excellent uniformity andlinearity.

0

90

180

270

360

450

GROUP DELAY

PHASE SHIFT

540

20

18

16

14

12

10

8

6

4

2

00 20,000 40,000 60,000 80,000 100,000

FREQUENCY (Hz)

GROUP DELAY (SEC)

PHASE SHIFT

()

Dimitri Danyuk, Niles Audio Corp

drive-output waveform’s duty cycle. Thevoltage applied to the fan corresponds tothe difference between Q2’s collectorvoltage and the 12V supply voltage.Even though a steady voltage appearsacross the fan, current pulses that the fan motor’s commutation produces stilldevelop a voltage across current-senseresistor RSENSE that connect to Q2’s emit-ter, and all of IC1’s protective and advi-sory features remain available.

The listed component values arevalid for a 100-mA, 12V, brushless fan.Use a general-purpose NPN transistorsuch as the 2N2222 for driver-transis-tor Q1 and an NPN transistor, such asFairchild Semiconductor’s PZT2222A,that can dissipate one-third of the fan’smaximum power consumption for Q2.Note that you can vary the PWM’snominal frequency over a range of 15to 35 Hz by altering the value of CF.EDN

R E F E R E N C E S“Fan Speed Controller and Fan

Fault Detector Family,” MicrochipTechnology Inc, 2002, http://ww1.microchip.com/downloads/en/DeviceDoc/21604c.pdf.

SMBus PWM Fan Speed Con-trollers with Fan Fault Detection,Microchip Technology Inc, 2003,http://ww1.microchip.com/downloads/en/DeviceDoc/21737a.pdf.

designideas

Figure 2 To minimize the effects of high-frequency noise on sensitive analogcircuits, you can convert the high-current PWM waveform applied to the fanto a continuous analog voltage.

86 EDN | FEBRUARY 16, 2006

Figure 1 In a typical application, fan-controller IC1 and transistor QA apply pulse-width-modulated current to vary a fan’s speed as a function of temperature.

IC1TC664TC665

VIN

CF

VDD

RSENSE

CSENSE0.1 F

RISO715VOUT

SCLK

SDA GND

FAULT

NC

SENSE

5V

6

7

8

9QA

FAN

12V

RFAULT20k

5

4

3

2

5V

5V

C10.01 F

CF1 F

C21 F

101

5V

R134.8k

R214.7k

RSCLK20k

RSDA20k

NTC THERMISTOR100k AT 25C

PICMICROMICROCONTROLLER

Figure 3 Output voltage at Q2’s col-lector shows a linear relationshipversus the controller’s pulse-width-modulated output-duty cycle. (Thepulse width increases as the temper-ature increases.) The fan’s operatingvoltage corresponds to the differ-ence between Q2’s output voltageand the 12V supply rail.

1

2

0 20 40 60 80 100

12

9

6

3

0

OUTPUT-DUTY CYCLE (%)

OUTPUT VOLTAGE

(V)IC1TC664TC665

VIN

CF

VDD

RSENSE

CSENSE0.1 F

RISO4.7k

R53.6k

R4680

R320k

VOUT

SCLK

SDA GND

FAULT

NC

SENSE

5V

6

7

8

9

Q2PZT2222A

Q12N2222

FAN

12V

RFAULT20k

5

4

3

2

5V

5V

C10.01 F

CF1 F

C21 F

C3100 F

101

5V

R134.8k

R214.7k

RSCLK20k

RSDA20k

NTC THERMISTOR100k AT 25C

PICMICROMICROCONTROLLER

+

Robotic applications frequentlyinclude multiple stepper motors

and switches. The stepper motors pro-duce motion in several directions, andthe switches identify home positionsand detect proximity to obstacles. ThisDesign Idea describes the developmentand implementation of a PLD (pro-grammable-logic-device)-based inter-face that can connect a PC’s parallelport to as many as eight switches andfour stepper motors (Figure 1). Thisinterface design serves many applica-tions, and using IC1, a 22V10 PLD, to minimize the circuit’s component

count reduces complexity, weight, andoverall dimensions. Drivers IC3through IC6 for the stepper motorscomprise three L293 quad half-H-bridge ICs (Figure 2).

Each rotation of the two-windingstepper motors in this design requires asequence of four mechanical steps thatyou produce by applying a pair of 7V,500-mA, 120-msec-long pulses to themotor’s windings (Figure 3). To makea stepper motor rotate either CW(clockwise) or CCW (counterclock-wise), you apply either of two pulsesequences (tables 1 and 2).

The following sections specify thefunctions of the input and output reg-isters’ bits that control the parallel-portinterface and the PLD. The PLD out-put-register bits are 7, 6, 5, 4, 3, 2, and1. Q7 signals the PC that one or moreswitches are active. Bit 0 means that aswitch is active; bit 1 means that noswitches are active. With Q6, Q5, andQ4, the BSS (buffered-status switch)tells the PC which of n switches isactive: 000S1, 100S5, 001S2,101S6, 010S3, 110S7, 011S4,and 111S8. For Q3, Q2, Q1, and Q0,the PLD’s outputs enable one of thefour motor-driver ICs to drive its asso-ciated stepper motor, with 1000M3,0010M1, 0100M2, and 0001M0.

The PLD input register’s bits are E11,E10, E9, and E0. For E11, the host PCcontrols the PLD, 0 disables the PLD,and 1 enables the PLD. For E10 and E9,the PLD reads these lines to determinewhich of the four motors in Figure 2receives drive pulses: 00 for Motor 0, 10for Motor 2, 01 for Motor 1, and 11 forMotor 3. For bit E0, the PLD reads thisbit to determine what to do with theBSS settings: 0hold, and 1clear. ForE8 through E1, the PLD reads the sta-tus of one switch and stores it in theBSS register:

00000001S1, 00010000S5,00000010S2, 00100000S6, 00000100S3, 01000000S7,00001000S4, 10000000S8.

The PLD ignores any unlisted bits.For the parallel-port output register,

address 88810,D7, and D6, the PC tells

PC’s parallel port and a PLD host multiple stepper motors and switches

designideas

Eduardo Pérez-Lobato, Universidad de Antofagasta, Antofagasta, Chile

Figure 1 A programmable-logic device, IC1, and a few additional compo-nents allow an IBM-compatible PC’s parallel printer port to drive as manyas four external stepper motors and to sense the states of as many as eightrange-of-motion limit switches.

88 EDN | FEBRUARY 16, 2006

12

1

2

3

4

5

6

7

8

9

10

11

GND

CLK

E10

E9

E8S8

S7

S6

S5

S4

S3

S2

S1

E7

E6

E5

E4

E3

E2

E1

E0 D4

VCC

Q7

Q6

Q5

Q4

E11

Q3

Q2

Q1

Q0

1 kHz

19

18

17

16

15

14

13

NC

D5

M3

M2

M1

M0

SELECT

PAPER

BUSY

7404ACK

5V24

23

22

21

20

GND

3

2

4

5

6

7

8

9

10

11

12

13

18

D0

D1

D2

D3

D4

D5

D6

D7

ACK

BUSY

PAPER

SELECT

TO IBM-COMPATIBLEPC'S PRINTER

PORT

NOTE: PINS 1, 14, 15, 16, AND 17 ARE UNUSED.

J1

IC122V10

TABLE 1 CLOCKWISE-ROTATION SEQUENCEStep A B C D

0 1 1 0 01 0 1 1 02 0 0 1 13 1 0 0 1

TABLE 2 COUNTERCLOCKWISE-ROTATION SEQUENCEStep A B C D

0 1 0 0 11 0 0 1 12 0 1 1 03 1 1 0 0

the PLD which motor should run, with00 for Motor 0, 10 for Motor 2, 01 forMotor 1, and 11 for Motor 3. For D5,the PC takes control of the PLD chip:0 disables the PLD, and 1 enables thePLD. For D4, the PC commands thePLD to control the BSS register’s con-tents, with 0 for hold and 1 for clear.For D3 through D0, the PC selectswhich pair of motor windings get ener-gized: 1001A and D, 1100C and D,0011A and B, and 0110C and B.Parallel-port input-register, address888101 indicates acknowledge, busy,paper, or select. The PC reads acknowl-edge to determine whether a switch isactive: 0 means that any switch isactive, and 1 means that no switch is

active. The PC reads thebusy, paper, or select reg-ister to determine whichof the switches is active:

000S1, 011S4,110S7, 001S2,100S5, 111S8,010S3, 101S6.

You can download List-ing 1 for this Design Idea from www.edn.com/060216di3. Note that the PC’s portion of thesoftware is written in Pas-cal, and the PLD’s inter-nal software is written inan emulated version ofBasic.EDN

designideas

Figure 2 Each half-bridge-driver circuit, IC3 through IC6, controls a single two-winding stepper motor.

90 EDN | FEBRUARY 16, 2006

Figure 3 To control a stepper motor’s directionof rotation, energize the windings as shown intables 1 and 2.

B

D

C A

TOIC5

TO IC5

MOTOR 2

B

D

C A

TOIC6

TO IC6

MOTOR 3

B

D

C A

TOIC3

TO IC3

MOTOR 0

B

D

C A

TOIC4

TO IC4

MOTOR 1

1

2

3

4

5

6

7

8

OUT 4OUT 1

OUT 3

VSS

IN 4IN 1

IN 3

GND

GND

GND

GND

14

13

12

11

10

9

D

D3

B

D1

5V

M0

M0

D0

D2

16

15

L293

EN 3, 4

OUT 2

IN 2

VS

EN 1, 2

7V

A

C

1

2

3

4

5

6

7

8

OUT 4OUT 1

OUT 3

VSS

IN 4IN 1

IN 3

GND

GND

GND

GND

14

13

12

11

10

9

D

D3

B

D1

5V

M1

M1

D0

D2

16

15

L293

EN 3, 4

OUT 2

IN 2

VS

EN 1, 2

7V

A

C

1

2

3

4

5

6

7

8

OUT 4OUT 1

OUT 3

VSS

IN 4IN 1

IN 3

GND

GND

GND

GND

14

13

12

11

10

9

D

D3

B

D1

5V

M2

M2

D0

D2

16

15

L293

EN 3, 4

OUT 2

IN 2

VS

EN 1, 2

7V

A

C

1

2

3

4

5

6

7

8

OUT 4OUT 1

OUT 3

VSS

IN 4IN 1

IN 3

GND

GND

GND

GND

14

13

12

11

10

9

D

D3

B

D1

5V

M3

M3

D0

D2

16

15

L293

EN 3, 4

OUT 2

IN 2

VS

EN 1, 2

7V

A

C

When you design for electronicsapplications, such as sensor or

amplifier bias supplies or special wave-form generators, a controlled constant-current source or sink circuit can serveas a useful building block. These cir-cuits exhibit high dynamic-outputimpedance and deliver relatively largecurrents within an allowed range ofcompliance voltage. You can imple-ment a constant-current circuit with anop amp and a discrete external transis-tor, but you can also design a bipolarversion of a current source or sinkaround a single op amp and a few resis-

tors (Figure 1). The constant-currentsink circuits in Figure 1a through Fig-ure 1c offer various compromisesbetween precision, dynamic imped-ance, and compliance range.

The circuit in Figure 1d describes abipolar current source with a simplerfeedback configuration than that of theusual Howland-current pump, whichrequires positive feedback and presentsvariable input impedance. Figure 1eshows a constant-current source. All ofthese circuits exhibit excellent linear-ity of output current with respect toinput voltage. The output from the circuit in Fig-

ure 1a includes an uncertainty due tothe op amp’s quiescent current, whichadds to the calculated output current.For example, in most applications, youcan neglect the MAX4162 op amp’squiescent current of approximately 25A. The circuit in Figure 1b behavessimilarly, but its quiescent current sub-tracts from the ideal output-currentvalue. The circuit in Figure 1c providesa current sink with no quiescent-cur-rent error, and the circuit in Figure 1dpresents a bipolar output—that is, itsinks or sources current—depending onthe polarity of the input voltage. Its per-formance depends on close matchingfor the resistor pairs R1 and R2 and R3and R4 and good tracking of the posi-tive- and negative-power-supply volt-ages. Any difference between theabsolute values of the supply voltagesappears as an offset current at 0V inputvoltage. To achieve insensitivity topower-supply-voltage variations, thecurrent-source circuit in Figure 1erequires close matching of resistor pairsR2 and R3 and R4 and R5.

You can use the following equationsto calculate output currents for the cir-

READERS SOLVE DESIGN PROBLEMS

Op amp can source or sink current

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

Figure 1 This compendium of constant-current circuits includes current sinks(a, b, and c), a bipolar sink or source (d), and a current source (e).

Alfredo H Saab and Steve Logan, Maxim Integrated Products Inc, Sunnyvale, CA

MARCH 2, 2006 | EDN 75

_

+

V+

VMAX4162

100INPUTVOLTAGE

_

+

V+

V+

V+

V

VMAX4162

100

INPUTVOLTAGE

(a) (b)

(d) (e)

OUTPUTCURRENT

(SINK)

OUTPUTCURRENT

(SINK)

OUTPUTCURRENT

(SINK)

_

+

V+

VMAX4162

INPUTVOLTAGE

INPUTVOLTAGE

OUTPUT CURRENT(BIPOLAR DEPENDSON INPUT-VOLTAGE

SIGNAL)

_

+

V+

VMAX4162

100

INPUTVOLTAGE

(c)

R449.9k

R349.9k

R1100

R2100

V+

_

+

V+

VMAX4162

OUTPUTCURRENT(SOURCE)

R349.9k

R549.9k

R1100

R449.9k

R249.9k

D Is Inside76 Simple digital filter cleans up noisy data

78 Single switch selects one of three signals

80 Low-cost audio filter suppresses noise and hum

82 Microprocessor’s single-interrupt input processes multiple external interrupts

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

cuits in Figure 1. Note that RLOAD100 in these examples. In Figure 1a,IOUTVIN/RLOAD25 A; in Figure1b, IOUTVIN/RLOAD25 A; in Fig-ure 1c, IOUTVIN/RLOAD; in Figure1d, IOUT2VIN/RLOAD; and, in Fig-ure 1e, IOUTVIN/RLOAD. The equationfor circuit 1d assumes perfect match-

es—that is, R3R4, R1R2, and VV. It also assumes that R4 is muchgreater than R1.

For a fixed value of output current ineach of the five circuits in Figure 1, thegraphs of Figure 2 show the circuits’dynamic impedance and range of use-ful output voltage (current compli-

ance). The graphs show a high nomi-nal output current of 5 mA to betterdisplay the higher end of the current-amplitude range. Depending on yourapplication, you can optimize each cir-cuit’s dynamic impedance and currentrange through a judicious choice of opamps and resistor values.EDN

designideas

76 EDN | MARCH 2, 2006

Figure 2 These graphs show output current versus output-voltage characteristics for the circuits in Figure 1. Notethat for b and c, the dynamic-output-impedance character-istic closely resembles that of an ideal current source:VOUT/VIN.

OUTPUTCURRENT

(mA)

OUTPUT VOLTAGE (V)

1 2 3 4 5 6 7 8 9 10

5.002

5.001

5

4.999

4.998

VIN = 500 mV, ANDRDYNAMIC = 10 M.

Many systems use an ADC tosample analog data that tem-

perature and pressure sensors produce.Sometimes, system noise or other fac-

tors cause the otherwise slowly fluctu-ating data to “jump around.” To reducehigher frequency noise, designers ofteninstall an analog RC (resistor-capaci-

tor) lowpass filter between the sensorand the analog-to-digital-conversionstage. However, this approach is notalways ideal or practical. For example,a long time constant of minutes wouldrequire very large values for R and C.

Figure 1 shows an analog RC lowpassfilter and its design equations. As analternative, you can clean up noisy sig-nals that remain within the ADC’s lin-

Simple digital filter cleans up noisy data

Richard Rice, Oconomowoc, WI

OUTPUTCURRENT

(mA)

OUTPUT VOLTAGE (V)

1 2 3 4 5 6 7 8 9 10

5.002

5.001

5

4.999

4.998

VIN = 500 mV RDYNAMIC = 72 M.

OUTPUTCURRENT

(mA)

OUTPUT VOLTAGE (V)

1 2 3 4 5 6 7 8 9 10

5.002

5.001

5

4.999

4.998

VIN = 500 mV, V+ = 10V, ANDRDYNAMIC = 80 M.

OUTPUTCURRENT

(mA)

OUTPUT VOLTAGE (V)

5 4 3 2 1 0 1 2 3 4 5

5.1

5.05

5

4.95

4.9

VIN = 250 mV, V+ = 5V, ANDRDYNAMIC = 170 k.

OUTPUTCURRENT

(mA)

OUTPUT VOLTAGE (V)

0 1 2 3 4 5 6

5.1

5.05

5

4.95

4.9

VIN = 500 mV, V+ = 10V, ANDRDYNAMIC = 278 k.

(a)

(c)

(b)

(d)

(e)

designideas

78 EDN | MARCH 2, 2006

This Design Idea shows how youcan use a single-pole momentary-

contact switch to select one of three sig-

nal sources by scrolling through threeoutput states. The circuit in Figure 1comprises commonly available compo-

nents from the CD4000 CMOS-logicseries, along with a general-purposeNPN transistor. The total cost of thecomponents doesn’t exceed $1. Onlyone of circuit’s three outputs, CH1, CH2,or CH3, goes low at any given time, andyou can use these outputs to control ana-log switches, relays, or the gates of JFETswitches. As long as you apply power, the

Single switch selects one of three signals

Felix Matro, JL Audio Corp, Phoenix, AZ

ear range by using the digital equivalentof an analog RC lowpass filter. The fil-ter’s software comprises only two linesof C code: LPOUTLPACC/K, where theoutput value of the filter is LPACC divid-ed by a constant, and LPACCLPACCLPINLPOUT, where you addthe difference between input and out-put to update LPACC. You specify allvariables as integers.

Each time the analog-to-digital con-version acquires a new input sample,LPIN, the software produces an outputvalue, LPOUT, which comprises a low-pass-filtered version of the input sam-ples. Calculate the value of the con-stant, K, based on the sampling rate ofthe system and the desired time con-stant for the filter as follows: KTSPS, where K1, and SPS is thesystem’s sampling rate. For example, fora system-sampling rate of 200 sam-

ples/sec and a desired time constant of30 sec, the constant K would equal6000 samples. Applying a step changeto the routine’s input requires 6000samples to reach approximately 63% ofits final value at the output.

The lowpass accumulator, LPACC,can grow large for large time constantsand large input values. It can grow aslarge as K times the largest possibleLPIN value. Under these conditions,you need to make sure that LPACC doesnot overflow, and you may need tospecify a larger data type to containLPACC. To avoid a long settling timeduring start-up, before the start of thesampling loop, you can initializeLPACC to a value of K times the currentinput value.

You can extend the basic filter con-cept presented to accommodate high-er order filters with greater high-fre-

quency rejection by executing multiplefilter code segments in sequence. Also,you can use an array of variables forLPACC and an array of values of the con-stant K to filter signals that multipledata channels acquire.EDN

Figure 1 In some circumstances,a classic RC lowpass filter doesan adequate job of removingnoise from signals.

INPUTR

OUTPUT

C

T=RC, AND F=1/(2T),WHERE T IS THE TIME CONSTANT IN SECONDS, AND F IS THE CUTOFF 3-dB FREQUENCY.

Figure 1 A handful of active and passive components form a one-of-three selector switch. Press switch S1 once toadvance to the next channel and twice more to revert to Channel 1.

VCC15V

Q12N3904

R11M1%

R24.75k1%

R347.5k1%

R447.5k1%

S1

R5100k1%

C10.1 F C2

0.1 F

IC2B

IC2D

IC2C

NOTE: S1 IS AN SPST NORMALLY OPEN PUSHBUTTON SWITCH.

IC1BCD4093B

IC1ACD4093B

CD4011BCM

CD4011BCM CD4011BCM

5

4

14

14 14

6 1

2

7

3 1311

12

16

10

510

4

4

68

9

9

8

J QK

CLK Q

SET VDD

RESET VSS

IC3ACD4027B

J QK

CLK Q

SET

RESET

IC3BCD4027B

IC4C

3 31

2

1

2

15

14 3

1

77 7

CH1

CH2

CH3

2

CD4011BCM

IC4B

IC4AIC2A

CD4011BCM

CD4011BCM

IC4D

CD4011BCM

GND

VCC 64

10

11

5

65

8

9

13

12

13

1211

C

E

B

selected output does not change, mak-ing the circuit a good choice for appli-cations requiring nonvolatile operation.Quiescent-current consumption aver-ages only about 15 A at room temper-ature, 25C, a low value even for battery-powered applications.

The heart of the circuit comprises adual JK flip-flop, IC3, that’s configuredas a 2-bit ripple counter. Without addi-tional circuitry, the counter would allowselection of four signal sources. Uponinitial application of power, a reset cir-cuit comprising R1, C1, and IC1B alwayssets the CH1 output to a logic-low level.

When the Q outputs of IC3, pins 2 and14, both go to logic zeros, the feedbackchain comprising IC2A, IC2B, IC2C, and

IC4A pulls Q1’s base to a logic-high level,which in turn pulls one input of IC1B toa logic low. This action causes the count-er to skip the 00 state and advances the

count to the 01 state. Components R5,C2, IC1A, and normally open momen-tary-contact switch S1 constitute adebounced switch that provides clockpulses for both sections of the counter,IC3. When a user pushes S1, the count-er advances to the 10 state, and a sub-sequent push advances the counter tothe 11 state. A third push restarts thecycle. To summarize, IC4B decodes thecounter’s 01 state and pulls CH1 low,IC4C decodes the counter’s 10 state andpulls CH2 low, and IC4D decodes thecounter’s 11 state and pulls CH3 low.The layout of the circuit should be non-critical, but use a low-leakage capacitorfor C1. Connect unused logic inputs toground or VCC as appropriate.EDN

The low-cost composite passivefilter in this Design Idea requires

no dc power and can enhance the per-formance of audio equipment andinstrumentation by rejecting power-supply hum and spurious pickup fromAM, FM, and low-band VHF trans-missions (Figure 1). The composite fil-ter comprises a cascade of three simplefilters: a T-section highpass filter toreject power-source hum and two -section lowpass filters to reject spuriousRF signals. As a starting point, thethree filter sections present a lossless0.01-dB Chebyshev response at a 50impedance level, but you can scale thecomponents’ values to meet otherimpedance requirements.

Table 1 lists the components the pro-totype filter uses. With the exceptionof inductor L3, all the components arestandard values that are available offthe shelf. Switch S1 provides a bypassmode that permits rapid frequency-response measurements without con-nection and disconnection of the pro-totype’s BNC connectors. To construct

the prototype, wire all components toa section of perforated breadboard stocksupported by metal spacers that mountinside a die-cast aluminum enclosure.This method of shielded constructionhas proved its worth in other laborato-ry-accessory applications (Reference1). Table 2 lists the filter’s measuredinsertion loss over a range of 40 Hz to200 MHz.

Low-cost polarized electrolytic ca-pacitors C1 through C6 provide rea-

sonable performance, but observeinput polarity for signals with a dc com-ponent. For a modest increase in costand assembly time, you can enhance fil-ter performance and reproducibility byselecting the values of these capacitorsto meet a 10% or better tolerance. Forbest results, use nonpolarized film-dielectric capacitors for C1 through C6.For noncritical applications, you canrelax the tolerances for the remainingcapacitors and use off-the-shelf induc-tors for 22-mH L1, 0.68-mH L2, and 3.9-H L3.

Redesigning the filter to match the600 impedance that you find in clas-sic audio circuits would increase the

designideas

80 EDN | MARCH 2, 2006

Low-cost audio filter suppresses noise and hum

Richard M Kurzrok, RMK Consultants, Queens Village, NY

TABLE 1 COMPONENTS IN THE PROTOTYPE FILTERReferencedesignators Values DescriptionC1, C2, C4, C5 10 F 50V electrolytic capacitor, 20% toleranceC3, C6 4.7 F 50V electrolytic capacitor, 20% toleranceC7, C9 0.15 F Polypropylene capacitor, 2% toleranceC8, C10 0.033 F Polypropylene capacitor, 2% toleranceC11, C12 0.001 F Polypropylene capacitor, 2% toleranceL1 22 mH Inductor, 5% toleranceL2 0.68 mH Inductor, 10% toleranceL3 3.85 H Inductor, 27 turns of AWG #28 magnet wire hand-wound

on T37-2 mixture (Carbonyl E) toroidal coreS1 NA DPDT panel-mounted toggle switchJ1, J2 NA 50 BNC panel jackNA NA Hammond 1590H-BK die-cast aluminum enclosure

R5, C2, IC1A, AND NORMALLY OPENMOMENTARY-CONTACTSWITCH S1 CONSTITUTE A DEBOUNCED SWITCHTHAT PROVIDES CLOCK PULSES FOR BOTH SEC-TIONS OF THE COUNTER.

On the lower end of the per-formance spectrum, many

widely available and inexpensivemicrocontrollers pay for their smallpc-board footprints by omitting func-tions. For example, most low-endprocessors provide only one external-interrupt input pin and only oneaddress vector in memory for the serv-ice routine that processes externalIRQs (interrupt requests). However, a

project occasionally requires that sev-eral interrupt-service programs mustprocess multiple external interruptsfrom various sources. Cost and inven-tory constraints may make it undesir-able to choose another microcon-troller whose only advantage is theavailability of a few more interruptpins.

For example, Freescale Semicon-ductor’s (www.freescale.com) popular

Nitron family of flash-memory micro-controllers, such as the MC68HC-908QT and QY, offer only one IRQinput pin. You can use one-time-pro-grammable versions of the family,such as the MC68HC705KJ1 or MC-68HC705J1A, that offer five exter-nal-interrupt inputs but omit some ofthe family’s valuable functions, suchas flash memory, built-in analog-to-digital conversion, and an advancedinstruction set. You could also selecta larger microcontroller, such as theMC68HC908JL3, from the sameproduct family to gain eight external-interrupt inputs at the expense of sig-

designideas

82 EDN | MARCH 2, 2006

inductors’ values by an order of mag-nitude, which would increase theinductors’ dimensions and costs. Analternative design approach could usecascaded active-RC filters, whichwould pave the way for their inclusioninto completely integrated composite-audio filters.EDN

R E F E R E N C EKurzrok, Richard M, “Simple Lab-

Built Test Accessories for RF, IF,Baseband, and Audio,” High Frequen-cy Electronics, May 2003, pg 60.

TABLE 2 FILTER INSERTION LOSSFrequency Insertion loss Frequency Insertion loss

(kHz) (dB) (MHz) (dB)0.04 45.2 0.1 42.30.07 35.4 0.3 600.1 29.4 0.5 600.2 17.3 1 55.50.3 10.9 2 52.20.5 5.5 3 51.11 2.7 4 56.22 2 5 605 1.9 10 46.5

10 2.1 25 4415 2.7 50 40.520 4.5 100 39.530 11.7 150 4550 24.5 200 44

Figure 1 A highpass filter and two lowpass filters help reduce or eliminate low-frequency hum and high-frequency noisefrom audio signals.

++

++++

50INPUT

IMPEDANCE

50OUTPUT

IMPEDANCES1 J2C1

10 F

C210 F

C510 F

C34.7 F

C410 F

C120.001 F

C110.001 F

C100.033 F

C80.033 F

C90.15 F

C70.15 F

C64.7 F

L20.68 mH

L122 mH

L33.85 H

NOTES:BOTH GROUNDS CONNECT TO CHASSIS.WHEN S1 IS IN THE UP POSITION, IT BYPASSES THE FILTER; WHEN IT IS IN THE DOWN POSITION, IT INSERTS THE FILTER.

HIGHPASS FILTER 20-kHz LOWPASS FILTER 4-MHz LOWPASS FILTER

J1

Microprocessor’s single-interrupt inputprocesses multiple external interruptsAbel Raynus, Armatron International Inc, Malden, MA

1

MARCH 2, 2006 | EDN 83

designideas

nificant increases in cost and pc-boardarea.

This Design Idea offers an alternativethat retains the small processor andadds extra interrupt inputs. The tech-nique involves applying the interruptsignals to an AND gate to generate anIRQ signal and using the microcon-troller’s inputs to recognize the inter-rupt’s source. For example, consider thefour external-interrupt sources in Fig-ure 1. If you apply no interrupt signalsand if all of the AND gate’s inputs restat logic ones, the IRQ level alsoremains at logic one. Applying an inter-rupt signal (a logic-zero level) to anyone of four inputs, INT1 throughINT4, drives the gate’s output to a lowlevel and triggers the interrupt. Theinterrupt-service routine recognizesthe interrupt’s source by testing the lev-els of input pins PA0, PA1, PA4, andPA5 and executing the correspondinginterrupt-service routine.

The MC68HC908QY2 microcon-troller, IC1, includes built-in pullup

resistors that eliminate the need forexternal resistors, and you can use aninexpensive and readily available74LS21 for IC2. For demonstration pur-poses, this circuit displays the addressof an incoming interrupt by lightingone of four corresponding LED indica-tors for 3 sec. The software routine in

Listing 1 that assigns a priority to eachinterrupt uses the standard set of assem-bler instructions and can apply to anymicrocontroller. You can downloadListing 1, as well as the sample’s assem-bler code and its accompanying table ofequations (Listing 2), from www.edn.com/060302di1.EDN

Figure 1 An external AND gate plus a software routine expand a microcon-troller’s single interrupt input into four inputs.

IC2A1/2 74LS21

PA0PA1PA4PA5

PB2

PB0

PB1

PB3

13

14

14

15

10

11

1245INT 4

INT 3INT 2INT 1

1254

IRQ

5V

16

7

6 9

1

IC1MC68HC908QY2

LED1

LED2

LED3

LED4

NOTE: LED1 TO LED4 ARE KINGBRIGHT CORP'S W934GD-5V WITH BUILT-IN RESISORS FOR OPERATION AT 5V.

Connecting a 600 audio circuitto a 50 or 75 circuit or test

instrument requires an impedance-matching circuit or, when isolation ofthe circuits is necessary, a transformer.Both approaches offer advantages anddisadvantages. A conventional trans-former can match impedances with lowtypical losses of 1.5 dB, provide dc iso-lation, and operate from either a bal-anced or an unbalanced, 600 primarycircuit. A high-quality transformer’s pass-

band can accommodate an audio-fre-quency range of 300 Hz to 15 kHz withminimal amplitude variation. However,transformers that can match 600 to 50or 75 may not be readily available ormay command a cost premium.

A minimum-loss, fixed-value im-pedance-matching circuit, or pad, pro-vides frequency-invariant audio-im-pedance transformation and can com-prise as few as two resistors. Althougha pad can provide useful impedance

matching, it introduces a significantinsertion loss of 14.8 dB for a 600-to-75 transformation or 16.6 dB for a600-to-50 transformation, either ofwhich might impose an unacceptableloss of dynamic range.

Part of a suite of test accessories, thislow-cost, switchable, dual-impedancetransformation circuit comprises a sin-gle conventional transformer and twominimum-loss pads (Reference 1). Asingle inexpensive, conventional trans-former steps down the 600 primaryinput impedance to an intermediateimpedance level of 100 (Figure 1).Switch S1 selects a 100 to 50 or a 100to 75 minimum-loss pad. Construc-tion of the unit involves noncriticalpoint-to-point wiring, although thisdesign uses a Hammond 1590LB die-cast-aluminum box to provide shield-ing and a rugged enclosure to supportthree Amphenol (www.amphenolrf.com) RFX series BNC panel-mounted,insulated-frame input and outputjacks. T1 is a Mouser Electronics(www.mouser.com) 42TM031 audiotransformer, and the resistors are 0.5W,metal-film units with 1% tolerances.With quantity discounts, the overallbill-of-materials cost is less than $20.

To verify frequency response and

READERS SOLVE DESIGN PROBLEMS

Audio-test accessory isolates and matches loads

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideasRichard M Kurzrok, RMK Consultants, Queens Village, NY

MARCH 16, 2006 | EDN 77

D Is Inside78 One oscillator drives multiple solid-state relays

80 Low-dropout linear regulatorsdouble as voltage-supervisor circuits

84 External components providetrue shutdown for boost converter

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 A handful of passive components creates a handy test fixture for matchingimpedances in audio-test circuits.

CT (NOT USED)CT (NOT USED)

T1

S1

J2

J3

J1

600INPUT

600 100

R271.5

R449.9

R171.5

R3150

TO 50 LOAD

TO 75 LOAD

NOTES:ALL GROUNDS CONNECT TO CHASSIS.COAXIAL CONNECTORS J1, J2, AND J3 ARE AMPHENOL PART NO. 31-10-RFX.IF MECHANICAL COMPATIBILITY WITH 75 BNC SERIES CONNECTORS IS NECESSARY, REPLACE J3 WITH AN APPROPRIATE CONNECTOR.

SELECT OUTPUT IMPEDANCE

TABLE 1 INSERTION LOSS VERSUS FREQUENCYFrequency Insertion loss (dB) Insertion loss (dB)

(kHz) 600 to 50 600 to 750.1 11.7 8.70.3 10 70.5 9.5 6.71 9.2 6.52 9 6.35 8.9 6.1

10 8.8 6.120 8.8 650 8.9 6.1

100 9.5 6.7

Thanks to a combination of lowinitial cost and low on-resist-

ance, a conventional electromechan-ical relay often makes sense for switch-ing large amounts of load current onand off and when proportional controlof the load’s current or voltage is un-necessary. Low cost and low on-resist-ance represent the main reasons thatrelays still enjoy widespread use in theindustry. In addition, a relay remainsuseful for switching high-voltage acunder the control of low-voltage elec-tronics, due to the high degree of iso-lation between the control and theload circuits.

However, although relay technologyhas matured and offers proven per-formance, the relay remains a mechan-ical device that suffers from wearing outand other failure modes. Electricalendurance of the relay’s contactsimposes a limit on the number ofswitching cycles. When a relay’s con-tact opens, interruption of the currentin an inductive load causes a spark thatdeteriorates the contact’s performance.When switching high currents, a relaymay reach the end of its operating life-time in as few as 100,000 actuationcycles.

As an alternative to a conventionalrelay, a series-connected pair of MOS-FETs can replace a contact in an ac cir-cuit (Figure 1). A pair of IRF530devices switches loads in circuits withpeak maximum voltages as high as100V. Based on the well-known 555timer, an astable oscillator, IC1, pro-vides a source of square-wave voltage todrive the MOSFET pairs’ gate. Resis-tors R1 and R2 provide charge and dis-charge paths for timing capacitor C1.The 555’s output stage can sink andsource several tens of milliamperes andprovide enough current to drive asmany as 10 stages’ simultaneously oper-ating switch gates, each consuming 5mA of peak current; the 555’s outputsinks a maximum of 50 mA at an on-state maximum voltage of 0.75V. The555’s output drives a distribution busthat provides power to an array of pulsetransformers, T1 and T2. Capacitor C3in series with the transformers’ primaryremoves the dc offset voltage thatwould otherwise appear across thewinding.

Selection of the transformer is notcritical, and any ferrite-core pulsetransformer that can provide gate volt-age to the MOSFETs and maintain a

safe level of voltage isolation can func-tion in the circuit. For example, youcan use C&D Technologies’ (www.cdtech.com) 76601/3, which providesa 1-to-1 turns ratio at a primary induc-tance of 219 H with 500V-dc inter-winding isolation.

Applying a control signal to the baseof general-purpose NPN switchingtransistor Q3 allows collector current toflow through the primary of its associ-ated transformer. Diode D2 provides areverse-current path through thewinding. On the secondary side, diodeD1 rectifies the secondary voltage andcharges capacitor C4, which filters therectified voltage to improve noiseimmunity and reduce voltage ripple atthe MOSFETs’ gates. Removing thecontrol signal switches off Q1 and Q2.Resistor R3 provides a discharge pathfor C4, allowing the MOSFETs toswitch off in approximately 3 msec. Forfaster turn-off, you can reduce the valueof either C4 or R3 at the expense ofincreased ripple on the rectified gatevoltage.

Using two series-connected MOS-FETs allows bidirectional ac conduc-tion through the pair. When theMOSFETs are off, their parasiticdiodes connect in series oppositionand thus block conduction. You canselect from among a range of MOS-FETs to match your application’srequirements, but make sure that thevoltage you apply to the gates of Q1and Q2 is sufficient to fully switch

attenuation in a 600 test setup, con-nect two identical units back to backthrough their 50 or 75 terminals. Youobtain the measured data (Table 1) fora single unit by halving the 600-to-600 transmission-loss measurements.

Calculated insertion loss for the 100to 50 minimum-loss pad is 7.7 dB, andinsertion loss for the 100 to 75 mini-mum-loss pad is 4.8 dB. Subtractingthese values from the measured lossesindicates that the transformer con-

tributes a midband loss of 1.3 to 1.5 dB.Insertion loss due to stray coupling fromthe selected output port to an unusedoutput exceeds 40 dB. Combining aconventional transformer with twominimum-loss pads takes advantage ofthe best of both techniques.

The low-cost transformer con-tributes moderate insertion losses andprovides dc isolation and good fre-quency response. In addition, thetransformer’s low-frequency roll-off

helps reduce 60-Hz hum and low-fre-quency noise. The electrically isolatedinput jack allows connection of thetransformer’s input to balanced orgrounded 600 sources.EDN

R E F E R E N C EKurzrok, Richard M, “Simple Lab-

Built Test Accessories for RF, IF,Baseband, and Audio,” High Frequen-cy Electronics, May 2003, pg 60.

designideas

78 EDN | MARCH 16, 2006

One oscillator drives multiple solid-state relays

Juan Ramón Vadillo Pastor, SOR Internacional SA, Saint Quirze Del Valles, Barcelona, Spain

1

Many low-dropout voltage reg-ulators include an enable-input

pin that can also serve as an inexpen-sive alternative to a voltage-supervisorIC. Although the enable pin normal-ly serves as a means of shutting downthe regulator’s output to save power, a

few discrete components ensure thatthe regulator’s output will turn on andoff at appropriate input voltages.Thus, you can use the circuit as a volt-age supervisor or as a controlled-char-acteristic linear-voltage regulator.

A typical low-dropout regulator’s

internal enable circuit comprises a voltage comparator that determineswhether the voltage at the enable pin iseither larger or smaller than an internalreference voltage, VREF. Although youcan create a low-dropout voltage super-visor by directly connecting the enablepin to the unregulated input voltage, thiscircuit’s turn-on and turn-off voltagesequal the reference voltage, which typ-ically falls below the minimum operat-ing voltage that most ICs powered bythe regulator’s output require.

both devices into full conduction.The IRF530 has a gate threshold volt-age of 3V, but applying a gate-sourcevoltage of 10V ensures low on-resist-ance. You can adjust the gate-sourcevoltage by altering the transformer’sturns ratio or IC1’s power-supply volt-

age within its 4.5 to 16V rating (ref-erences 1 and 2).EDN

R E F E R E N C E S“Transformer-isolated gate driver

provides very large duty cycle ratios,”Application Note 950, International

Rectifier Co, www.irf.com/technical-info/appnotes/an-950.pdf.

Balogh, Laszlo, “Design and appli-cation guide for high speed MOSFETgate drive circuits,” Texas Instruments,2002, focus.ti.com/lit/ml/slup169/slup169.pdf.

designideas

80 EDN | MARCH 16, 2006

Low-dropout linear regulators double as voltage-supervisor circuits

William Lepkowski, On Semiconductor, Tucson, AZ

Figure 1 A single 555 oscillator provides square-wave ac gate drive to an array of as many as 15 MOSFET-based solid-state relays.

RESET

TRIGGER

THRESHOLD

DISCHARGE

CONTROL OUTPUT

IC1NE555P

C21 nF

C11 nF

C5220 nF

C610 nF

D41N4148

D31N4148

Q4IRF530 Q5

IRF530

Q6BC547B

R64.7k

R5100k

R23.3k

R18.2k

9V

1

5 3

7

6

2

4

8

T2

0V5V

2

CONTROLSIGNAL

60 kHz

FROMSOURCE

TO LOAD

C3220 nF

C410 nF

D21N4148

D11N4148

Q1IRF530

Q2IRF530

Q3BC547B

R44.7k

R3100k

T1

0V5V

1

CONTROLSIGNAL

FROMSOURCE

TO LOAD

BIDIRECTIONAL-CURRENT-CONDUCTION PATHTO ADDITIONAL

CIRCUITS

1

2

In addition, directly connecting the enable pin to theunregulated input doesn’t provide a turn-on delay to ensurethat the input voltage has reached a value higher than thelow-dropout regulator’s dropout voltage. The directly con-nected circuit has unsatisfactory power-up and power-downcharacteristics (Figure 1). As a first-order improvement,you can enhance the circuit’s performance by adding R1,CIN, and D1 to provide a start-up delay for the voltage reg-ulator’s enable pin (Figure 2). Unfortunately, the externaldelay network improves the output’s rising-edge charac-teristic, but its falling edge continues to track the input volt-age (Figure 3).

You can solve the circuit’s shutdown problem by replac-ing the single resistor with a voltage-divider network (Figure 4). Resistor R2 raises the switching threshold ofthe regulator’s enable pin and “tricks” the enable com-parator into turning on at a higher voltage. The regula-tor’s output then exhibits an adequate start-up delay and

designideas

82 EDN | MARCH 16, 2006

Figure 1 Connecting a low-dropout regulator’s enablepin directly to the unregulated voltage input forces theoutput voltage to track the input voltage during the reg-ulator’s turn-on and turn-off intervals.

Figure 3 The added components in Figure 2 eliminatethe problem of rising-edge output-voltage tracking.However, the falling-edge output voltage still tracks theinput voltage.

NCP500

VIN VOUT VOUT+

GNDENABLE

VIN+

COUT1 F

CIN10 F

CD0.22 F

R115k

D11N5817

Figure 2 An alternative to directly connecting the regu-lator’s input and enable pins, this “conventional” modifi-cation uses a resistor and a capacitor to delay the reg-ulator’s turn-on time. The diode eliminates the power-down delay interval.

NCP500

VIN VOUT VOUT+

GNDENABLE

VIN+

COUT1 F

CIN10 F

CD0.22 F

R227k

R18k

D11N5817

Figure 4 Resistor R2 increases the enable pin’s switch-ing threshold voltage.

Figure 5 The addition of R2 in Figure 3 solves the falling-edge problem, and shutdown occurs immediately afterthe input voltage drops too low. The regulator’s outputswitches on only after sufficient voltage is present at itsinput.

The step-up switching-convert-er circuit in Figure 1 presents a

familiar problem: If you shut downboost converter IC1 by pulling itsSHDN input low, external inductor L1and forward-biased Schottky diode D1allow the load to continue drawing cur-rent. For battery-powered applicationsthat present a heavy load—300 mA, forexample—this unwanted dc-currentpath may quickly drain the battery.Adding an N-channel MOSFET, Q1,and a 100-k resistor, R1, solves theproblem by opening the unwanted cur-rent path during shutdown. Theresulting circuit is suitable for battery-powered-system applications in whicha microcontroller handles the powermanagement.

Asserting a low logic level on theSHDN input simultaneously shutsdown the switching converter, aMAX756, and turns off the MOSFET,thereby blocking load current byremoving the load’s ground connec-tion. When the SHDN signal de-asserts, the 100-k pullup resistorturns on the MOSFET by pulling theMOSFET’s gate high. With its groundreconnected, the load then draws cur-

rent from the activated boost-con-verter circuit.

For optimum results at high load cur-rents, select a logic-level MOSFET for

Q1 that presents a reasonably low on-resistance.. The MOSFET’s drain-to-source breakdown voltage should alsobe able to withstand at least twice themaximum output voltage you expectfrom the boost converter. If necessary,you can reduce the MOSFET’s effectiveon-resistance by connecting two ormore MOSFETs in parallel.EDN

designideas

84 EDN | MARCH 16, 2006

cleanly switches on and off (Figure 5).You can use Equation 1 to calculate

the values of resistors R1 and R2 to alterthe enable pin’s threshold voltage inthe circuit in Figure 4.

where VIN(TURN-ON) is the user-definedturn-on voltage, VEN(RISING) is theenable pin’s rising-edge trip-point volt-age, and VEN(FALLING) is the enable pin’s

falling-edge trip-point voltage. Forexample, VIN(TURN-ON)4V, VEN(RISING)0.89V, and VEN(FALLING)0.85V. To pre-vent the regulated output voltage fromtracking the input, set the minimumvalue of VIN(TURN-ON) to VOUTVDROPOUT, where VDROPOUT is the drop-out voltage.

If you select a value of 8 k for R2, thenR13.3R2, or approximately 27 k.

Equation 1 calculates only approxi-mate values for the voltage-divider resis-tors, which may vary slightly dependingon the voltage regulator’s characteris-tics. If the resistors’ values are too low,the regulated output tracks the input, aproblem that you can easily solve byincreasing the value of R1. Also, R1 andCD determine the regulator’s turn-ondelay time, and CD’s capacitanceshould ideally be 0.01 to 0.47 F. Toolarge a value increases the dischargetime and reduces the circuit’s effective-ness as a voltage supervisor.EDN

External components provide true shutdown for boost converterNavid Mostafavi, Maxim Integrated Products Inc, Sunnyvale, CA

IC1MAX756

LBI

REF

GND

LBO

OUT

LX

4

6

8

LOW-BATTERY-DETECTOR

OUTPUT

LOAD

D11N5817

L122 H

C3100 F

R1100k

C2150 F

C10.1 F

+

+

1

2

3

NC

7

5

INPUT2V TO VOUT

SHDN

SHDNINPUT

3/5

IOUT

Q1

SG

D

VOUT

Figure 1 Adding R1 and MOSFET Q1 to this step-up-converter circuit enables theSHDN control to impose a “true” shutdown that blocks load current when boostconverter IC1 switches off.

(1)

(2)

Many applications require amethod of switching an analog

or a digital signal on or off under digi-tal control. A “wish list” of specifica-tions for such a switch might includeattenuation of less than 90 dB when theswitch is in its off-state, distortion of nomore than 0.002% when the switch is

in its on-state, and the ability torespond to an on or an off command in10 sec or less. In addition, the circuitshould accommodate positive- or neg-ative-going signals, and no turn-on orturn-off overshoot should occur foreither signal polarity. The list mightalso require that the circuit’s control

input must accept digital signals frommost logic families and that the circuit’sSNR should exceed 90 dB.

The circuit in Figure 1, comprisingIC1, a low-noise, high-speed, precisionLinear Technology LT1007 opera-tional amplifier and IC2, a MaximMAX301 dual SPST, normally openanalog switch, fulfills these require-ments. In the circuit, VIN is the inputvoltage, and VOS and IOS representoperational amplifier IC1’s voltage andcurrent offsets of either polarity. IOFFrepresents the off-state leakage currentof either section of analog switch IC2.In the buffer circuit, RR1R2, andR4R/2. Hence, R(R1R2)/(R1R2)R4.

If all resistors were identical in value,R would equal zero. However, eachresistor exhibits its own tolerance error,and the equation for R expands to:

where e1 through e4 are maximum tol-erance errors of 1%. Worst-case val-ues for R occur when the tolerancevalues e1 and e2 for R1 and R2 are of thesame sign and e4 for R4 has the oppo-site sign:

READERS SOLVE DESIGN PROBLEMS

D Is Inside96 Single switch serves dual dutyin small, microprocessor-basedsystem

98 Isolated-FET pulse driverreduces size, power consumption

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

On/off buffer switches analog or digital signals

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideasLiviu Pascu, Kepco, Flushing, NY

MARCH 30, 2006 | EDN 95

Figure 1 This buffered switch can accommodate either analog or digital signals.

R410k

C1100 nF

C2100 nF

R220k

R120k

C3100 pF

C6100 nF

C5100 nF

D11N4148

D21N4148

C4100 nF

R31k

R5

IC1LT1007

3 17

4

1 9 16

8

6NC

NC2

OUTPUT

15V

15

INPUT

15V

POSITIVEOFFSET

NEGATIVEOFFSET

15

15V

COM1

COM2

NC1 NC2

IN1

IN2

15

10

ON/OFFCONTROL

BUFFER:0=ON;1=OFF.

V+ VVL GND

11 12 13 14

5V

15V

8

IC2MAX301

IC2A

IC2B

_

+

,

Traditional control-system de-signs use separate switches to

control power and various system func-

tions, but adding a few components toa small, microprocessor-based systemcan combine a control function with

the system’s on/off switch. For example,you can design a system to display rel-ative humidity and temperature (Ref-erence 1). This small, battery-poweredsystem requires a microprocessor-con-trolled on/off power switch, which youimplement with a pushbutton, and afunction switch to change the displayfrom degrees Celsius to degrees Fah-

Single switch serves dual duty in small, microprocessor-based system

designideas

Steve Hageman, Windsor, CA

96 EDN | MARCH 30, 2006

Simplifying further, RR|e|(0.01)R when you use 1%-toleranceresistors for R1, R2, and R4. The com-bination of the resistors’ tolerances withthe operational amplifier’s internalerrors and leakage effects from switch-es IC2A and IC2B determines the buffer’saccuracy. When the circuit is on, bothIC2A and IC2B are open. The followingequation defines the circuit’s outputvoltage:

Simplifying further, you can calculateVOUT(ON) as: VOUT(ON)(VIN)VOS((IOS)(R))((IOFF)(R)).

Most of today’s solid-state switchespresent an IOFF of less than 1 nA, andyou can select an op amp for IC1 whoseVOS is less than 50 V and whose IOSis less than 50 nA. Thus, for the resis-tor values in Figure 1, the maximumerror for the amplifier’s on-state isapproximately 80 V, or 0.0008%,when referred to a 10V nominal output.You can determine the minimumallowable value of the amplifier’s loadresistance by solving the followingequation:

where VSAT represents the op amp’smaximum saturated output voltage—usually, 13.5V for 15V power-supply

voltages. For example, using the resis-tor values in Figure 1 and assuming amaximum output voltage of 10V, youcan calculate a minimum allowableload resistance of 3.3 k.

Also, IAMP, the current from IC1,should be less than the device’s speci-fied maximum current output: IAMP(VOUTMAX)[(1/R2)(1/RLOAD)].

Using these values, you can deter-mine that IAMP is 3.5 mA, which is lesscurrent than most op amps as sourcesdeliver. When the amplifier is off,switches IC2A and IC2B are closed. Inthis state, the worst-case output occursfor VINMAX. IC1’s offset errors are negli-gible with respect to the full-scale inputvoltage. Therefore, for the real case inwhich the on-resistance of IC2A andIC2B is much less than the load resist-ance, the following equation definesthe circuit’s output voltage: VOUTOFF[(VINR2RONRON)/(K1K2K3K4)], where K1R1R2R3, K2R1R3RON, K3R1RONRON, andK4R1R2RON. For R1R2R and RONR, and RONR3, theequation simplifies to: VOUTOFF[(VINRONRON)/(RR3)].

Many of today’s analog switches pres-ent a maximum 20 on-resistance, and,using the resistor values in Figure 1 andan input voltage of 10V, you can calcu-late that output voltage to be approxi-mately 200 V, or 0.002%, whenreferred to a 10V nominal output.Amplifier IC1’s slew rate limits the cir-cuit’s dynamic behavior, because analogswitch IC2 generally switches in muchless than 1 sec. Using an operationalamplifier with a slew rate of 1.5V/secyields a circuit-response time of 10 sec.

For applications that require unipo-lar outputs when the amplifier is in its

off-state, you can add a known output-offset voltage by connecting resistor R5between the buffer’s output and thepower-supply voltage of the samepolarity as the desired offset voltage.Note that IC1’s output must be able tosink current. Adding resistor R5 does-n’t affect the circuit’s output voltage inits on-state because the closed-loopgain lowers the amplifier’s outputimpedance.

To analyze the circuit’s offset outputvoltage, assume that IC2A and IC2B pre-sent an on-resistance that’s much lessthan RLOAD, R2, and R5. The followingequations define the circuit’s positiveand negative offset-output voltages,VOUT(OS) and VOUT(OS), respectively:

To make the offset voltage lessdependent on the input signal, calcu-late the maximum value for R5 as:

Using the resistor values in Figure 1,solving this equation produces a min-imum reliable offset voltage of 2 mV;the value of R5 must be 150 k or less.The maximum current-sinking abilityof IC1 determines the minimum valueof R5.EDN

,

renheit, which you implement as a tog-gle switch. From ease-of-use and total-cost perspectives, combining these twofunctions in a single switch makessense.

Figure 1 shows a circuit for this ap-plication. Initially, Q1, a P-channelMOSFET, is off because R1 holds Q1’sgate-to-source voltage at 0V. No inputreaches voltage regulator IC1, and,thus, the system’s microprocessor, IC2,also remains off. When the operatorpresses the normally closed momen-tary-contact pushbutton switch, S1,current flows through R1 and R2 toground, developing sufficient gate-to-source voltage to turn on Q1 and applypower to voltage regulator IC1 and the

microprocessor. Capacitor C1 de-bounces the switch contact andensures that Q1 remains on longenough to start the microprocessor,regardless of how quickly the user press-es and releases the switch. In addition,as its final task, the start-up firmwareinitializes the system’s LCD, thus rein-forcing the operator’s tendency to holdthe power switch in its on position longenough to ensure full start-up.

Immediately after the microprocessorpowers up, it begins executing itsfirmware and turns on Q2, an N-chan-nel MOSFET, by delivering a logic oneof more than 3V to Q2’s gate. In turn,Q2 keeps Q1 switched on, and the sys-tem runs under software control. If the

operator again presses the on/off but-ton, Q1 remains on, and the micro-processor continues to run but pulls itsmode line high. The mode line drivesan interrupt input pin, and the softwarecan use the interrupt as a toggling func-tion or to access a wraparound, multi-ple-choice menu. After a suitable pre-programmed time interval, the micro-processor system turns itself off by plac-ing a logic zero on Q2’s gate. In turn, Q2switches off Q1 to remove power fromthe system.EDN

R E F E R E N C EHageman, Steve, “Relative humid-

ity/temperature meter,” www.analoghome.com/projects/dewpointer.html.

designideas

98 EDN | MARCH 30, 2006

B0

B1

B2

B3

B4

B5

B6

A0

5V

1 3

2

5V

A1

A2

A3

A4

A5

VR

COM

OUTINP

VDD

IC2

C50.1 F

C410 F

C310 F

C10.1 F

C20.1 F

R2100

R3100

S1

R110k

R410k

R510k

Q1TP0610T

Q22N7000

IC1VOLTAGE REGULATOR

LP2931AZ

9VSYSTEMBATTERY

ON/OFF AND MODEPUSHBUTTON SWITCH

SPDT MOMENTARYCONTACT

NO NC

MODE TO MICROPROCESSORINTERRUPT INPUT

MICRO-PROCESSOR

I/O LINE

Figure 1 A single pushbutton switch can control power and select among operating modes in a simple microprocessor-based system.

Three-phase controlled rectifiersand inverters, matrix cyclocon-

verters, and cascaded power stages typ-ically comprise large numbers of powertransistors, each with its own driver cir-cuit. The circuit in Figure 1 drives acapacitive-input power device, such asa MOSFET or an IGBT (insulated-gate

bipolar transistor) with pulses of allduty cycles at frequencies of 1 to 200kHz. A single transformer provides gal-vanic isolation, and the circuit con-sumes little power from its 15V pri-mary-side power supply. Tested satis-factorily using several MOSFETs andIGBTs with input capacitances as high

as 5 nF, the driver can accommodatehigher current power transistors byresizing the driver’s transistors and cou-pling transformer and a few passivecomponents.

Transistors Q1 and Q2 transmit puls-es of approximately 1-sec durationthrough coupling transformer T1 totransistors Q3 and Q4, which respec-tively charge and discharge power tran-sistor Q5’s gate-source input capaci-tance. The charging pulse that Q1 pro-duces begins on the rising edge of thedrive-control signal, and the discharge

Isolated-FET pulse driver reduces size, power consumption

José M Espí, Rafael García-Gil, and Jaime Castelló, Electronic Engineering Department, University of Valencia, Spain

1

pulse that Q2 produces begins on thefalling edge of the control signal. Dif-ferentiator circuits comprising C1, R1,a portion of potentiometer P1, C2, R2,and the remaining portion of P1 set thedurations of the charge and dischargepulses. If necessary, adjusting P1’s set-ting alters the balance of the positiveand negative charge and discharge volt-ages that Q5’s gate receives.

Transistors Q3 and Q4, respectively,transmit pulses to charge or dischargeQ5’s input capacitance and thenswitch off, producing a high impedanceacross Q5’s input capacitance so thatQ5’s gate voltage doesn’t change,except for discharging slowly due tosmall leakage currents. Thus, the driv-er circuit consumes power only during

the short intervals of the gate-to-sourcecharge and discharge processes.

When transistors Q1 through Q4switch off, resistor and diode pairs R3, D3,R4, and D4 form a path for transformerT1’s demagnetization current. Al-though they’re reverse-biased most ofthe time, diodes D5 and D6 form a peak-amplitude discriminator, configured as alogical-OR circuit, to ensure that gatevoltages at Q3 and Q4 always equal orexceed the voltage at the positive ter-minal of Q5’s gate-to-source capacitance.

Resistors R5 and R6 limit charge anddischarge rates for Q5’s gate-to-sourcecapacitance and can vary depending onQ5’s drive characteristics. TransformerT1 comprises a Philips RM5/I core of3E5 ferrite material with a center-

designideas

100 EDN | MARCH 30, 2006

14

11

9

15V

0V

8

15 7

12 5

10 31

2

4

6

15V IC1CD4049

C2470 pF

R1560

D11N4148

D21N4148

Q2ZVN2106

Q4ZVP2106

D61N4148

D51N4148 D7

12V

Q5 VCC

D812V

Q3ZVP2106

Q1ZVN2106

R2560

P11k

R447 R6

2.2

R52.2

RLOAD

R347

C3100 F

C1470 pF

+

15V

D31N4148

D41N4148

T1

170 H10 TURNS

240 H12 TURNS

170 H10 TURNS

G

S

E

C

+

Figure 1 The isolated pulse driver transmits all duty cycles and consumes energy only during the gate charge and dis-charge processes.

Figure 2 A top view of the isolatedgate driver’s prototype version showsthat an isolation barrier interrupts theground plane beneath transformer T1

(upper right center).

Figure 3 The top trace shows the driver-control voltage, and the bottom trace shows the gate-source voltage of anAPT40GF120JRD IGBT, Q5, at 20 kHz. You can use poten-tiometer P1 to adjust the 9.1 and 20.7V high and low gate-to-source levels, respectively.

Figure 4 The top trace shows the driven transistor’s gate-to-source voltage, and the bottom trace shows its collector-emit-ter voltage, which a probe attenuates. The transistor’s loadcomprises a resistor that connects to a power supply.

designideas

102 EDN | MARCH 30, 2006

tapped, 20-turn primary winding and a12-turn secondary winding, both fabri-cated from 0.2-mm-diameter, 0.008-in,AWG #32 magnet wire.

When transistor Q1 switches on, itinduces a positive voltage in T1’s sec-ondary winding that switches on P-channel MOSFET Q3 and drives Q4’sinternal body diode into conduction tobegin charging Q5’s gate-to-sourcecapacitance. Q3’s on-channel resist-ance primarily determines the chargingrate. Charging ends either when thepulse terminates or when Q5’s gate-to-source voltage approximates T1’s sec-ondary voltage minus Q3’s gate-threshold voltage.

Next, Q3 switches off, allowing thecharging current to decay to zero andthe capacitance to reach its maximumpositive charge. When Q1 switches off,transformer T1’s magnetizing currentresets through R3 and D3. The voltageat T1’s secondary winding goes slightlynegative to balance the core’s volt-sec-ond characteristic, which forward-bias-

es Q3’s body diode without current, andQ4’s body diode blocks the discharge ofQ5’s gate-to-source voltage.

The negative voltage you apply toQ4’s gate cannot switch on Q4 becausediode D5’s forward-voltage drop setsQ4’s gate voltage higher than the volt-age at Q5’s gate. Thus, Q5’s input capac-itance remains charged, and the resetpath presents high impedance to thiscapacitance. When Q2 switches on, thenegative voltage that appears on T1’ssecondary turns on Q4 and starts thedischarge process, which ends whenQ4’s source-to-gate voltage equals itsthreshold level or when the pulse ter-minates. Then, Q4 turns off, and Q5’sgate-to-source capacitance reaches itsminimum negative voltage. When Q2turns off, T1’s magnetizing currentresets through D4 and R4, Q4’s bodydiode conducts, and Q3’s body diodeblocks Q5’s gate-to-source voltage.Diode D6 applies a high voltage to Q3’sand Q4’s gates to ensure that the resetvoltage at T1’s secondary doesn’t drive

Q3 into conduction. Thus, all transis-tors remain off, and Q5’s gate-to-sourcecapacitance remains discharged.When Q1 next switches on, the se-quence repeats.

Figure 2 shows the driver prototypecompared with a €1 coin and a powertransistor. The transistor, an Ad-vanced Power Technology APT40GF-120JRD, combines an IGBT and aFRED (fast-recovery epitaxial diode)that operates at a maximum of 1200Vand 60A with a gate-to-source capaci-tance of 4 nF. The transistor comes ina JEDEC SOT-227 package measuringapproximately 1.51 in. (3825mm). Figures 3 and 4 show experi-mental waveforms for the circuit of Fig-ure 1 to drive IGBT Q5 at 20 kHz. Theturn-on delay is approximately 600nsec, and the total current consump-tion is 22 mA for a power consumptionof 0.33W. When driving transistors thatpresent a lower gate-to-source capaci-tance, the circuit’s turn-on delay andpower consumption both decrease.EDN

Most of today’s CPLDs (com-plex programmable-logic de-

vices) feature reduced-power operatingmodes, but, when the system is not inuse, a complete shutdown that con-serves battery power remains the ulti-mate power-reduction goal of manydesigners. Figure 1 shows how you canadd a few discrete components to aCPLD—in this example, an AlteraEPM570-T100—to implement a bat-tery-powered system’s power-down cir-cuit. An external P-channel MOSFET,Q1, an International Rectifier (www.irf.com) IRLML6302 or equivalent,serves as a power-control switch for the

CPLD, IC1, and other components inthe system. The CPLD and an array ofswitches control the MOSFET’s gate,applying bias that switches on Q1whenever a user presses a switch. TheCPLD includes an embedded timerthat monitors switches and systemactivity. After a specified period of inac-tivity, the timer disables the MOSFET’sgate drive, powering down the CPLDand other components connected tothe MOSFET.

Q1’s source connects to the battery’spositive terminal, and its drain con-nects to IC1’s VCC(INT), VCC(IO1), andVCC(IO2) power pins and other compo-

nents that require power-down control.When power switches off, a 1-kpullup resistor, R3, keeps Q1 off bymaintaining its gate at a gate-to-sourcevoltage of 0V. When you turn off IC1,it presents a leakage path to groundthrough the CPLD’s power-down pin.The EPM570-T100 includes hot-sock-et protection that limits the currentavailable from any user-accessible de-vice-I/O pin to less than 300 A. Thus,even in the worst case, the voltage thatthe I/O pin develops across R3 doesn’treach the FET’s minimum gate-thresh-old turn-on voltage of 0.7V.

Pressing any switch creates a currentpath through the switch’s contacts andits associated diode, which in turndevelops approximately 2.3V of gate-source bias across R3—more thanenough to turn on Q1 and to power upIC1 in approximately 100 sec. Whenyou actuate the mechanical switches,they exhibit a minimum on-time of atleast 3 msec, whereas a typical humanoperator’s minimum press-and-releaseoperation consumes at least 30 msec.During these relatively slow responsetimes, the CPLD can turn on, resettingits internal circuitry and asserting itspower-down pin to a logic zero thatturns on Q1 before the operator canrelease the switch.

READERS SOLVE DESIGN PROBLEMS

CPLD automatically powers itself off

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideasRafael Camarota, Altera Corp, San Jose, CA

APRIL 13, 2006 | EDN 97

Figure 1 A few external components and internal logic blocks enable a CPLDcircuit to switch itself off after a predetermined interval.

APPLICATIONLOGIC

JTAG PINS 22, 23, 24, 25

GROUND PINS 10, 11, 32, 37, 46, 60,65, 79, 90, 93

25-HEADERPROGRAMMING

INTERFACE

EN

R44 MILLION

CO

LPM_COUNTER

ALTUFM_OSC

4.4-MHzPOWER-DOWN

VCC PINS 9, 13, 31, 39, 45,59, 63, 80, 88, 94

EPM570-T100

TWO AA BATTERIES

(3V NOMINAL)

C10.1 F

Q1IRLML6302

R21k

R31k

D21N914

R11k

D11N914

S2

S1

G

S

D

SWITCHED POWER TO OTHER

COMPONENTS

IC1

NOTE: S1 AND S2 ARE NORMALLY OPENPUSHBUTTON SWITCHES.

D Is Inside98 Amplifier removes common-mode noise on RGB differential-video-transmission line

102 Use a switching-regulator controller to generate fast pulses

106 Shift registers and resistorsdeliver multiphase sine waves

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Comprising four twisted pairswithin a durable external sheath,

Category 5 network cable offers a com-mon and cost-effective choice for trans-mitting component-video signals.Three of the pairs can carry RGB video

signals, and the fourth pair carriesaudio, synchronization, and othertransmissions. Unfortunately, Catego-ry 5 cable lacks shielding, and thus it’ssomewhat vulnerable to common-mode coupling that induces equal volt-

ages in each of the cable’s conductors.As a first line of defense against com-mon-mode problems, you can config-ure RGB signals as differential voltages,but any voltage difference between theground references of the twisted-pairs’drivers and receivers results in a com-mon-mode signal on each of thereceived lines.

Common-mode-noise voltages limittransmission quality of video signals.This Design Idea shows how you canuse a single operational amplifier to

Amplifier removes common-modenoise on RGB differential-video-transmission line

designideas

Tamara Papalias and Mike Wong, Intersil Corp

98 EDN | APRIL 13, 2006

In addition to user-specified applica-tion logic (not shown), the CPLD’spower-control logic adds a pair of stan-dard parameterized, library-macro cir-cuits that Altera’s (www.altera.com)Quartus II development tools generate.An internal 4.4-MHz25% oscillator,Altufm_osc, drives a modulo-44-mil-lion LPM (library-parameterized-mod-ule) counter. A logic-low signal thatthe CPLD’s application logic producesor closing any switch resets the count-er. When you reset the counter, itscarry-out signal goes low and drives theexternal power-down pin. An invertedversion of the carry-out signal re-enables the LPM counter once youremove the reset.

If you leave all switches open and theapplication logic becomes inactive, thecounter counts to 44 million in ap-proximately 10 sec, and the internalcarry-out signal goes high, disabling thecounter and holding the carry-out sig-nal high. In turn, the power-down pinrises toward VCC, turning off Q1 whenthe voltage on the power-down pinreaches 2.3V. Removing power fromthe CPLD places the power-down pinin the tristate, or disconnected, mode,and R3 keeps Q1 off.

You can use JTAG-compliant com-mands to configure the EPM570-T100with a download cable you connect toa manufacturer-defined 10-pin header.The process requires that you press anexternal switch before, during, andshortly after configuration to ensure thatthe CPLD receives power throughout

the configuration process. You can setthe inactivity time-out to any desiredvalue by changing the counter’s modu-lus. Although power, ground, and JTAGsignals use specific device pins, you canassign any general-purpose CPLD I/Opins as inputs for switches and as thepower-down output.

If your application requires a matrixof pushbutton switches, you can useonly n diodes to configure an nmswitch matrix for efficient power-updetection (Figure 2). In this example,rows of switches connect to the MOS-FET’s gate through diodes D1 through

D4. Resistors R8 through R11 provide aground path for each column ofswitches and carry current only duringkey closures, holding the column inputslow while waiting to minimize power-supply current drain.

When a user presses any switch, Q1’sgate goes low, turning on the CPLD. Afast CPLD-power-up routine allows theapplication to scan the switch matrix’srows and columns and determinewhich switch a user pressed before theuser can release the switch. In thisapplication, the row signals reset theLPM counter’s inactivity timer.EDN

Figure 2 A keypad matrix expands the CPLD circuit’s control capabilities andretains the circuit’s automatic power-off function.

R81k

D41N914

D31N914

D21N914

D11N914

IC1CPLD

R310k

Q1

R710k

R610k

R510k

R410k

R91k

R101k

R111k POWER-

DOWN

COLUMN 0

COLUMN 1

COLUMN 2

COLUMN 3

ROW 0

ROW 1

ROW 2

ROW 3

VCC

VCCINTVCCOCX

D

G

S

minimize common-mode signals’ ef-fects on differential-component-videoreceivers. In Figure 1, the receiver cir-cuits’ ground terminals (in red) showthat the ground-reference voltages ofeach of the RGB differential signalsdiffer from those present at the driv-ers. To maintain signal quality andminimize reflections, each video-sig-nal twisted-pair transmission line ter-minates in 100. For example, resis-tors R35 and R37 terminate the Rline, and R36 and R38 terminate theR line. Meanwhile, the G and Btermination circuits are identical. Anycommon-mode voltage on the R-sig-nal pair appears at the junction of R37and R38 and across R39.

To create a common-mode cancel-lation voltage, operational amplifierIC1 sums and inverts the signals on allthree or four signal-line pairs. Forexample, adding the R and R sig-nals cancels their differential-voltagecomponents and doubles the com-mon-mode voltage that each line con-tributes. Capacitors C1 and C2 provideac coupling for the circuit’s input andoutput, respectively. The output fromIC1 applies a common-mode bias volt-age through a matched pair of 30-kresistors, R42 and R43, to the R andR receiver network. Close toler-ances for R42 and R43 ensure that thedifferential voltages delivered atROUT

and ROUTclosely balance with

respect to the inputs’ common-mode

designideas

100 EDN | APRIL 13, 2006

Figure 1 A common-mode-cleanup circuit reduces noise pickup on unshieldedCategory 5 differential-video signals.

Figure 2 The common-mode signal (yellow trace) heavilyinfluences the video signal (pink trace).

Figure 3 Adding the common-mode-reduction circuit inFigure 1 significantly reduces the amount of common-mode voltage on the video signal.

ROUTRR3550

R3750

R39150

R4230k

R3850

R4330k

R4012k

ROUTR

R3650

R4112k

GOUTGR1850

R2050

R22150

R2530k

R2150

R2630k

R2312k

GOUTG

R1950

R2412k

BOUTBR2750

R2950

R45150

R3330k

R3050

R3430k

R3112k

BOUTB

R2850

R68k

C210 F

C52.2 F

C110 F

C62.2 F

R112.2k

R176k

R166k

R126k

R136k

R146k

R156k

R3212k

C85 pF

C125 pF

C115 pF

C105 pF

C95 pF

C75 pF

NCNC

IC1ISL55001

GND

VS 9V

9V VS

OUT

NC

8

7

6

5

1

2

3

4

voltage. Capacitors C11 and C12 pro-vide equalization to boost the differ-ential-video signal’s higher frequencycomponents.

Before applying cancellation, thesignals at the circuit’s outputs ROUT

and ROUTwould appear as: ROUT

VDIFF/2VCM, and ROUTVDIFF/

2VCM, where VDIFF represents thedesired differential signal, and VCMexists with respect to the circuit’s localground. After applying cancellation,the output signals appear as: ROUT

VDIFF/2VCMVCMSVDIFF/2,and ROUTVDIFF/2VCMVCMSVDIF/2, where VCMS represents the

summed and inverted common-modevoltage at IC1’s output.

Figure 2 shows a representative 1Vpeak received signal that’s on the Rline (yellow trace) and an accompa-nying 2V peak common-mode signal(pink trace). Figure 3 shows the circuit’s common-mode-cancellationabilities. Although the differentialsignal (yellow) remains unchanged,the common-mode signal (pink)exhibits an 80%, 14-dB reduction.Any mismatch between the time delayand the summed analog signal, whichthe passive input network and IC1,respectively, produce, prevents com-

plete cancellation. Also, for best per-formance, the common-mode signalmust not exceed IC1’s common-modeinput-voltage rating. In addition, IC1,an Intersil ISL55001, must exhibitunity-gain stability over a wide band-width and an excellent slew-rate re-sponse and, for best results, must oper-ate at relatively high-power-supplyvoltages for good linearity. Use 10-F,nonpolarized input- and output-cou-pling capacitors to accommodate ex-tremely low-frequency common-mode voltages. Ensure adequate by-passing for IC1’s power-supply termi-nals for all frequencies of interest.EDN

designideas

102 EDN | APRIL 13, 2006

A source of pulses with fast-ris-ing edges that approximate the

step function can help you performmany useful laboratory measure-ments, including characterization ofcoaxial cables’ rise times and locationof cable faults using time-domain-reflectometry methods. For example,evaluating the rise time of a 10- to 20-ft-long RG-58/U cable requires edge-transition times of 1 to 2 nsec. Agi-lent’s (www.agilent.com) HP8012B, a

workhorse pulse generator that findsuse in many electronics labs, can deliv-er pulses with rise times of 5 nsec thatare adequate for many applications butnot for cable characterization.

As an alternative, switching-regu-lator-controller ICs can deliver gate-drive pulses with rise and fall times ofless than 2 nsec, making them idealcandidates for laboratory pulse-gener-ation service. A simple implementa-tion uses Linear Technology’s (www.

linear.com) LTC3803 constant-fre-quency flyback controller, IC1 (Figure1). The controller self-clocks at 200kHz, and applying a sample of its out-put to its Sense pin causes the con-troller to operate at its minimum dutycycle and produce a 300-nsec-wideoutput pulse.

The LTC3803’s output can delivermore than 180 mA into a 50 load,so use a low-series-inductance bypasscapacitor that connects as directly aspossible between IC1’s power andground (pins 5 and 2). The decouplingcomponents, C1, a 10-F ceramiccapacitor, and R1, a 200 resistor,minimize pulse-top aberrations with-out introducing amplitude droop.The circuit’s output directly drives a50 termination at amplitudes as highas 9V. For applications that requiremaximum pulse fidelity, use a back-termination resistor, RBACKTERM, tosuppress triple-transit echos andabsorb reflections from the cable andany mismatch in the cable’s far-endtermination impedance. Back-termi-nation also helps when driving passivefilters, which expect to see a specificgenerator impedance. The LTC-3803’s output impedance is ap-proximately 1.5, which affects thevalue of the back-termination resistor.The back-termination technique

Use a switching-regulator controller to generate fast pulses

Mitchell Lee, Linear Technology Corp

Figure 1 Switching-regulator-controller IC1 delivers pulses with 1.5-nsec riseand fall times into a 50 load.

VCC

NGATE

SENSE

ITH/RUN

VFB

GND2

3

1 6

5

4

J1RBACKTERM48.7

VCC12V

R2100k

R12005%

250 mW

IC1LTC3803

R32k

C110 F

6VCERAMIC

NC

(continued on pg 106)

Sine waves with fixed phase rela-tionships find application in

communications equipment, instru-mentation, and power sources. Al-though you can use any of several tra-ditional analog techniques to generatebasic sine-wave signals, this Design Ideaoffers a simple method that uses onlydigital logic and fixed-value resistors(Figure 1a). A common clock pulsedrives three of four sections of a pair ofCD4015 4-bit shift registers that recir-culate a pattern comprising 12 zerosand 12 ones—that is, 00000000000-0111111111111. Each of the registers’outputs drives a resistor, R1 through R12,that connects to a summing node. If allof the resistors were of equal value, theirsummed output would comprise astepped linear triangular waveform at a repetition frequency one-twenty-fourth that of the clock frequency.

To produce a stepped sinusoidal out-put waveform, you replace the equal-value resistors with the weighted val-ues in Figure 1a. If you use resistors of1% tolerance, the output’s amplitudewill approximate that of a true sinewave to better than 1. To produce acleaner sine wave, a lowpass filter helpsremove clock-pulse feedthrough andstepped-edge transients (Figure 1b).For many applications, a simple one-pole lowpass filter/buffer provides ade-quate filtering, but a more elaboratemultipole filter further increases outputpurity.

You can add a second set of registersand resistors, R13 through R24, to pro-duce cosine and sine waves offset by a

90 phase shift—that is, two sine wavesin quadrature (Figure 2). RegisterIC2A’s inverted and recirculated outputfrom Q4 generates the 0000000000-

00111111111111 bit pattern that thefirst set of shift registers uses. IC1B’s Q2output produces the D input that youapply to the second set of shift regis-ters—IC2B, IC3A, and IC3B—which inturn generate a 90 phase-shifted ver-sion of the bit pattern to form a cosinewave. The cosine bit pattern requiresno recirculation and simply propagates

works well with load impedances of atleast 2 k. At impedances higherthan that value, parasitic impedancesassociated with the terminating resis-tor and IC1 degrade bandwidth andpulse fidelity.

In a back-terminated, 50 system,

the circuit delivers a 4.5V output pulsewith symmetric rise and fall times of1.5 nsec, pulse-top-amplitude aberra-tions of less than 10%, and amplitudedroop of less than 5%. Directly driv-ing a 50 load doesn’t degrade theoutput’s rise and fall times. For best

pulse fidelity, use stripline techniquesto route IC1’s output directly to thetermination resistor and output con-nector J1. Using a 100-mil-wide traceon a 1/16-in., double-sided, glass-epoxypc board approximates a 50 surgeimpedance.EDN

designideas

106 EDN | APRIL 13, 2006

Shift registers and resistors deliver multiphase sine waves

Figure 1 A pair of shift registers, an inverter, and a handful of precision resis-tors form a sine-wave generator (a). Two operational amplifiers form a resist-ance-capacitance lowpass filter that removes clock-signal artifacts from theoutput (b).

Gary Steinbaugh, 4 E A Transform, Loveland, OH

R1 1M

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IC2B

IC2A

IC1A

IC1B

IC3

SINE-WAVEOUTPUT

RESET ONPOWER UP

CLOCK IN(24fOUT)

DUAL FOUR-STAGE

SHIFT REGISTER

INVERTER

(a)

(b)

SINE-WAVEINPUT

IC4

IC5

_

+

_

+

R

C

SMOOTHEDSINE-WAVE

OUTPUT

through the second set of shift registers and “falls off the end.”To adjust the second output’s phase shift with respect to the firstoutput from 15 to 180 in 15 increments, you can connect IC2B’sD input to any one of IC1’s or IC2A’s Q outputs.

Figure 3 illustrates a three-phase sine-wave-generator circuit.The Q4 output from IC1B supplies the D input to the second setof shift registers, IC2A and IC2B, to produce the recirculated bitpattern. In similar fashion, the Q4 output from IC3A supplies theD input to the third set of shift registers, IC4A, to transfer a dupli-cate bit pattern that’s phase-shifted by 240 with respect to theoutput from the first set of shift registers.

Register IC2B’s D input connects to IC1B’s Q4 output to pro-duce a signal—Phase 2’s output—that lags behind the Phase 1output by 120. In similar fashion, register IC4A’s D input con-nects to IC3A’s Q4 output to produce a signal—Phase 3’s out-put—that lags behind Phase 2’s output by 120, or 240 withrespect to Phase 1.

You can expand the basic circuit to accommodate addition-al signal phases. The weighted resistors’ values are adequate forlow-frequency sine waves and 4000-series CMOS-logic devices.However, you can scale the resistors’ values to accommodateother output frequencies and logic families.EDN

designideas

108 EDN | APRIL 13, 2006

Figure 2 Add a second set of shift registers to generate acosine wave.

R1 1M

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SINE-WAVEOUTPUT

CLOCK IN(24fOUT)

DUAL FOUR-STAGE

SHIFT REGISTER

INVERTER

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RRESET ONPOWER-UP

Figure 3 Adding a third set of shift registers yields a three-phase sine-wave output.

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CLOCK IN(24fOUT)

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RESET ONPOWER-UP

A Class D amplifier providesbetter efficiency and thermal

performance than a comparable ClassAB amplifier, but implementing a ClassD amplifier still requires attention togood electrical- and thermal-designpractices. Most engineers use a contin-uous-sine-wave-input signal to evaluatea Class D amplifier’s performance in thelab. Although convenient for measure-ment purposes, a sine wave representsa worst-case scenario for the amplifier’sthermal load. If you drive a Class Damplifier near maximum output powerwith a continuous sine wave, it’s notuncommon for the amplifier to enterthermal shutdown.

Typical audio-program material com-prising music and voice has a muchlower rms value than its peak outputpower. The ratio of peak-to-rms power,

or “crest factor,” typically averagesabout 12 dB for voice and 18 to 20 dBfor musical instruments. Figure 1 showstime-domain-oscilloscope, rms-voltagemeasurements of an audio signal and asine wave. Although the audio signalcorresponds to a burst of music, it pres-ents a slightly higher peak value thanthe sine wave, and its rms valueapproaches only half and may averageeven less than that of the sine wave. Anaudio signal’s thermal effects on a ClassD amplifier are considerably lower thana sine wave’s, and, thus, it’s importantto test performance with actual audiosignals instead of sine waves.

In an industry-standard TQFNpackage, a bottom-side-exposed padprovides the primary path for heattransfer from the IC and into copperareas of the amplifier’s pc board that

serves as a heat sink. Soldering the ICto a large copper pad helps minimizethermal resistance, as do multiple viasthat transfer heat to the pc board’sopposite side, on which an additionalcopper area further reduces thermalresistance. In addition, you can connectany of the device’s pins to the thermaltransfer area, provided that the pins andthermal pad are at the same electricalpotential, such as the upper- and lower-right pins in Figure 2.

Although an IC’s pins don’t providethe primary heat-transfer path, they dodissipate a small amount of heat, and it’shelpful to maximize the widths of all pctraces that connect to the IC. Figure 3shows how wide traces connect the IC’soutputs to two inductors. In this case,the inductor’s copper windings providean additional thermal path away fromthe Class D amplifier. Improving heatdissipation by even a few percentagepoints may make the differencebetween achieving acceptable per-formance and encountering thermalproblems. To further reduce thermalresistance, you can specify a heat sink

READERS SOLVE DESIGN PROBLEMS

Thermal considerations matter for Class D amplifiers

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideasJohn Guy, Maxim Integrated Products, San Jose, CA

APRIL 27, 2006 | EDN 93

Figure 1 A sine wave’s higher rms level than that of an audio signal predictsthe additional thermal burden on a Class D amplifier that’s tested with a sinewave.

D Is Inside

96 Microcontroller simplifies bat-tery-state-of-charge measurement

98 Switching regulator efficientlycontrols white-LED current

100 Programmed reference oscillator generates nonstandardclock frequencies

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

designideas

94 EDN | APRIL 27, 2006

that solders to the pc board adjacent tothe IC. For example, a Wakefield Engi-neering (www.wakefield.com) 218-series sink has lower edges that form theconduction path.

A few basic calculations can help youestimate a Class D-amplifier IC’s dietemperature. For example, consider anamplifier that operates at an ambienttemperature of 40C, has output powerof 16W, and has 87% efficiency. Spec-ified thermal resistance from the IC’sjunction to ambient air is 21C/W.First, calculate the Class D amplifier’spower dissipation: PDISS[(POUT/)POUT](16W/87%)16W2.4W,where PDISS is the dissipated power,POUT is the output power, and is theefficiency. Use the power dissipation tocalculate the die temperature, TC, asfollows: TCTAPDISSJA40C2.4W21C90.4C, which is withinthe device’s maximum junction tem-perature of 150C. A system seldomenjoys the luxury of operation at a 25Cambient temperature, and it’s impor-tant to base these calculations on a rea-sonable estimate of the system’s actualinternal ambient temperature.

The on-resistance of a Class D ampli-fier’s MOSFET output stage affectsboth its efficiency and its peak-currentcapability. Reducing the peak load cur-rent reduces the infinite-impulse-response losses and increases efficien-

cy in the MOSFETs. To further lowerpeak currents, choose the highestimpedance speaker that delivers thedesired output power within the volt-age-swing limits of the Class D ampli-fier and its supply voltage. In Figure 4,a Class D amplifier with an output-cur-rent capability of 2A and a supply-volt-age range of 5 to 24V goes into currentlimiting with a 4 load and a supplyvoltage of 8V for a corresponding max-imum continuous output of 8W.

If 8W represents an acceptable out-put power, consider using a 12 speak-er and a 15V supply voltage. The peakcurrent limit then occurs at 1.25A, witha corresponding maximum continuousoutput power of 9.4W. Furthermore, the12 load operates at 10 to 15% high-er efficiency than the 4 load and thus

lowers the IC’s power dissipation. Ac-tual efficiency improvements varyamong Class D-amplifier ICs.

To complicate matters for the designer, a loudspeaker behaves as acomplex electromechanical systemthat presents a variety of resonancesacross its frequency range and exhibitsits nominal impedance only within anarrow frequency band (Figure 5).Over much of its audio bandwidth, thisloudspeaker’s impedance exceeds itsnominal value of 8; adding acrossover network and a tweeter mayreduce the total load impedance belowthe nominal value. Keep the loadimpedance’s behavior in mind whenyou consider the amplifier’s power-sup-ply current and thermal-dissipationcapability.EDN

Figure 2 The exposed tinned-cop-per pad in the center provides theprimary thermal path for a Class D-amplifier IC in a TQFN or TQFPpackage.

Figure 3 The wide traces to theright of this Class D-amplifier IChelp conduct heat away from thedevice and into the adjacent components.

Figure 4 Selecting an optimal impedance, such as 12,and supply voltage, such as 15V, maximizes output powerand prevents current-limiting-induced distortion.

25

20

15

10

5

5 10 15 20 250

POWER-SUPPLY VOLTAGE (V)

4

6

8

12

PEAK OUTPUT POWER

(W)

100

5

10

15

20

25

30

100 1000 10,000

FREQUENCY(Hz)

IMPEDANCE()

Figure 5 The electrical impedance of this nominally 8,13-cm-diameter, wide-range loudspeaker varies signifi-cantly with frequency.

designideas

96 EDN | APRIL 27, 2006

A system that receives itspower from a renewable-energy

source, such as a photovoltaic panel ora wind-driven generator, typicallyaccumulates power in a rechargeablebattery and delivers it to a load. Often,both processes occur simultaneously.Periodic evaluation of the battery’sremaining charge ensures extended per-formance and battery life, as does con-trol of the battery current that goes tothe load. A battery’s residual chargecomprises its previously calculatedcharge plus the amount of newly accu-mulated charge or minus the amount ofcharge it expends. According toCoulomb’s Law, you can calculate theaccumulated charge as follows:

where QACC is the amount of a battery’snewly accumulated charge, and i rep-resents the amount of current inte-grated over time interval t.

In its discrete form, the equationbecomes

where n represents the number of cur-rent measurements, Ik, taken during thetime interval, t. Although you canselect any value for t, it’s convenientto choose a value equal to one hour,because battery manufacturers specifycapacity in units of ampere-hours.

To simplify the microcontroller’sfirmware and reduce the amount ofmemory necessary for arithmetic oper-ations, you can divide one hour into128 measurement cycles and use regis-ter shifting to perform the divisionrequired in the equation. You calculateeach charge measurement as an aver-age value from 32 current samples,which the microprocessor’s internalADC converts. One of the ADC’s mul-tiplexed input channels convertscharging current, and another convertsdischarging current. Thus, the equationfor remaining battery-charge capacityreduces to QREMQPREV QACC, whereQREM is the remaining battery charge,QPREV is its previously calculatedcharge, a plus sign indicates a netcharge, and a minus sign indicates a netdischarge.

As Figure 1 shows, the circuit com-

prises an eight-pin version Freescale’s(www.freescale.com) low-cost MC68-HC908QT2 microcontroller, IC3. Thevoltage across current-sampling resistorR1 reverses polarity depending onwhether the battery charges or dis-charges. Connected as identical-gainnoninverting and inverting amplifiers,respectively, IC2A and IC2B sense thevoltage developed across R1. Nonin-verting amplifier IC2A responds only toa positive voltage developed by a charg-ing current and delivers zero output fora negative input voltage developed bya discharge current. Inverting amplifi-er IC2B responds only to a negativeinput and delivers 0V for a positive-charging current. The outputs of bothop amps are positive and range from 0to approximately 5V and simplifydesign of the interface with the ADC’smultiplexed inputs. Using TexasInstruments’ (www.ti.com) TLC277 forIC2 offers the benefits of a small-pc-board footprint and a low input-offsetvoltage.

You calculate the sense resistor R1’svalue and the amplifiers’ gain, G, bydetermining the lowest and highestexpected charge and discharge currentsand applying the following equation:

Microcontroller simplifies battery-state-of-charge measurement

Figure 1 Measure a storage battery’s state of charge using only a few components.

CHARGESOURCE LOAD

LOAD-CONTROLCIRCUIT

IC3MC68HC908QT2_

_

+

+

DISCHARGE

R10.5

R41k

R21k

R39.09k

R510k

C10.33 F

D11N4001

C20.1 F

CHARGE 6

6

7

7

5

2

2

8

8

1

1

3

2

13

4

DATA

PA0

PA1

PA5

STORAGEBATTERY

IC2ATLC277

_

+

IC2BTLC277

_

+

IC178L05

Abel Raynus and Evgueni Freidline, Armatron International, Malden, MA

designideas

98 EDN | APRIL 27, 2006

where IMAX is the maximum dischargecurrent and VIN(MAX) is the maximumADC input. In this example, the max-imum charge and discharge currents areapproximately 1A.

Thus, for a 1A charge or dischargecurrent and a maximum ADC input of5V, you can choose a value of 0.5 forR1 and a gain of 10 or 100. Once youcalculate the battery’s charge capabili-ty, you can send the data to a hostprocessor or another destinationthrough a single-wire interface, SPI,

I2C, CAN (controller-area-network),or another industry-standard method(Reference 1). To maximize batterylife, you can use the microprocessor’soutput to control current that an exter-nal load draws.

Manufacturers generally ship lead-acid batteries fully charged to avoid sul-fation, and this design assumes that abattery starts in a fully charged state. Toaccommodate battery chemistriesother than lead acid, you must modifythe value of the battery’s maximum

charge capability that’s stored in a specialized firmware register. You can download the microprocessor’sfirmware from www.edn.com/060427di1.EDN

R E F E R E N C ERaynus, Abel, “Single wire con-

nects microcontrollers,” EDN, Oct 22,1998, pg 102, www.edn.com/archives/1998/102298/22di.htm#single.

A few years ago, manufacturersspecified their white, but dim,

LEDs for a maximum forward-currentrating of 20 mA. Today’s white LEDsdeliver more light and thus must oper-ate at ever-higher bias currents. Main-taining control of an LED’s bias pointwhile operating at high current near its maximum rating requires a newapproach.

The simplest and most commonmethod of biasing an LED involvesconnecting a resistor in series with theLED to limit the LED’s maximum cur-rent, but this method directly impactspower efficiency, which you define asthe ratio of power to the LED to thetotal input power. For a white LEDoperating at 350 mA, the correspon-ding forward-voltage drop across thediode is approximately 3.2V. A seriesresistor and LED connected to a 5Vpower source operates at 64% efficien-cy—that is, 3.2V for a 5V source. Thepower dissipates as heat, causing anaverage power loss in the series resistorof 36 mW at a forward current of 20mA, which is acceptable, but this fig-ure balloons to 630 mW at a forwardcurrent of 350 mA.

In addition, using a series resistorallows the diode’s bias point and thusits brightness to fluctuate as the

power-supply voltage and the ambienttemperature vary. Based on NationalSemiconductor’s (www.natsemi.com)LM2852 switched-mode bucking regu-lator, which features internal compen-sation and synchronous-MOSFETswitches that can drive loads as large as2A, the circuit efficiently provides con-stant-current drive to a high-currentLED and minimizes the effects of sup-ply-voltage and temperature variationson the LED’s brightness (Figure 1).

In this circuit, the LM2852 operatesat efficiency of approximately 93% anddirectly controls a step-down-regulatortopology that maintains a constantcurrent flow through LED1, which

potentiometer R1 adjusts. Current-to-voltage conversion taking place with-in the circuit’s control loop effective-ly regulates the circuit’s output current.In operation, the LM2852 compares itsinternal reference voltage with thevoltage from the divider formed by D1,R1, and R2 and drives the control loopto maintain a constant 1.2V at its volt-age-sense pin. Current through thevoltage divider is proportional to thecurrent through LED1, and the ratio ofthe currents tracks over the circuit’soperating-temperature range becauseD1 and LED1 exhibit approximately thesame forward-voltage temperaturecoefficient of 2 mV/C. Mounting D1and LED1 next to each other on the pcboard provides sufficiently close ther-mal coupling for temperature com-pensation.

With R1’s wiper fully clockwise, the

Switching regulator efficiently controls white-LED current

Figure 1 This circuit drives a high-current, white LED at 93% efficiency overinput voltage and temperature. Potentiometer R1 controls current throughLED1 and allows brightness adjustment. Diode D1 provides temperature compensation for LED1’s forward-voltage drop.

Clayton B Grantham, Agtech, Tucson, AZ

IC1LM2852Y-1.2

SGND PGND

3 10, 11

SNS

SWP_VIN

A_VIN

EN

SS

+

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2

1

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+CIN22 F

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1N4001

LED1LXHL-BW02+

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CCW

1

Although manufacturers offercrystal and ceramic resonators

and packaged oscillators for many fre-quencies, nonstandard frequencies maynot be readily available. When a uniqueintegrator application required a 2021-Hz fixed-frequency clock, the circuit inFigure 1 solved the problem andrequired only a few extra and inexpen-sive components. The heart of the oscil-lator comprises a small assembly-lan-guage process that exploits equalized,fixed-length branch loops with only 12instructions. A simple Visual Basic program, available at www.edn.com/

060427di2, provides a user-input win-dow that calculates the number of loopsnecessary to create the desired frequen-cy and also determines the requirednumber of individual instruction peri-ods needed to “top off” the duration ofthe output period (Figure 2).

Including Microchip’s (www.microchip.com) PIC12F508 8-bit microcon-troller, IC1, the circuit in Figure 1 usesonly four components. The microcon-troller operates at clock-crystal fre-quencies as high as 4 MHz and includesa configuration option that uses theIC’s internal 4-MHz oscillator, which is

accurate to 1% as the controller’sbase frequency. Another version of themicrocontroller, the PIC16F505, canoperate at clock-crystal frequencies ashigh as 20 MHz.

To calculate the constants to programthe microcontroller for the desired out-

current through D1 approaches 1 mA,and the current through LED1 averagesapproximately 500 mA. Adjusting R1counterclockwise reduces LED1’s for-ward current from 500 mA to 0A.

When scaling the values of R1 and R2for a different current-loop gain,decreasing the gain impacts the circuit’sconversion efficiency, and increasingthe gain makes the loop more sensitiveto component tolerances. To provide aremote brightness control, you canreplace mechanical potentiometer R1with a digitally programmed poten-tiometer. Luxeon (www.luxeon.com),the manufacturer of LED1, an LXHL-

BW02, specifies limits of 350-mA con-tinuous current and 500-mA peak-pulsed current. Figure 2 shows the cir-cuit’s efficiency versus variations ininput voltage. Note that the circuit’sefficiency increases as input voltagedecreases, which helps extend operat-ing time in battery-powered-systemapplications.

As temperature fluctuates, the cur-rent through LED1 varies less than 3%over the temperature range, a factor-of-three improvement over a series-resis-tor current-limiting circuit (Figure 3).Although more complex than a singleresistor, the circuit in Figure 1 requires

only a few components. For L1, this pro-totype uses Coilcraft’s (www.coilcraft.com) MSS5131-103 surface-mountinductor rated for 10 H.

National Semiconductor’s datasheet for the LM2852 outlines criteriafor selecting capacitors CIN, CSS, andCOUT. For efficient heat removal, thecircuit’s pc board should include gen-erous copper-mounting pads and tracesfor IC1 and LED1. At a forward currentof 350 mA, LED1 dissipates 1.1W, soconsult the manufacturer’s data sheet toreview its thermal-design recommen-dations.EDN

Programmed reference oscillatorgenerates nonstandard clockfrequencies

designideas

Figure 1 Delivering a fixed clock fre-quency, this preprogrammed oscil-lator uses few components.

100 EDN | APRIL 27, 2006

Figure 2 Circuit efficiency versus input voltage shows anincrease in efficiency for increasing LED current anddecreasing input voltage.

3 3.5 4 4.5 5 5.5

100

95

90

85

80

EFFICIENCY(%)

INPUT VOLTAGE (V)

~100 mA~300 mA~500 mA

LED1 CURRENT

Figure 3 Current through the LED varies less than 3%over an operating-temperature range of 0 to 75C.

0 15 30 45 60 75

360

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CURRENT(mA)

TEMPERATURE(C)

IC112F508

8 VSS

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CLOCK OUTPUT

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C215 pF

X1

William Grill, Honeywell BRGA, Lenexa, KS

designideas

102 EDN | APRIL 27, 2006

put frequency, you use the Visual Basicprogram, editing the clock frequency of4 MHz in this example if necessary.Next, you enter the clock’s frequencyerror in percentage points or parts permillion and the desired output fre-quency in hertz. When you click on the“Evaluate” control, the program com-putes the high- and low-state coeffi-cients, the number of appendedinstructions, and the output’s dutycycle. The program also calculates themaximum initial percentage error ofthe output frequency. The controller’sinstruction-execution times and clockfrequency impose constraints on thedesired output frequency, duty cycle,and frequency error. For the 2021-Hzclock in this application and a 4-MHzclock frequency, the program calculatesthe coefficients and number of discreteinstructions as 20, 21, and three,respectively. Before compiling thecode and writing the results to themicrocontroller’s internal flash memo-ry, you transcribe the coefficients into

the microcontroller’s assembly-lan-guage program.

The controller’s assembly-languagelisting, at www.edn.com/060427di2,uses only 40 instructions, and its imple-mentation leaves three of the con-troller’s pins unused but available for auser-defined enable input or for select-ing one of several preset output fre-

quencies or coefficients. You can reducethe pc-board area the basic design usesif you select a microcontroller thatoccupies a smaller package, such as six-lead SOT-23 versions of thePIC10F200 or PIC10F220, and use itsinternal 4-MHz clock oscillator insteadof an external crystal.EDN

Figure 2 Use this Visual Basic program to calculate programming coefficientsfor the clock circuit.

Many process-control sensors,such as thermistors and strain-

gauge bridges, require accurate bias cur-rents. By adding a single current-set-ting resistor, R1, you can configure volt-age-reference circuit IC1 to produce aconstant and accurate current source(Figure 1). However, the source’serrors depend on the accuracy of bothR1 and IC1 and affect measurementaccuracy and resolution. Although youcan specify high-precision resistorswhose accuracy exceeds that of mostcommonly available voltage-referenceICs, the voltage reference’s error dom-inates this current source’s accuracy.Although the manufacturer mini-mizes the voltage reference’s tempera-ture sensitivity and output-voltageerror, sensitivity to power-supply vari-ations can affect its accuracy, especial-

ly in process-control applications thatmust operate over a wide range of sup-ply voltages.

A cascode-connected pair of JFETs,Q1 and Q2, form a constant-currentsource that minimizes the referencecircuit’s sensitivity to supply-voltagefluctuations and extends IC1’s operat-ing voltage beyond its 5.5V maximumrating. In addition, Q1 and Q2 effec-tively increase the current source’sequivalent resistance from a fewmegohms almost into the gigohmrange. In the circuit’s Norton model,equivalent resistance represents theparallel resistance across an ideal cur-rent source.

An N-channel JFET operates as adepletion-mode device at its maxi-mum saturated drain current when itsgate-to-source bias voltage is 0V. In

contrast to a depletion-mode MOS-FET that requires a gate-bias voltageto conduct, the JFET operates in adefault on-state and requires gate-biasvoltage to cut off conduction. As itsgate-to-source voltage becomes morenegative with respect to the source, aJFET’s drain current goes to zero at thepinch-off voltage. The JFET’s draincurrent varies approximately with itsgate bias: IDIDSS(1VGS/VP)

2,where ID is drain current, IDSS is the sat-

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

MAY 11, 2006 | EDN 75

JFET cascode boosts current-source performanceClayton B Grantham, Tucson, AZ

D Is Inside

76 Microcontroller delivers voltage-multiplied dc power

80 Low-dropout linear regulatorsdeliver constant currents

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 A pair of cascode-connected JFETs reduces theeffects of power-supply-voltage fluctuations on a currentsource’s accuracy.

POWER SOURCE

POWER RETURN

Q1 Q2

VIN VREF

EN GND

IC1LM4132-1.8V

C10.1 F

D D

S S

G G

MMBF4393

ISOURCE = (VREF/R1) IGND.

IGND

R11k

0.1%25 PPM/C

R2SENSOROR LOAD

REQUIRINGCONSTANT-CURRENT

DRIVE

POWER-SUPPLYINPUT

3

1.5

1

2

2.5

3

3.5

4

9 15 21 27 33 39POWER-SUPPLY VOLTAGE (V)

CURRENT-SOURCEOUTPUT

(mA)

R1=510

R1=750

R1=1k

Figure 2 Setting R1 to values of 1 k, 750, and 510delivers output currents of approximately 1.8, 2.5, and 3.6mA that are insensitive to a wide range of power-supplyvoltages.

designideas

76 EDN | MAY 11, 2006

The combination of an exter-nal circuit and a low-voltage

microcontroller occasionally requiresa significantly higher power-supplyvoltage. You can use either an exter-nal boost converter to increase thelogic supply or a buck converter todecrease an even higher voltage.However, you can alternatively usethe microcontroller to create a high-er voltage. For example, some of Cy-press Semiconductor’s (www.cypress.com) PSOC (programmable-system-on-chip) microcontrollers include aconfigurable comparator block that,with a PWM block, can form theheart of a simple inductor-based boostconverter (Figure 1). A few externalcomponents implement a 40V powersupply (Figure 2). When the feedbackvoltage you apply to Pin 3 (P0.3)exceeds the comparator’s software-defined threshold voltage, the com-parator shuts off the PWM stage.When the voltage drops below thethreshold, the comparator re-enablesthe PWM block and thus regulatesthe output voltage. The voltage reg-ulator uses only hardware blocks and

VCC

P0.6

P0.7

P0.5

P0.3

P0.1

P2.7

P2.5

P2.3

P2.1

SMP

P1.7

P1.5

P1.3

P1.1

GND

P0.4

P0.2

P0.0

P2.6

P2.4

P2.2

P2.0

XRES

P1.6

P1.4

P1.2

P1.015

16

17

18

19

20

21

22

23

24

25

26

27

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

5VINPUT

IC1CY8C27443

R11k400 kHz

R27.3k

R31k

D1SCHOTTKY

DIODE

Q1IRFD110

L122 H

C110 F

D

S

G

5V

+

40VOUTPUT

Microcontroller delivers voltage-multiplied dc powerAaron Lager, Masterwork Electronics, Santa Rosa, CA

Figure 1 Use a pair of a PSOC microprocessor’s internal blocks and a fewexternal components to build a voltage-boost converter. Use a Schottkydiode rated for a peak-inverse voltage of 100V for D1. The PSOC’s remainingpins are available for application support.

urated drain current, VGS is the gate-to-source voltage, and VP is the pinch-offvoltage.

Assume that IC1’s output voltage,VREF, remains constant at 1.8V. Be-cause the output voltage drives Q2’sgate, IC1’s input voltage, VIN, equalsVREFVGS(Q2),or 1.8V(1.2V)3V.Thus, Q2’s gate-to-source voltage restsat its nominal pinch-off voltage of1.2V and varies in step with smallchanges in current source. As thepower-supply voltage varies from 3V tomore than 30V, then the input voltageremains almost constant, as you wouldexpect, because VREF also remains con-stant. The cascoded-FET configurationincreases the current source’s Nortonequivalent resistance beyond that ofthe voltage reference and R1 alone. You

can use a single JFET, but stacking twoJFETs further enhances the circuit’seffective impedance. Note that IC1doesn’t degrade accuracy because theJFETs hold IC1’s input voltage virtual-ly constant, and IC1 effectively cancelsinitial gate-to-source-voltage varia-tions and temperature effects that Q1and Q2 introduce.

Negative feedback in the Kirchhoff-voltage loop that comprises VIN, VREF,and VGS(Q2) allows the drain current toreach an equilibrium bias point that sat-isfies Q2’s transfer equation. Compris-ing the sum of (VREF/R1) plus IC1’sinternal “housekeeping” current, IGND,Q2’s drain current remains constant.Adding Q1 reduces the effects of Q2’soutput impedance to insignificance.Adjusting the value of R1 varies the cir-

cuit’s output current over a useful rangeof 200 A to 5 mA, with Q2’s saturat-ed-drain-current specification imposingan upper limit. If you select a JFET withhigher saturated drain current, makesure not to exceed Q1’s maximumpower dissipation.

Note that the circuit’s lower power-supply-voltage limit must exceed the cir-cuit’s compliance voltage, 3V, plus thevoltage drop that the sensor introduces:ISOURCER2. The circuit’s upper power-supply voltage must not exceedISOURCER230V. For example, supply-ing a current of 2.5 mA to a 1-k pres-sure-sensor bridge, R2, limits the power-supply-voltage range to 5.5 to 32.5V.The circuit’s output current varies lessthan 1 A over a wide range of power-supply voltages (Figure 2).EDN

designideas

78 EDN | MAY 11, 2006

thus is immune to the effects of otheractivities taking place in the PSOC’sCPU.

However, some microcontrollerslack a built-in comparator. For thesedevices, the Villard Cascade circuitoffers a less expensive alternative to anexternal boost-voltage converter (Ref-erence 1). Most engineers who arefamiliar with the Villard Cascadeassociate it with high-voltage appli-cations and do not envision it as a low-voltage dc-supply technique. The cir-cuit in Figure 3 requires an ac inputsource that you can easily simulateusing a PSOC’s internal PWM andinverter blocks. A square-wave outputvoltage appears on Pin 1, and aninverted version of the same squarewave appears on Pin 2. The voltagedifference between the two pins ap-plies an ac square-wave voltage to thecascade.

Figure 4 shows how to configure aPSOC’s internal blocks to drive thecircuit in Figure 3. The PSOC’s out-put multiplexer inverts the PWM’soutput and drives Port_0_5, andPort_0_6 receives the PWM’s nonin-verted output signal. Again, thePSOC uses hardware blocks to drivea Villard Cascade voltage multiplier,and the circuit produces an outputvoltage without regard to CPU activ-ity. For an input voltage, VIN, a VillardCascade of N stages delivers an outputvoltage of VIN2N. One stage com-prises two diodes and two capacitors(Figure 5). However, the series-con-nected capacitors and diodes intro-duce voltage drops that limit the out-put current available from a VillardCascade. In addition, the followingequation imposes a practical limit thatgoverns the cascade’s output voltage:

where V is the output-voltage drop, fis the input frequency, C is the capac-itance, I is the output current, and Nis the number of stages.

Both boost circuits can supply onlymodest amounts of current, especial-

Figure 2 A pulse-width modulator (top) and a comparator (bottom) can operateindependently of other PSOC functions. Unconnected pins are available foradditional functions.

Figure 3 A few diodes and capacitors form a Villard Cascade voltage multiplier.

VCC

P0.6

P0.7

P0.5

P0.3

P0.1

P2.7

P2.5

P2.3

P2.1

SMP

P1.7

P1.5

P1.3

P1.1

GND

P0.4

P0.2

P0.0

P2.6

P2.4

P2.2

P2.0

XRES

P1.6

P1.4

P1.2

P1.015

16

17

18

19

20

21

22

23

24

25

26

27

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

5VINPUT

IC1CY8C27443

C11 nF

C31 nF

C21 nF

C41 nF

D1BAV21

D2BAV21

D3BAV21

D4BAV21

HIGH-VOLTAGEOUTPUT

Linear voltage regulators offer asimple method of producing a

constant current by connecting a fixedresistor between the regulator’s outputand ground nodes. The regulator’s con-stant output voltage produces a con-stant current through the resistor. Youcan use the basic circuit as either ahigh-side or a low-side current source.The high-side current source uses a pos-itive-output linear voltage regulator,IC1, a Maxim MAX1818, to provide aconstant current of 25 mA to the loadresistance (Figure 1). The designimposes two conditions: First, the volt-age between IC1’s VCC and ground ter-minals must not exceed 5.5V. Second,the voltage between IC1’s input andground terminals must meet or exceed2.5V, the minimum voltage for properoperation. To satisfy these conditions,choose an output-resistance value thatallows 2.5 to 5.5V between input and

ground and provides a fixed output of1.5V across the output resistance at thedesired load current.

For example, if you use the circuit todrive a constant current through a 100maximum load resistance while apply-ing 5V VCC between IC1 and ground, thecircuit functions properly when ROUTequals or exceeds 60. This value allowsa maximum programmable current of1.5V/60, or 25 mA. The voltage acrossIC1 then equals the allowed minimum:5V(25 mA100)2.5V. Availablein six-pin SOT-23 packages, the MAX-1818 can source as much as 500 mA.

The low-side current-source circuitdraws a constant current of 2.5V divid-ed by the output resistance through theload resistance (Figure 2). In this exam-ple, IC1, a MAX1735 linear negative-voltage regulator, provides a fixed out-put voltage of 2.5V. As in Figure 1,ensuring a voltage of 2.5 to 6.5V be-

designideas

80 EDN | MAY 11, 2006

ly when they receive power from a 5or 3.3V source. However, you cancharge a high-value storage capacitorfrom the boost circuit’s output anddrive a load that presents a low dutycycle (for example, solenoid actua-tion).EDN

R E F E R E N C E“Jochen’s High Voltage Page,”

www.kronjaeger.com/hv/hv/src/mul/.1

Figure 4 To drive a Villard Cascade multiplier, a PWM block and an inverterblock deliver a balanced ac voltage with respect to ground.

HIGH-VOLTAGEOUTPUT

D2BAV21

D1BAV21

C21 nF

C11 nF

BALANCEDAC

INPUTVOLTAGE

+

+

Figure 5 An isolated multiplier stageeases analysis.

Low-dropout linear regulators deliver constant currentsBudge Ing, Maxim Integrated Products Inc, Sunnyvale, CA

tween IC1’s ground and input terminalsrepresents the only precaution for itsproper operation. To satisfy that condi-tion, choose an output-resistance valuethat allows 2.5 to 6.5V between ground

and the input. When using the circuitto draw current through a maximumload of 100 with VCC at 5V, the out-put resistance should exceed 100,which provides a maximum program-mable current of 2.5V/10025 mA,which in turn produces a minimum rec-ommended voltage across the device of5V(25 mA100)2.5V. TheMAX1735 can source as much as 200mA and occupies a five-pin SOT-23package.

In addition to the programmed loadcurrent, both configurations allow theregulator’s quiescent current to flowthrough the load and introduce a sourceof error that varies with the voltage youapply between the regulator’s input andground connections. You can minimizethe error by choosing a voltage regula-tor that draws low quiescent current orwhose quiescent current remains con-stant through the operating range andallows you to compensate the error byadjusting the value of the output resist-

ance. Quiescent currents for thedevices in figures 1 and 2 typicallyaverage 130 A and vary less than 40A for a regulator input-voltage rangeof 2.5 to 5V.EDN

designideas

82 EDN | MAY 11, 2006

IC1MAX1818EUT15

IN

VCCIN

SHDN GND

SET

OUT

POWER OK

+CIN4.7 F

COUT10 F

ROUT

+NC

RLOAD ILOAD

IOUT

Figure 1 This high-side constant-current sourcedelivers load current of 2.5V divided by the out-put resistance, provided that you choose theoutput resistance to ensure that the voltagebetween the regulator’s input and ground termi-nals is at least 2.5V.

+

+

IOUT

ILOAD

ROUT

VCCIN

CIN4.7 F

COUT10 F

IC1MAX1735EUK25

RLOAD

OUTGND

SET IN SHDN

Figure 2 As in Figure 1, this low-sideconstant-current source draws a loadcurrent of 2.5V divided by the outputresistance through the load resist-ance, provided that you select theoutput resistance to make the voltagedifference between IC1’s input andground terminals at least 2.5V.

You use a JFET’s self-biasingcharacteristics to build a dc/dc

converter that operates from powersources such as solar cells, thermopiles,and single-stage fuel cells, all of whichdeliver less than 600 mV and some-times as little as 300 mV. Figure 1shows the drain-to-source characteris-tics of an N-channel JFET under zero-bias conditions, which you can produceby connecting its gate and sourcetogether. Applying 100 mV causes acurrent of 10 mA to flow through thedevice, increasing to 30 mA at 350 mV.Exploiting the JFET’s ability to conductsignificant current at zero bias makes itpossible to design a self-starting, low-input-voltage converter.

The circuit can supply 5V at currents

as large as 2 mA—enough to servemany micropowered applications or toprovide auxiliary bias for a higher powerswitched-mode voltage regulator. At300-mV input, the circuit starts up atload currents of 300 A. A load currentof 2 mA requires an input of 475 mV.

In Figure 2, Q1, a parallel-connect-ed pair of Philips Semiconductor’s(www.semiconductors.philips.com)BF862 JFETs, and Coiltronics’ (www.coiltronics.com) Versa-Pac trans-former, T1, form an oscillator in whichT1’s secondary winding provides feed-back to Q1’s gate. When you first applypower, Q1’s gate rests at 0V, and draincurrent flows through T1’s primarywinding. T1’s phase-inverted secondarywinding responds by delivering a neg-

ative voltage to Q1’s gate, which turnsoff Q1 and interrupts current flowthrough T1’s primary winding. In turn,T1’s secondary voltage collapses, andsustained oscillations begin. Althoughthe BF862’s published specifications donot cover the device’s internal geome-try, the device has a low on-resistanceand maintains a low gate-turn-onthreshold voltage. Using a pair of par-allel-connected JFETs for Q1 ensuresthe low saturation voltage for operationat low power-supply voltages.

Rectifying and filtering the positive-going flyback-voltage impulses on Q1’sdrain produce a dc voltage across capac-itor C1. To assist the circuit’s start-up,a P-channel MOSFET, Q2, whichrequires a gate-to-source voltage ofapproximately 2V for conduction, ini-tially isolates the output load from therectifier. When Q2 conducts, the out-put voltage increases toward 5V. Com-parator IC1, a Linear Technology (www.linear.com) LTC-1440, draws powerfrom Q2’s source and imposes output-voltage regulation by comparing itsinternal voltage reference with a sam-ple of the output voltage. The output

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

MAY 25, 2006 | EDN 91

JFET-based dc/dc converter operates from 300-mV supplyJim Williams, Linear Technology Corp, Milpitas, CA

D Is Inside

94 Configurable logic gates’Schmitt inputs make versatile monostables

98 Stealth-mode LED controls itself

100 Data-acquisition system cap-tures 16-bit voltage measurementsusing the USB

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 At 100 mV between drain and source (horizontal axis), the draincurrent reaches 10 mA (vertical axis) and increases to 30 mA at 300 mV.

designideas

92 EDN | MAY 25, 2006

Figure 2 A pair of parallel-connected JFETs allows this dc/dc converter to operate from power sources that supply as littleas 300 mV.

from IC1 varies Q1’s on-time throughQ3 to close the control loop and main-tain output-voltage regulation. Figure3 shows the ripple voltage present atthe power supply’s output. When theoutput voltage decays, comparator IC1switches (Trace B, middle) and allowsQ1 to oscillate. The resulting flybackevents at Q1’s drain (Trace C, bottom)restore the output voltage.

Using Q3 as a simple but effectiveshunt control for Q1’s gate voltageresults in a 25-mA quiescent-currentdrain from the power source. A modi-fication reduces the quiescent drain to1 mA (Figure 4). Inserting switch Q4in series with T1’s secondary windingmore efficiently controls Q1’s gate.Bootstrapping the voltage across T1’ssecondary winding produces negative-turn-off-bias voltage for Q4. Figure 5illustrates how to connect T1’s wind-

_

+

++

NOTES:1. USE 1%-TOLERANCE METAL-FILM RESISTORS FOR R1 AND R2.2. CONNECT T1 AS SHOWN IN FIGURE 5.3. Q1 COMPRISES PHILIPS BF862 JFETs CONNECTED IN PARALLEL.

IC1LTC1440

C40.001

C16.8 F

R3100 R2

1.21M

R13.83M

C30.01 F

C2100 F

VN2222L

TP0610LQ1

T1

GG

S

S

D

D

G

S

D

D11N5817

D2BAT-85

7

7

6

6

3

3

4

5

5

8

1.18VREFERENCE

OUT

0.3 TO1.6VIN

5 VOUT,2 mA MAXIMUM

PRIMARY

SECONDARYQ2

Q3

Figure 3 The dc output (Trace A), comparator IC1’s output, and the voltageat Q1’s drain (Trace C) have a horizontal-deflection factor of 5 msec.

designideas

94 EDN | MAY 25, 2006

ings. When Q4 switches off, it inter-rupts the current flowing in T1’s sec-ondary winding and drives T1’s Pin 5positive. Without diodes D4 and D5, the

peak voltage would approach 15V andreverse-bias Q4, an undesirable condi-tion. Under normal operating condi-tions, excursions of approximately

0.8V appear at Pin 5, necessitating theuse of two series-connected diodes toclamp the voltage at a safe level. Zenerdiode D3 holds off bias-supply loadingto aid start-up during initial powerapplication.EDN

TO R3

TO VIN

T1

TO Q1 DRAINS

TO Q1 GATES

5

2

3

6

4

112

911

810

7

SECONDARYPRIMARY

Figure 5 Comprising six independ-ent windings that offer more than500 configurations, Coiltronics’VP1-1400 serves as a combinationfeedback and flyback transformer inthis application. Connect the wind-ings as shown.

R21.21M

1% METALFILM

R5470k

R13.83M

1% METALFILM

R41M

0.3 TO1.6VIN

Q2TP0610L

Q1BF862

D11N5817

Q4BF862

C30.01 F

C2100 F

D

G

S

C16.8 F

C510 F

C41 F

1N7515.1V

5VOUT, 2 mA MAXIMUM

IC1LTC1440

3

4

65

1

8

NOTES: 1. USE 1%-TOLERANCE METAL-FILM RESISTORS FOR R1 AND R2.2. CONNECT T1 AS SHOWN IN FIGURE 5.3. Q1 COMPRISES PHILIPS BF862 JFETs CONNECTED IN PARALLEL.4. T1 = COILTRONICS VP1-1400.

7Q3TP0610L

D2

D31N4148

D

5

7

3

6

S

G

D41N4148

D61N4148

D51N4148

1.18V REFERENCEOUTPUT

12V

T1

R351

D

DS

S

G

G

+

+

+

+

Figure 4 Adding Q3, Q4, and the bootstrapped negative-bias generator compris-ing D2, D3, and C4 reduces the circuit’s quiescent current from 25 mA to 1 mA.

You can assemble a pulse-gener-ation circuit from a simple

Schmitt-input AND gate plus a resis-tor-capacitor timing network. Howev-er, if you need a logic function that’s nota standard catalog item, you need aSchmitt-input gate or inverter and anadditional logic gate. Drawing from anearlier Design Idea (Reference 1) anda recent design requirement for addingpulse-generation functions to a crowd-ed pc board, I searched Fairchild Semi-conductor’s Web site (www.fairchildsemi.com) for small-footprint Schmitt-

input logic gates and found only “oldfaithfuls”—familiar Schmitt-inputAND gates and Schmitt buffers.

Disappointed, I investigated otherlogic offerings from Fairchild and stum-bled across a section of the Web sitethat describes “configurable logicgates.” Lo and behold, I suddenly real-ized I was looking at the solution to myproblem. The NC7SZ57 and NC7SZ-58 (Reference 2) comprise tiny, six-pinsurface-mount packages that you canconfigure as inverters or as AND, OR,or XOR gates, all of which allow the

inversion of one input. These devicesfeature inverted outputs, overvoltage-input tolerance, and high current drive.

Every input has hysteresis, makingthese devices ideal for timed pulse gen-eration. A design that combines digi-tal logic with analog interfaces oftenrequires timed pulses and delays, alongwith pulse shorteners and stretchers.For applications in which exact pulsetimes are not critical, the added featureof Schmitt inputs allows the delay ofone input using an RC (resistance-capacitance) timing network. Whenthe slowly changing RC circuit’s outputcrosses the analog-level upper- or lower-trip-point thresholds, the Schmitt fea-ture converts the slowly rising andfalling voltages to fast digital edges.

Texas Instruments (www.ti.com)

Configurable logic gates’ Schmittinputs make versatile monostables

Glenn Chenier, Allen, TX

offers functional equivalents—the SN-74LVC1G57 and SN74LVC1G58(Reference 3). Both companies’ de-vices offer upper- and lower-trip-point-voltage thresholds averaging 37 and63%, respectively, of VCC, or approxi-mately one RC time constant on therising or the falling edges. According tothe published data sheets from themanufacturers’ Web sites, Texas In-struments’ versions impose somewhattighter tolerances on the analogthreshold levels and thus delivertighter timing tolerances than do theFairchild parts.

For digital-analysis purposes, anyvoltage below the upper trip point fora rising edge effectively represents alogic zero, and any voltage above thelower trip point for a falling edge rep-resents a logic one. These conditionsare true only after the input crosses arespective trip point, such as a risingedge that approaches but never crossesthe upper trip point. This voltageremains a logic zero, even if the volt-age then drops back to ground poten-tial on its falling edge.

Figure 1a shows some typical circuitimplementations. Note that these cir-cuits lack some of the niceties of gen-uine monostables. For example, a cir-cuit doesn’t retrigger until after its RCnetwork has stabilized or about fivetime constants have elapsed. The RCtime constant must be five times short-er than the time between triggeringevents. Devices from the SN74LVC-1G57 family produce the waveforms inFigure 1b, and circuits using the SN-74LVC1G58-family devices producethe inverse of these waveforms. Thecircuits’ operation is straightforward.The RC circuits delay one input, sothat the inputs momentarily rest atopposite states. When one RC timeconstant elapses, the delayed voltagecrosses the Schmitt upper- or lower-trip-point thresholds, and the delayedinput catches up to the straight-through input.

Of unusual interest and unlike theusual variety of monostable that trig-gers only from a voltage transition inone direction, the XOR implementa-tion functions as a monostable trig-

gered by both the rising and thefalling edges, enabling it to functionas a frequency doubler for generatingstrobe pulses on rising and fallingclock edges. You can make any invert-ing-gate configuration into an oscil-lator by feeding back its inverted out-put to an RC-delayed Schmitt inputand enabling the gate’s remaininginput. However, once the XOR oscil-lator’s remaining gate switches off theoscillation, the gate’s output statehangs at either a one or a zero to pro-duce a truly random state derivedfrom the oscillation’s nonsynchronousrelationship to the timing of the dis-abling input.EDN

R E F E R E N C E SRoche, Stephan, “Add a Schmitt-

trigger function to CPLDs, FPGAs,and applications,” EDN, Oct 13,2005, pg 104, www.edn.com/article/CA6262539.

“NC7SZ57/NC7SZ58, TinyLogicUHS Universal Configurable 2-InputLogic Gates,” Fairchild Semiconduc-tor, April 2000, www.fairchildsemiconductor.com/ds/NC/NC7SZ57pdf.

“SN74LVC1G57 ConfigurableMultiple-Function Gate,” Texas Instru-ments, November 2002, http://focus.ti.com/lit/ds/symlink/sn74lvc1g57.pdf.

designideas

Figure 1 One gate plus an RC network (a) can deliver a range of usefultimed outputs (b).

96 EDN | MAY 25, 2006

INPUT

INPUT

PIN 3 VCC

PIN 5 VCC

R

C

1

6

INPUT

PIN 1 GND

PIN 2 GND

PIN 3 VARIES AS SHOWN

R

C

3

6

INPUT

PIN 3 GND

R

C

1

6

INPUT

PIN 3 GND

R

C

6

1

INPUT

R

C

1, 3

6

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUTR

C

1, 3

6

DEVICE CONNECTIONS

UPPERTRIP POINT

LOWERTRIP POINTS

RC CIRCUIT'S OUTPUT

OUTPUTS'DELAYED RISING

EDGE

DELAYED FALLINGEDGE

FALLING-EDGEPULSE

RISING-EDGEPULSE

FREQUENCYDOUBLER

GATEDOSCILLATOR

RANDOM-STATE

GENERATOR

4

4

4

4

4

4

(a) (b)

1

2

3

Since the LED’s invention morethan 30 years ago, its emission

efficiency has steadily increased, and,although it may surprise you, theincreased conversion efficiency worksin two directions. Certain bright, effi-cient LEDs, such as Hewlett-Packard’s(www.hp.com) HLMP-EG30-NR000,a red emitter molded in clear encapsu-lation, also exhibit significant photo-voltaic action. The circuit in Figure 1shows how you can put an LED’s pho-tovoltaic characteristics to work.Using the same components, older, redLEDs also function but with lower lightoutput in this circuit. This Design Ideacircuit describes an LED that controlsitself by determining whether it’s on oroff without the assistance of any lightsensor other than its own characteris-tics. When you darken the LED, itturns on, and, when you illuminate it,

it turns off. The circuit’s main compo-nents comprise LED D1, micropoweroperational amplifier IC1, one-shotIC2A, and transistor switch Q1 to con-trol current through the LED.

When dark, the LED produces nophotovoltaic current. When moderatelighting, such as that in an office or alab, illuminates it, it generates 50 to100 mV into a 4.7-M load resistor.Comparator op amp IC1 compares thevoltage that the LED produces with athreshold reference voltage of approx-imately 50 mV. You can vary the cir-cuit’s sensitivity threshold by alteringthe values of resistors R1 and R2 in thevoltage divider that connects to IC1’sPin 2.

When ambient light decreases, theLED produces less voltage, and, whenthe voltage falls below the 50-mVthreshold, the op amp’s output goes low

and triggers one-shot IC2A. The one-shot turns on transistor Q1 for an inter-val, lighting the LED for approximate-ly 3 msec until the one-shot’s outputgoes low. In a darkened room, the cyclerepeats at a 200-Hz rate, and the LEDblinks repeatedly with short off periods.At high flash rates, the LED appears tobe continuously on.

The circuit’s current drain in the day-light state mainly comprises the currentdriving the reference-bias network:3.6V/162 k22 A. In both day andnight modes, with the LED drawing afew milliamperes when illuminated, abattery that can deliver 1 Ahr wouldpower the circuit for a couple ofmonths. You can reduce the current byincreasing the values of R1 and R2.Given the circuit’s low and intermit-tent current drain in a well-lightedenvironment, a 1-Ahr lithium cell’sservice life should approach its shelflife.EDN

Stealth-mode LED controls itself

designideas

Howard Myers, Greensboro, NC

Figure 1 An efficient LED forms the heart of a light-sensitive “mystery lamp” that contains no apparent photodetector.

98 EDN | MAY 25, 2006

R1160k

R4470

R510kQ1

2N2907

R6100kVCC

VSS

C10.22 F

IC1OP-90

R22.2k

R34.7M

D1RED LED

DETECTIONTHRESHOLD

VOLTAGE

LED SEESLIGHT

LED SEESDARKNESS2

35

44

67

16 3

7

3.6VLITHIUM

CELL

2

8

GND

CXRX

QRESET

1

11

14

NC

NC

NC

10

9

12

15 13

IC2A½MC14528

IC2B

REPEATED ONE-SHOTPERIODS WHEN LED

SEES DARKNESS

3.6VWHEN LEDSEES LIGHT

ONE-SHOT

0V

NOTE: CONNECT IC2B'S UNUSED INPUTS TO GROUND.

The USB has become the inter-face of choice for connecting to

PCs. Available on all relatively modernPCs, the USB offers a standard con-nector and can supply power to periph-erals at 5V and as much as 100 mA ofcurrent. The circuit in Figure 1 com-bines Maxim’s (www.maxim-ic.com)MAX1168, a low-power, 16-bit ADC,with a small USB-interface module to

make a simple, eight-channel, 16-bitmeasurement system. The MAX1168includes eight input channels, an SPI(serial-peripheral-interface) port, a4.096V reference, and a clock oscillator.The MAX1168 operates from a 5V sup-ply and can convert individual channels,execute multiple conversions on onechannel, or scan the channels sequen-tially and store measured data on-chip.

Based on a Cypress (www.cypress.com) CY7C63743 controller, USBmi-cro’s (www.usbmicro.com) U421 USB-interface module provides as many as 16I/O lines and an option to use some ofthose lines as an SPI port at selectableclock rates of 62.5 kHz, 500 kHz, 1 MHz,or 2 MHz. Firmware on the U421 allowsgeneric access to SPI read-and-writedevices, and the device’s general-purposeI/O lines can serve as slave-select linesfor addressing multiple SPI devices. OneI/O line controls the MAX1168’s chip-select input. When you use it with an

designideas

Figure 1 This simple data-acquisition system provides eight channels of 16-bit data to a host computer through a USBinterface.

100 EDN | MAY 25, 2006

Data-acquisition system captures 16-bitvoltage measurements using the USB

Terry Millward, Maxim Integrated Products Inc, Blonay, Switzerland

_

+

MAX4230

0.22 F

100 pF

100 pF

100 pF

100 pF

100 pF

100 pF

100 pF

100 pF

AVCCAVCC

AVCC DVCC

_

+

MAX4230

0.22 F

AVCC

_

+

MAX4230

0.22 F

AVCC

_

+

MAX4230

0.22 F

AVCC

_

+

MAX4230

0.22 F

10 F0.1 F 0.1 F

1 F 0.1 F

AVCC

_

+

MAX4230

0.22 F

AVCC

_

+

MAX4230

0.22 F

AVCC

_

+

MAX4230

0.22 F

AVCC

IC100MAX1168

IC101USBMICRO

U421

FB2

AIN0

DSEL

DSPR

DSPX

EOC

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

REF REFCAP AGND AGND DGND DGND

5VUSB

FB1

10

150 F0.1 F 0.1 F

51

DOUT

DIN

SCLK

CS

PA.0

PA.6/SPI MISO

PA.5/SPI MOSI

PA.7/SPI SCK

PB.0

USB D

USB D

NC

J1USB

CONNECTOR

USB5V 1

2

3

4USB

DGND

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

NOTE:RESISTOR-DIVIDER PAIRS ARE PRECISION-MATCHED, 100-k MAX5490s.

HID (human-interface de-vice), the U421 USB con-troller can transfer data at ratesas high as 800 bytes/sec. Withadditional filtering to reducenoise, the USB port provides5V power to the circuit.

The MAX1168’s sample-and-hold circuit must acquirethe input voltage and chargeits 45-pF holding capacitor in3 sec and thus requires a fastamplifier to minimize acquisi-tion errors. Available in dualand quad versions, the MAX-4230 provides a 10-MHzbandwidth, 2V/sec slew rate,rail-to-rail inputs and outputs,and the ability to operate froma 5V rail or from voltages aslow as 2.7V. The MAX4230’sbias current—typically, 50 pA—allowssignificant input impedance withoutaffecting accuracy.

To provide protection from over-voltages and apply input-voltage scal-

ing, each buffer amplifier’s input in-cludes a 100-k precision-matchedresistive divider. This application usesMaxim’s MAX5490VA10000 10-to-1dividers, which provide a scaling factor

of 1/11, to allow maximum read-able inputs of 45V at resolu-tions of 687.5 V.

Written in Microsoft’s Visu-al Basic.Net, Standard Edition,the evaluation software pro-vides commands to the U421through the USBm.dll DLL(dynamic-linking-library) file.The demo program sets theMAX1168 to scan all eightchannels and display theresults. When you run the pro-gram, the Visual Basic formallows you to set the referencevoltage to allow for the inputdivider, select the scan time,and enable any of the eightinput channels for screen dis-play (Figure 2). You can down-load the evaluation software at

www.maxim-ic.com/MAX=1168DI.EDN

AC K N OW L E D G M E N TThanks to Robert Severson of USBmicrofor his help with the interface.

designideas

Figure 2 User-interface software for the data-acquisi-tion system allows selection of operating parameters.In this image, the lower three channels are unselectedand hence are not visible in the display.

102 EDN | MAY 25, 2006

You can use the circuit in Figure1 to obtain a low regulated volt-

age, such as 5V dc, from a higher volt-age, rectified, sinusoidal voltage sourcewithout resorting to an electricallynoisy dc/dc converter or wasting wattsin a dropping resistor. This applicationrequires a regulated 5V-dc source, buta transformer supplies 18Vrms to a full-wave bridge rectifier. During thecharging phase, two equal-value elec-trolytic capacitors, C1 and C2, receivecharging current when connected inseries through forward-biased diodes D1and D2. An enhancement P-channelMOSFET transistor, Q1, an Interna-tional Rectifier (www.irf.com) IRF-9530, remains off because its gate

receives a slightly positive reverse-gate-bias voltage due to zener diode D4’s for-ward-voltage drop. Each capacitorcharges to approximately one-half thepeak value of the rectified voltageminus the forward-voltage drops thatD1 and D2 present. The full-wave bridgerectifier, D5, or Graetz bridge, producesthese drops (Reference 1).

When the discharge phase begins, D1gets reverse-biased, and capacitor C2discharges through the load that volt-age regulator IC1 presents. Subse-quently, the anode voltage of diode D1continues to decrease, Q1’s gate-to-source voltage becomes negative, andthe transistor conducts, allowing C1 todischarge into the load through for-

ward-biased diode D3. In effect, the twocapacitors charge in series and dis-charge in parallel into the load, halv-

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

JUNE 8, 2006 | EDN 87

Obtain a lower dc voltage from a higher voltage power supplyLuca Bruno, ITIS Hensemberger Monza, Lissone, Italy

D Is Inside

88 Line-powered driver lights uphigh-power LEDs

90 Rectifier tracks positive andnegative peaks

92 Isolated indicator signals tele-phone line’s status

94 Circuit converts DAC’s outputsfrom single-ended to differentialmode

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 In this unconventional step-down circuit, capacitors C1 and C2 charge in series and discharge in parallel, reduc-ing the voltage applied to regulator IC1.

ACLINE

TRANSFORMER

117V AC 18V AC

BRIDGE RECTIFIERT1

D5

D11N4002

D415V

D21N4002

D31N4002

R2100

R12.2k

C12200 F

C22200 F

C3100 nF

Q1IRF9530

C4100 nF

IC1LM7805

3

2 1

GND

VIN VOUT 5VOUTPUT

D

S

G

TO ORIGINAL CIRCUIT

designideas

88 EDN | JUNE 8, 2006

ing the raw rectified voltage and ripplevoltage at IC1’s input. During C1’s dis-charge, zener diode D4 protects Q1 byclamping its gate-to-source voltagewithin its maximum rating.

To function properly, the circuitrequires a minimum load current; the

regulator’s quiescent-current drain isusually enough. Otherwise, capacitorC2 charges to the peak voltage availablefrom D5. The values of C1 and C2 andthe ratings of the remaining compo-nents depend on the maximum loadcurrent required. The values of resistors

R1 and R2 are not critical. Note that Q1functions as a switch; selecting a devicewith low on-resistance limits Q1’spower dissipation.EDN

R E F E R E N C Ewww.answers.com/topic/graetz-ag.

Using LEDs has gained popu-larity as a method of saving

power for general-purpose lighting, butan efficient method for driving themhas also become a necessity. For exam-ple, Lumileds’ (www.lumileds.com)Luxeon devices create lighting effectsor room lighting. Providing power to afew LEDs may require only a current-limiting resistor, but illuminationapplications need a string of 20 or moreLEDs to provide light over an area.Based on On Semiconductor’s (www.onsemi.com) NCP1200A, a 100-kHz

PWM current-mode controller for uni-versal offline power supplies, the circuitin Figure 1 provides a low-cost, offlineconstant-current source for poweringmultiple LEDs. Although designers typ-ically configure it to provide a voltagesource, in this application, theNCP1200A provides a constant-cur-rent source. Figures 2 and 3 showclose-ups of the circuit.

A full-wave bridge rectifier, D2 to D5,and filter capacitor C1 provide approx-imately 160V dc to the conversion cir-cuit, IC1, and its associated compo-

nents. Resistor R3 alters the bias forIC1’s current-sense pin and, at 6.2 k,allows the use of a 1.2 sense resistorfor R6. Decreasing R6 not only reducescosts over a higher wattage sense resis-tor, but also improves the circuit’s effi-ciency. Capacitor C3 stabilizes the feed-back network’s current and carries a400V rating in case of an open circuitin the LED string. An RC networkcomprising R5 and C4 provides a smallamount of lowpass filtering to the CSpin.

Bleeder resistors R1 and R2 eliminateany shock hazard across the ac-lineplug’s prongs when you disconnect it. Although you can use a 1-Mthrough-hole-mounted resistor, twosurface-mounted 500-k series resistorscost less and provide the required track-

Line-powered driver lights up high-power LEDs

+

TO ACLINE

C20.1 F250V

C147 F400V

L1500 H

D1MUR160

C30.001 F

400V

Q1MTD1N60E

C522 F16V

C4470 pF

R61.2

R543

R1500k

R36.2k

R2500kR4

10

OPTIONAL PWMDIMMING INPUT

1

11

8

6

52

2

23

3

4

4

5

4

20LEDs

IC1NCP1200

IC24N35

D2 THROUGH D5BRIDGE

_

+

NC

NC

ADJ

FB

CS

GND DRV

VCC

HV

7

G

D

S

Aaron Lager, Masterwork Electronics, Rohnert Park, CA

Figure 1 An offline constant-current source drives a string of high-output LEDs.

1

to-track pc-board spacing for line-volt-age applications. Use a capacitor ratedfor line-bypass service for capacitor C2.You can use any power MOSFET witha suitable breakdown voltage and a lowon-resistance, such as an MTD1N60Eor IRF820, for Q1. Inductor L1, a 500-H device, should be able to operateat 100 kHz and handle more than 350mA of continuous current. You can usean inductor from Coilcraft’s (www.coilcraft.com) RFB1010 or DR0810series of surface-mount inductors, oryou can experiment with inductorsmanually wound on suitable core mate-rials. As an option, adding optoisolatorIC2 allows microcomputer-controlledillumination dimming using pulse-width modulation of IC1’s feedback ter-minal, Pin 2.

To understand the economic moti-vation for using LEDs as illuminators,compare the light output of a string of20 1W, white Luxeon emitters with astandard incandescent light bulb. EachLED provides 45 lumens, or 900 lumensfor a string of 20 LEDs. The average

forward voltage per LED is 3.42V for apower dissipation of 1.197W each at aforward current of 350 mA. Thus, the20-LED string dissipates 23.94W. Fac-toring in a conservative 80% efficien-cy for the power supply, the power thesystem consumes becomes 28.73W fora light-emission-efficiency value of 900lumens/29W or 31 lumens/W. TheLuxeon emitters also carry a rating for100,000 hours, or approximately 11years, of operation.

In contrast, a standard 60W Philipsincandescent light bulb produces 860lumens for 1000 hours, or just over amonth, at an efficiency of only 14lumens/W. From a power-consumptionviewpoint, the LED-based design istwice as efficient as the incandescent-bulb-based design and thus reducespower consumption and cost. In addi-tion, the LED design imposes no addi-tional maintenance costs for replace-ment bulbs and labor.EDN

designideas

90 EDN | JUNE 8, 2006

Figure 2 A close-up view of the cir-cuit of Figure 1 shows inductor L1

in the upper right corner.

Figure 3 This version of the circuitcomprises three constant-currentdriver channels. An LED light-barassembly is above the pc board.

Signals ranging from music tocomplex control-system wave-

forms may contain unequal positiveand negative peak amplitudes. An“envelope-follower” circuit can trackunequal peaks, but the ability to selecta desired peak can enhance the circuit’sperformance (Reference 1). The cir-cuit in Figure 1 applies a new twist toa classic absolute-value circuit. Apply-ing an input signal to R1 (full) producesan output equal to the input’s absolutevalue. Applying an input signal to R6(positive) or R7 (negative) producesoutputs of positive or negative half-cycles, respectively. Figure 2 illustratesall three modes of operation.

Understanding the circuit is simple ifyou consider that op amp IC1A strives

to maintain its inverting input at vir-tual ground. For example, applying1V to the negative input, R7, drivesthe anode of D1 to 333 mV. IC1A’soutput, Pin 1, drives D2’s cathode pos-itive enough to force D2’s anode volt-age to 333 mV. Because IC1A’s inputsnow rest at 0V, D1 is effectively reverse-biased and out of the circuit. The 333mV available at D2’s cathode alsoapplies to IC1B’s noninverting input,Pin 5, and IC1B must balance its inputvoltages by driving its output, Pin 7, to1V. IC1B’s inverting input, Pin 6, goesto 333 mV. The voltage drop across R4thus equals 666 mV. One-third of theinput current flows through the seriesconnection of R2 and R3, and two-thirds flows in R4. To achieve unity

gain, R7’s value equals that of R2R3 inparallel with R4.

Applying a positive input to R7 caus-es IC1A’s output to go negative by avoltage equal to one forward-diodedrop and thus holds D1’s anode atground. D2 is reverse-biased, and bothof IC1B’s inputs rest at 0V. The circuit’soutput is thus 0V. Applying an inputvoltage at R6 yields similar operation.A positive input causes an equal-valuepositive output, and a negative inputproduces a 0V output. You can ignorethe effects of IC1B’s high input imped-ance, which are negligible. To maintainunity gain, the value of R6 is twice thatof R3.

Resistors R1, R2, R3, R4, and R5 are ofequal value and close tolerance. Notethat IC1’s power-supply connectionsrequire bypass capacitors (not shown).To minimize errors, use a low-imped-ance source or buffer amplifier to drivethe circuit. You can use a three-posi-

Rectifier tracks positive and negative peaks

Harry Bissell Jr, Welding Technology Corp, Farmington Hills, MI

tion rotary switch for input-mode selec-tion, or an on/on/on toggle switch, suchas C&K Components’ 7211, availablefrom Digi-Key Corp (www.digikey.com) and other sources, or a similarswitch, wired as a three-way selector.(See the manufacturer’s data sheet fora connection diagram.) You can alsouse separate connectors for the inputs,but connect no more than one input ata time.EDN

R E F E R E N C EBissell, Harry, “Envelope follower

combines fast response, low ripple,”EDN, Dec 26, 2002, pg 59,www.edn.com/article/CA265499.

designideas

Figure 1 Use this versatile precision rectifier circuit to recover a signal’s positive peaks, negative peaks, or both in full-wave mode.

92 EDN | JUNE 8, 2006

NEGATIVE

FULL

POSITIVE

R76.65k

R210k

R410k

R510k

R310k

D11N4148

D21N4148

R110k

R620k

S1

OUTPUTIC1B

TL072

IC1ATL072

8

7

4

5

6

1

3

2

12V

12V

INPUT

NOTE: SCHEMATIC DOES NOT SHOW POWER-SUPPLY DECOUPLING CAPACITORS.

1Figure 2 This waveform plot shows the circuit’s outputs for a sine-wave inputconnected to the negative, full, and positive inputs, respectively. Traces arevertically offset for clarity.

AMPLITUDE

TIME

R7 INR1 IN

R6 IN

INPUT

OUTPUTSWITH SIGNALAPPLIED TO:

Part 68 of the FCC’s (FederalCommunications Commission,

www.fcc.gov) telecommunications reg-ulations requires that certain signalingequipment connecting directly to thepublic-telephone network must presenta line-to-line resistance of at least 5M. In addition, status signals thatequipment derives from the phone linesmust include electrical isolation to pre-

vent interaction between earthgrounds from the telephone networkand attached control or communica-tions equipment. Although a trans-former can provide isolation for voice-frequency signals, the telephone-line-status-indicator circuit in Figure 1meets FCC isolation requirementswithout incorporating a transformer(Reference 1). A diode bridge, D1

through D4, and R1, a 5.6-M resistor,supply a small amount of dc power fromthe phone line to a nanopowered com-bination comparator and a 1.2V volt-age reference, IC1. The Maxim (www.maxim-ic.com) MAX917 IC drawsonly 0.75 A at 1.8VCC.

Resistors R2 and R3 form the detec-tion-voltage divider, and R4 provideshysteresis. When IC1’s output goes low,R4 and R3 form a parallel combinationof 3.26-M resistance. To reach thecomparator’s reference voltage of1.245V, the voltage across C1 mustreach at least 5.06V. Once IC1’s output

Isolated indicator signals telephone line’s status

Yongping Xia, Navcom Technology, Torrance, CA

goes high, R4 and R2 form a parallelresistance of 6.67 M, and the voltageacross C1 must reach 3.37V to delivera 1.245V input to the comparator. IC1’soutput drives a photocoupler, IC2, aToshiba (www.semicon.toshiba.co.jp)TLP190B. Unlike other photocouplers,IC2 includes an array of photodiodesthat, when illuminated, delivers a volt-age output. Although weak by power-conversion standards, the photocou-pler’s output can deliver several micro-amperes at an open-circuit voltage thatexceeds 7V, or enough to drive a MOS-

FET’s gate or a microprocessor’s inputpin. In addition, the TLP190B carriesa 2500V-rms emitter-to-detector isola-tion-voltage rating.

When a telephone is not in use, theon-hook voltage across its line ofapproximately 48V produces a cur-rent of 7 to 8 A through R1, whichimposes a low-leakage requirement onC1. The prototype version of the circuituses an X5R-characteristic ceramiccapacitor. When the voltage across C1exceeds 5.06V, IC1’s output goes highand drives IC2 through R5, discharging

C1. When the voltage across C1decreases to 3.37V, IC1’s output goeslow, and C1 recharges. The output fromIC2 comprises a 1.4-msec-wide voltagepulse with a repetition period ofapproximately 240 msec. When thephone is off the hook, the voltageacross its lines drops to a few volts,which don’t sustain pulse genera-tion.EDN

R E F E R E N C Ewww.fcc.gov/wcb/iatd/part_

68.html.

designideas

Figure 1 Drawing minuscule amounts of power from a telephone line, this isolated-output circuit indicates whether theline is in use.

94 EDN | JUNE 8, 2006

6

4

1

3

OUTPUT

IC2TLP190B

VEE

1.245V

VCC

R52.2kIC1

MAX917

C11F R3

3.9M

R210M

R15.6M

R420M

OUT

D1 TO D41N4007

6

7

TO TELEPHONE

LINE

NC

4

3

2 REF

IN

High-speed DACs, such asAnalog Devices’ AD9776/

78/79 TxDAC family, offer differentialoutputs, but, for low-end ac applica-tions or high-precision level-settingapplications, a single-ended current-output DAC with a differential-con-version circuit provides a novel ap-proach to generating differential-waveform-control functions. The basiccircuit in Figure 1 combines a current-output DAC, IC1, such as the 8-bit

AD5424 DAC, with a single-ended-to-differential op-amp stage—IC2, IC3A,and IC3B—to generate the desired out-puts. For dual-power-supply applica-tions, you select the DAC’s unipolarmode of operation to achieve optimumperformance from the DAC. Using asingle op amp, the DAC provides two-quadrant multiplication or a unipolaroutput-voltage swing. The DAC’s out-put requires a buffer because changingthe code applied to the DAC’s input

varies its output impedance.This equation defines the circuit’s

output voltage: VOUTVREF(D/2N), where N defines the number ofinput bits, VREF is the reference voltage,and D is the decimal equivalent of thebinary code. To generate a positivecommon-mode voltage, you use a neg-ative voltage for the DAC’s referencevoltage. The DAC’s internal designaccommodates ac reference input sig-nals of 10 to 10V. In this mode, theDAC provides a 5M-sample/sec maxi-mum update rate for one-quarter full-scale code changes when you operate itfrom a 5V power supply. Use resistorsR1 and R2 only if your applicationrequires adjustable gain.

Circuit converts DAC’s outputs from single-ended to differential mode

Liam Riordan, Analog Devices, Limerick, Ireland

1

designideas

Figure 2 In this configuration, a positive reference voltage produces a positive output voltage.

½ AD8042

½ AD8042

AD8042

GAIN=1(R2/R1)=1.75

CM=0.8V

VIN

VDD

VDDRFB

R1

VREF

IOUT1

IOUT2

IC2BIC1

1V

5V

20k

R215k

R410k

R310k

R52.2k

R72.2k

R82.2k

R6

VVD

2.2k

1.4V

0V1.4VREFERENCE

GND

AD5424

DB0 TO DB7

IC3A

IC2A

IC3B

8-BITDIGITALINPUTS

0.343V P-P

0.6V P-P

VVS

1.4V

0V

0.6V P-P

The single-ended-to-differentialstage comprises two cross-coupled opamps, which resistors R5 and R6 con-figure as a unity-gain follower. To yielda symmetric circuit, the outputs alsodrive each other as unity-gain invert-ers through R7 and R8. The voltage youapply to the positive terminal of op ampIC2 sets the circuit’s common-modevoltage. Resistors R3 and R4 control theamplitude of the differential voltage.Review your application’s output-load

requirements and the op amps’ input-and output-voltage capabilities.

For single-supply applications, youcan use a current-output DAC inreverse mode, in which you apply thereference voltage, VIN, to the DAC’sIOUT1 pin and take the output voltagefrom the DAC’s VREF terminal (Figure2). In this configuration, a positive ref-erence voltage produces a positive out-put voltage. This circuit does not usethe DAC’s feedback resistor, RFB, and

its connection to IOUT1 prevents straycapacitance effects. The DAC’s refer-ence input “sees” an impedance thatvaries with the applied code and thusrequires a low-impedance source.

Note that the switches in the DACladder no longer have the same source-to-drain drive voltage, which in turnlimits the input voltage to low voltages.As a result, the switches’ on-resistanc-es differ and degrade the DAC’s lin-earity. Also, this mode limits the max-

½ AD8042

AD8042

VDD

VDD

IC1

VOUT

RFB

R1

VREFVREF

C1

IOUT1

IOUT2

R2

R410k

R310k

R52.2k

R72.2k

R82.2k

R6

VVD

2.2k

1.4V

0V1.4VREFERENCE

GNDAD5424

DB0 TO DB7

IC3A

IC2A

IC3B

8-BITDIGITALINPUTS

0.6V P-P

VVS

1.4V

0V

0.6V P-P

5V

1.8V

Figure 1 This basic circuit combines a current-output DAC, IC1, with a single-ended-to-differential op-amp stage—IC2,IC3A, and IC3B—to generate the desired outputs.

96 EDN | JUNE 8, 2006

imum update rate to 1.5M sam-ples/sec. You can use sections ofa dual op amp to buffer theDAC’s input and to amplify theDAC’s output voltage (Figure3). The circuit’s intendedapplication determines yourchoice of supporting amplifiers.For lower speed, precision ap-plications, the op amp requireslow input-bias currents and lowinput-offset voltage to avoiddegradation of the DAC’sDNL (differential-nonlineari-ty) performance. For example,the AD8628 offers 100-pAmaximum bias current at roomtemperature and 5-V maxi-mum input-offset voltage. Theop amp’s low-frequency noise isimportant in precision level-settingapplications, and the AD8628 specifies0.1- to 10-Hz noise of less than 0.5 Vp-p. Its rail-to-rail inputs and outputsmake it ideal for use in single-supplycircuits.

For high-speed-system applications,the op amp’s slew rate must not domi-nate the DAC’s slew rate. The op amp’sbandwidth must be large enough todrive the feedback load and must notlimit the circuit’s overall bandwidth,and the DAC’s output- voltage settling

time should determine the cir-cuit’s maximum update rate.The AD8042 in figures 1 and2 offers 170-MHz bandwidthand a 225V/sec slew rate,allowing it to easily achievethese results. Other high-speedop amps, such as the AD8022,AD8023, and AD8066, alsowork well in this application.

The DAC consumes only 0.4A of power-supply current,and the op amps thus dominatethe circuit’s power consump-tion. To minimize the area forthe circuit on a pc board, youcan replace all four op amps inFigure 2 with a single AD8044quad op amp. The single-

ended-to-differential conversion of adigitized, eight-point sine wave in thepresence of a 1.4V common-modevoltage and a 0.6V differential signalproduces differential outputs (Figure3).EDN

designideas

100 EDN | JUNE 8, 2006

Figure 3 The single-ended-to-differential conversionof a digitized, eight-point sine wave produces differ-ential outputs.

The circuit in Figure 1 offers aninexpensive alternative to com-

mercial digital voltmeters. Although ithas only two digits, it provides consid-erable flexibility and thus lends itself to customization by means of a micro-controller and its software. As one of Microchip’s (www.microchip.com)least expensive offerings, the PIC-16F84A lacks an internal ADC. How-ever, you can use a classic RC time-delaycircuit to implement an analog-to-dig-ital conversion by connecting capacitorC3 between lines RB7 (output) andRA4 (input) and in series with an equiv-

alent “unknown” resistor consisting ofQ3’s drain-to-source on-resistance, plusR4, plus R5. Q3, a BF245A JFET, presentsthe on-resistance. Q3’s “A” suffix isimportant because it corresponds to anon-resistance of 200 to 2 k for a gate-to-source voltage of 0 to 1V (Figure 2).Other devices in the BF245 familyexhibit a less pronounced change ofresistance versus gate-to-source voltage.To correct the measurement nonlinear-ity inherent in Q3’s gate-to-source volt-age versus drain-to-source on-resistancetransfer, the microprocessor’s softwareincludes a 100-point look-up table that

provides correction for a two-digit display.

For an application requiring the dis-play of readings of 0.01 to 0.99V, youcan use a 4-MHz crystal and Micro-chip’s PIC16F84A microprocessor forIC1. To display the rightmost threedigits of readings in the 0.001 to0.999V range, use a 20-MHz crystaland a PIC16F84A-20 microprocessor.Choose 15- to 33-pF values for capac-itors C1 and C2, which the PIC’s datasheet describes. Listing 1, which isavailable online at www.edn.com/060622di1, includes the full as-sembler source code for the PIC16-F84A. The most critical portion of thefirmware comprises a subroutine thatprovides a precision time delay ac-cording to the following steps:

1. Configure RA4 as an input tosense the voltage across C3 duringthe charging interval. When youconfigure RA4 as an input, itserves as a Schmitt trigger with1.6V low-threshold and 3.2Vhigh-threshold voltages whendrain-to-drain voltage is 5V.

2. Configure RB7 as an output andset it high to begin charging C3.Initialize a counter (register 0CH)to its maximum value of FFH.

3. Decrement the counter in a loop

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

JUNE 22, 2006 | EDN 71

Microcontroller, JFET form low-cost,two-digit millivoltmeterNoureddine Benabadji, University of Sciences and Technology, Oran, Algeria

D Is Inside72 Inexpensive envelope trackerhandles wide signal variations

76 Hartley oscillator requires no coupled inductors

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 Build a low-cost, two-digit dc millivoltmeter from a microprocessorand a few components.

VIN

VINRETURN

C118 pF

C218 pF

C30.1 F

C40.1 F

R42.7k

R6560

DS2(TENS)

DS1(UNITS)

R7560

R8560

R9560

R10560

R5470

CALIBRATION

NOTES: Q2=Q1=BC237/BC337/BC546 ... 550.Q3=BF245A. (USE "A" GRADE ONLY.)C1, C2=SEE TEXT.DS1, DS2=COMMON-CATHODE, SEVEN-SEGMENT LED DISPLAY.

MC LR

CLKOUT

CLKIN

RB7

RA4

VSS

VDD

IC1PIC16F84A

5V

INPUTMEASURE

0.01V0.99V

6

7

8

4

5

16

15

14

13

3

9

10R11560

R12560

11

12R110k

R210k

17

R310k

Q2

Q3

18

A

B

C

D

E

F

G

RB0

RB1

RA0

RA1

RB2

RB3

RB4

RB5

RB6

Q1

DG

S

4-MHzCRYSTAL

Converting band-limited NRZ(non-return-to-zero) data to a

digital format suitable for microproces-sors and other digital systems posesproblems when a signal’s duty cycle oramplitude varies or when its averagelevel unpredictably wanders within agiven dc range. Transferring the signalto a fixed-reference comparator usingac coupling produces poor resultsbecause changes in duty cycle causevariations in average signal level thatresult in jitter or distortion of the out-put signal’s timing.

Based on diodes and RC networks,an envelope tracker creates a voltagebetween the input signal’s excursions(Reference 1). Using the midpointvoltage as a reference, the comparatorgenerates a digital output signal thatfaithfully replicates the original signal’stiming information. Although highlyeffective for relatively large signals, a

diode-based circuit can introduceerrors or even fail completely for inputsthat are small relative to a diode for-ward-voltage drop or when the input’saverage level drifts toward either of thecircuit’s supply-voltage rails.

Requiring no diodes, the single-sup-ply circuit in Figure 1 reconstructs aband-limited NRZ data stream whoseduty cycle can vary from less than 5%to more than 95% and whose ampli-tude varies from less than 100 mV tothe supply-rail voltage—5V, for exam-ple. Furthermore, the circuit toleratesan average signal level that fallsbetween the two supply rails. The cir-cuit comprises triple analog switch IC1,dual comparator IC2, and a few passivecomponents.

The circuit functions as a self-clock-ing envelope tracker by sampling theinput signal’s upper and lower levels, VUand VL, and generating corresponding

dc levels, VUC and VLC, on capacitorsC3 and C4. Two equal-valued resistors,R4 and R5, between C3 and C4, producea third voltage, VMID, that’s equivalentto the input signal’s midlevel voltage,VM. Capacitor C2 smoothes and filtersVMID, which serves as a reference poten-tial for output comparator IC2B. R2, R3,and C1 provide temporal hysteresis,ensuring clean switching of VOUT, evenfor relatively small inputs.

To understand the circuit’s operation,assume that C4, C2, and C3 all dis-charge; that is, VLC, VMID, and VUC areall 0V. Because input signal VIN isgreater than VMID and the potential atIC2A’s inverting input, both compara-tors’ outputs go high and cause thethree analog switches to assume thepositions in Figure 1. Now, assume thatVIN is at its positive peak amplitude,VU. Capacitor C3 now charges throughR1 and the on-resistances of the threeswitches. Provided that C3 is not toolarge, VUC rapidly acquires a valueroughly equal to VU.

When VIN falls below VUC, com-parator IC2A’s output goes low and

designideas

72 EDN | JUNE 22, 2006

until RA4 senses a low state. Atthat time, C3 charges to nearly66% of the power-supply voltage.

4. Use the time it takes to produce alow on the RA4 input as a jumpvalue in the linearity-correctionlook-up table to extract a value forthe two-digit LED readout.

5. Configure RB7 as an input and setit low to discharge capacitor C3.

6. After a time delay, repeat Step 2.To round out the design, another

software subroutine solves the problemof driving a two-digit LED display atadequate visibility with a minimumamount of current. Although an LCDwould use less current, LCDs aren’tvisible in darkness. The display sub-routine examines the eight bits of theunits and tens—registers 11H and12H—and tests each one in sequence;if the subroutine sets a bit, then thesubroutine puts a short-duration highstate on its corresponding segment-

driver line, RB. Doing so lights onlyone LED segment at a time, and, con-sequently, the maximum current con-

sumption of the circuitremains relatively constanteven if you add a third LEDdisplay to build a 999-countmillivoltmeter.

Persistence of visioneliminates the need to keepthe displayed digits contin-uously visible, and main-taining the segments on forapproximately 33% of a 1-sec refresh interval allows agood and sufficient displayeffect. Transistors Q1 and Q2are never simultaneouslyon, and only one displaysegment lights at a time. Youcan further optimize thehardware by removing cur-rent-limiting resistors R6through R12, lifting the

emitters of Q1 and Q2 from ground, andinserting a single 560 resistor betweenthe emitters and ground.EDN

Inexpensive envelope tracker handles wide signal variations

Anthony H Smith, Scitech, Bedfordshire, England

GATE-TO-SOURCE VOLTAGE (V)

DRAIN-TO-SOURCE

ON-RESISTANCE(k)

103

102

101

101

10 2 3 4

1BF245A BF245B

BF245C

Figure 2 Gate-to-source-voltage-versus-drain-to-source-resistance-transfer curves for three select-ed grades of the BF245 JFET show maximumresistance variation for the “A” grade at low gatevoltage.

forces analog switch IC1C to changestate and disconnect C3 from VIN.Ignoring comparator input-bias cur-rents and assuming negligible switch-leakage currents, C3 can now dischargeonly through R4. If R4 is large enough,the relatively slow discharge rateallows VUC to remain roughly equal toVU.

During C3’s charging interval, C2 alsocharges through R4. Depending on thevalues of C2 and R4 and on the dura-tion of the input signal’s positive-goingpulse, voltage VMID may exceed theinput signal’s lower level, VL. If VMIDexceeds VL, comparator IC2B trips when

VIN approaches VL, and the resultinglow level at VOUT causes both IC1A andIC1B to change state. Capacitor C4 nowconnects to VIN through R1 and theswitches’ on-resistances and quicklycharges to a level at which VLC approx-imately equals VL.

Depending on component valuesand on the input signal’s timing param-eters, several cycles may elapse beforethe circuit’s voltage levels stabilize attheir quiescent values, at whichVUCVU, VLCVL, and VMID VM.However, careful selection of compo-nents ensures that the circuit rapidlyreaches equilibrium. Ensuring that the

comparator trips properly when VINgoes below VU or above VL requires thatR1 provide a minimum amount ofimpedance of 100 to 1 k betweenVIN and IC2A’s inverting input. Highervalues result in sluggish charging of C4and C3. In many designs, the combinedon-resistances of IC1B and IC1C mayallow omission of R1.

The presence of IC1B, IC1C, and IC2Aensures that C3 can charge when VIN isclose or equal to VU and that C4 cancharge only when VIN is close or equalto VL. Without IC1B, IC1C, and IC2A—that is, with VIN connected directly toR1—C3 would discharge on the down-ward slope of VIN between VU and VM

designideas

74 EDN | JUNE 22, 2006

Figure 1 This circuit tracks an NRZ signal’s envelope excursions and recovers the original waveform.

IC2A

VIN 5

314

1311

122

19

4

10

15

_

+

IC1C R1IC1BIC1A

C310 nF

C21 nF

C410 nF

R4560k

VOUT

R5560k

VUC

VLC

VMIDIC2B

R21k

R3100k

C1100 pF

_

+

5V

OUTPUT SIGNAL, VOUT

NOTES: IC1: 74HC4053 (PIN 16: V+; PINS 6, 7, 8: 0V).R1, IC2: SEE TEXT.

VU

VM

VL

INPUT SIGNAL, VIN

5V/DIV

100 mV/DIV 500 mV/DIV

2V/DIV

100 SEC/DIV 500 SEC/DIV

Figure 3 The lower trace shows the envelope tracker’soutput signal recovered from an inductively coupled datatransceiver.

Figure 2 The lower trace shows the envelope tracker’sresponse to a bandwidth-limited, low-duty-cycle, low-amplitude input signal. The horizontal line in the uppertrace shows the signals’ recovered midpoint voltage, VMID.

designideas

76 EDN | JUNE 22, 2006

Examine a traditional Hartley-oscillator circuit, and you’ll

note its trademark: a tapped inductorthat determines the frequency of oscil-lation and provides oscillation-sus-taining feedback. Although you caneasily calculate the total inductance fora given frequency, finding the couplingcoefficient, k, may require experimen-tal, or “cut-and-try,” optimization. ThisDesign Idea presents an alternative

equivalent circuit that allows you tomodel the circuit before building theprototype.

Figures 1a and b show the Hartleyoscillator’s equivalent tuned circuit, theequations that calculate its compo-nents, and component values for an 18-MHz oscillator. The mutual inductanceis LMkL1L2. For the equivalentcircuit, the equations are: LALM,LBL2LAL2LM, and LCL1LA

L1LM. The rest of the equations forthe equivalent circuit are:

and

Unfortunately, a truly equivalent cir-cuit requires a negative inductance, LA.

Hartley oscillator requires no coupled inductors

Jim McLucas, Longmont, CO

and would thus pull down VUC. Simi-larly, C4 would continue to charge onthe upward slope of VIN between VL andVM and would thus pull up VLC.Although VMID might be roughly equalto VM, such a minimal configuration per-forms relatively poorly, particularly forsmall signals and at extreme duty cycles.

The components in Figure 1 producegood results for input frequencies of 5 to50 kHz. Frequencies lower than 5 kHzmay require larger capacitor values, andoperation higher than 50 kHz may re-quire reduction of capacitors’ values andselection of a comparator with minimalresponse time. With properly selectedcomponents, the circuit performs well atbaud rates to or exceeding 128 kbps.

The values of R5, R4, C2,,and, to a less-er extent, the analog switches’ on-resist-ance and R1, C4, and C3 determine thecircuit’s response time to a suddenchange in input-signal amplitude or

average level. Making C2 approximate-ly 10 times smaller than C4 and C3ensures a rapid “attack” time, but toosmall a value can result in excessive rip-ple and noise on VMID. For reliable oper-ation, use equal values of close-toleranceresistors of 100 k to 1 M for R4 andR5. If you use high-value resistors for R4and R5, choose a comparator with lowinput-bias currents for IC2. For detectionof signals that might approach the pos-itive-supply rail, the 0V rail, or both,make sure that IC2 offers rail-to-railinput capability. Bypass each IC’spower-supply connections with low-impedance ceramic capacitors.

Note that, with no input signal pres-ent (that is, when applying a dc levelto VIN) VOUT may contain random puls-es caused by noise and the comparators’attempts at maintaining VMID equal toVIN’s average dc level. To eliminate thepulses, remove C1 to replace temporal

hysteresis with “normal” hysteresis, butensure that the hysteresis levels that R2and R3 set are not excessively large rel-ative to the minimum input-signalamplitude.

Figure 2 shows the circuit’s responseto a bandwidth-limited input signal ofapproximately 5% duty cycle and 75-mV amplitude. The horizontal trace,VMID, neatly bisects the waveform. Thebottom trace shows the reconstructedsignal at VOUT. In Figure 3, the circuitprocesses the real-world output of aninductively coupled transceiver (uppertrace) of approximately 200 mV p-p.Again, the lower trace shows the recon-structed signal at VOUT.EDN

R E F E R E N C EWhipple, Roger C, “Envelope

tracker quells jitter,” EDN, July 7,1994, pg 102, www.edn.com/archives/1994/070794/14di8.htm.

C67 pF

L2815 nH

L1168 nH

k=0.250LM=92.5 nH

C67 pF

LB907.5 nH

LB907.5 nH

LA92.5 nHLC

260.5 nHLC

260.5 nH

CA845 pF

C67 pF

(a) (b) (c)

1

Figure 1 A traditional Hartley oscillator’s resonant circuit comprises a tapped inductor and resonating capacitor (a).Allowing for mutual coupling between windings produces an equivalent circuit containing a negative inductance (b).Replacing the negative inductance with a capacitor yields an easily modeled equivalent circuit (c).

However, for frequencies near the res-onant frequency, f0, you can replace thenegative inductor with a capacitor, inwhich CA replaces LA (Figure 1c).Note that the equivalent circuit’s der-ivation neglects parasitic windingresistances and capacitances.

Figure 2 illustrates an oscillator andoutput buffer using the equivalent cir-cuit. The constructed circuit generallyperforms as you would expect from aninitial Spice simulation. During testing,several components’ values requiredtweaking, and multiple iterations ofSpice analysis ultimately yielded thefinal design. The oscillator’s tank circuitcomprises LB, LC, C4, and C5, pluscapacitance provided by voltagedivider C6, C7, and C8. This ca-pacitance of approximately 6 pFincludes Q1’s and Q2’s input capaci-tances and some stray capacitance. Thetotal tank capacitance of 66 pF approx-imates the calculated value of 67 pF.Capacitors that connect to the tunedcircuit feature ceramic-dielectric con-struction with NP0 temperature coef-ficients.

Inductors LB and LC comprise air-corecoils with their axes at right angles toeach other to minimize stray coupling.However, vibration affects their induc-tances, and, in a final design, bothshould comprise windings on dielectricor toroidal cores, providing that thetoroids’ temperature coefficients of in-ductance are acceptable for the in-tended application. Reference 1 pro-vides basic designs for both inductors,and adjusting the spacing of their turnstunes the oscillator to exactly 18 MHz.For a more rigorous design, you canmeasure the inductors before installa-tion, but parasitic effects may requirereadjusting the inductors’ values.

The capacitive voltage divider com-prising C6, C7, and C8 applies the prop-er signal levels to Q1 and Q2. Becausethe divider “sees” the tank circuit’seffective capacitance as only 6 pF, theremaining 60 pF can comprise a vari-able capacitor if the design calls for atunable oscillator. In this example, theoutput stage comprising Q3 and itsassociated components would requiremodification to provide more band-

width if the oscillator requires a tun-ing range exceeding 2 MHz.

Capacitor C3 bootstraps Q1’s Gate 2to Q1’s source to provide additionalgain from Q1 and to reduce its Gate 1input capacitance below its value ofapproximately 2.1 pF (Reference 2).An 8.3-H inductor, L2, connects toQ1’s source and presents relatively highimpedance at 18 MHz and provides adc path from Q1’s source to groundthrough R3. The impedance of L2 at 18MHz comprises an inductive reactanceof about 940 in parallel with a resist-ance of approximately 3.5 k, whichresults in a choke with low resistivelosses. You can substitute a smallerinductor for L2 provided that its induc-tance and reactance approximate theoriginal’s values. You can use a stan-dard-value 8.2-H choke for L2 pro-vided that its resistive losses meet theselow-loss criteria and that its inherentseries resistance is 2 or lower to avoidupsetting Q1’s dc bias voltage. Theinductance and resonance of thechoke for L1 are less critical than thosefor L2, but using a choke with low resis-

designideas

Figure 2 This buffered-output, 18-MHz oscillator has a resonant circuit that doesn’t rely on mutual coupling for operation.

78 EDN | JUNE 22, 2006

9.5V2% C1

0.01 F

C20.01 F

C3560 pF

C100.01 F

D11N4370A

Q1BF998 Q2

BF998

G1

G1

G2

G2

L18.3 H

L28.3 H

R163.01k

R1773.2k

R1843.2k

R339

R2100k

R110k

R155k

C184.7 F

C190.22 F

C90.01 F

C20220 pF

C718 pF

C610 pF

C839 pF

CA845 pF

LB0.9075

H

LC0.2605

H

C21220 pF

D3SD101C

D2SD101C

OUTPUT-LEVEL

ADJUSTMENT

D

D

S

S

+

CONTROL VOLTAGE

LOADR1950

OUTPUT

C16240 pF

C150.01 FC13

0.01 F

C120.01 F

C17240 pF

C14560 pF

C11220 pF

C427 pF

C533 pF

L3620 nH

R14220

R1113k

R822

R1310k

R9220

R547k

R44.3k

R10220

R727k

R610k

R1222

Q32N3904C

A=680 pF+150 pF+15 pF=845 pF.

TANK

NOTES:L1, L2: SIX TURNS AWG #22 WIRE ON A FAIR-RITE 2643002402 CORE.L3: FIVE TURNS AWG #26 WIRE ON A CWS BYTEMARK FT-23-61 CORE.LB: 11 TURNS AWG #22 WIRE AIR CORE, 0.450-IN. AVERAGE DIAMETER, LENGTH=0.450 IN.LC: SEVEN TURNS AWG #22 WIRE AIR CORE, 0.300-IN. AVERAGE DIAMETER, LENGTH=0.275 IN.AVERAGE DIAMETER IS THE DIAMETER OF THE CORE PLUS ONE WIRE DIAMETER.

designideas

80 EDN | JUNE 22, 2006

tive losses at L1 helps avoid spuriousresonances.

Source follower Q2 drives the outputstage, which uses a pi-matching net-work to transform the 50 output loadto 285 at Q3’s collector. BootstrappingQ2’s Gate 2 by one-half of its outputvoltage increases the source follower’sgain and dynamic range and reduces itsinput capacitance. Potentiometer R5adjusts the circuit’s output level fromabout 0.9V p-p to approximately 1.5Vp-p across a 50 load. The circuit’s fre-quency remains stable at a constantroom temperature of about 23C. Also,the output-level-control circuit re-mains stable even if you apply no loadto the output. For a fixed-frequencyoscillator, the output circuit’s loadedresistive losses of approximately 4 pro-vide adequate bandwidth without re-tuning L3, C16, and C17.

To set the output level to a safe max-imum, connect a 50 load to the out-put and adjust the output to 1.5V p-p.

The drain-to-source voltage you applyto Q1 remains at a safe level for all loadsfrom 50 to no load, even though theoutput-voltage level increases as theload resistance increases. To avoidexceeding Q1’s specified maximum 12Vdrain-to-source voltage, do not exceedan output-voltage setting of 1.5V intoa 50 load. Note that zener diode D1reduces Q1’s drain voltage to provide anadditional safety margin.

In a previous Design Idea, an oper-ational amplifier and a diode-rectifiercircuit control the oscillator’s gain byapplying a variable voltage to Q1’sGate 2 (Reference 3). In this design,a simple passive circuit serves the samepurpose. A portion of the signal at Q3’scollector drives a voltage doubler com-prising D2, D3, C20, and C21. The volt-age doubler develops a negative volt-age, part of which drives the junctionof R18 and C19, the control-voltagenode. This control-voltage node alsoreceives a positive voltage through R17

from variable resistor R15, and theresultant voltage sets the output-signallevel. At start-up, only a positive volt-age is present at Q1’s Gate 2, and Q1’smaximum gain easily starts the oscil-lator. When the output reaches steadystate, the control voltage decreasesand maintains oscillation at a signallevel that the output-level controldetermines.EDN

R E F E R E N C E SReed, Dana G, Editor, “Calculating

Practical Inductors,” ARRL Handbookfor Radio Communications, 82ndEdition, American Radio RelayLeague, 2005, pg 4.32.

“Practical FET Cascode Circuits,”Designing with Field-Effect Transis-tors,” pg 79, Siliconix, 1981.

McLucas, Jim, “Stable, 18-MHzoscillator features automatic levelcontrol, clean-sine-wave output,”EDN, June 23, 2005, pg 82,www.edn.com/article/CA608156.

1

3

2

You can improve a current sink’saccuracy by at least two orders of

magnitude by adding two standard 1%-tolerance resistors. As a bonus, you alsocompensate for errors that a low-cur-rent-gain pass transistor’s base currentintroduces. To do so, you measure thetransistor’s base current and add a pro-portionally scaled error term to thesource’s reference voltage. When youdesign a current sink, you can use aMOSFET for the sink’s pass transistorbecause of its nearly infinite power gainand low gate current. However, a high-power MOSFET presents high inputand output capacitances that reducethe sink’s high-frequency output im-pedance.

As an alternative, a low-current-gain,bipolar power transistor presents a muchlower output capacitance than does a

MOSFET of comparable power ratings.Figure 1 shows a design for a bipolar-transistor-based current sink that unfor-tunately suffers from accuracy errors dueto Q1’s base current’s flowing into thecurrent-measurement resistor R1. Thebase current varies with changes in Q1’scollector current and current gain,which in turn depend on Q1’s produc-tion tolerances, junction temperature,and collector-emitter voltage.

You can use a Darlington transistorto increase the circuit’s current gain andreduce the output error, but few Dar-lington transistors offer good high-fre-quency parameters. Superbeta powertransistors are rare, have typically lowerunity-gain-bandwidth frequencies, andare more expensive. In other words,even though a bipolar transistor pres-ents higher output impedance at high

frequencies, the error from its base cur-rent makes it a poor choice for a high-precision current sink. You could com-pensate for base-current errors by meas-uring the output transistor’s collectorcurrent and introducing a correctionfactor, but that approach increases cir-cuit complexity and reduces the sink’soutput impedance.

Figure 2 shows a better approach,which adds a differential amplifier, IC2,and resistors R6 through R9 to measureQ1’s base current by sampling the volt-age across R2. Resistors R4 and R5 scaleand sum the error and reference volt-ages you apply to differential amplifierIC1. Because IC1’s inverting input con-nects to current-shunt resistor R1’supper end and not to ground, the ref-erence voltage, VREF, determines theerror voltage applied to Q1, preservingoutput scaling and allowing output-cur-rent calculation as VREF/R1. As a result,the regulated voltage across R1 repre-sents the sum of the desired output cur-rent plus the transistor’s base current.Because the transistor inherently “sub-tracts” its base current, its collector cur-rent and, hence, the output currenthave no base-current error.

You can simplify the circuit and pre-serve its error-correction properties bycombining IC1 and IC2; better yet, youcan add two resistors to Figure 1 to

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

JULY 6, 2006 | EDN 83

Error compensation improves bipolar-current sinksChristian de Godzinsky, Planmeca Oy, Helsinki, Finland

IC1

CCOMP

VREF

R41k R2

47

R31k

R11

VC

_

__

+

++

Q1

2N3020

REGULATEDCURRENT

D Is Inside86 Phase-sequence indicator usesfew passive components

90 Microcontroller’s single I/O-portline drives a bar-graph display

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 This typical quickly responding constant-current sink uses a bipolartransistor but suffers from base-current-induced error. Its nominal output currentis IOUT(VREF/R1)IB.

achieve the same effect. Figure 3 showsthe final circuit. To understand its oper-ation, think of the circuit as a voltageregulator that delivers a voltage equalto VREF across R1. If you short-circuitbase resistor R2, note that any common-mode error that resistors R5 and R6introduce cancels and thus has no effecton Q1’s base voltage. When you feedthe voltage drop back to IC1’s inputthrough R5 and R4, the voltage dropacross R2, representing Q1’s base cur-rent, increases the regulated voltageacross R1 by the ratio of R5/R4. If theratio of R5/R4 equals that of R2/R1, thevoltage across R1 includes an error termthat effectively cancels the base cur-rent. If R3R4 and R5R6, the follow-ing equation describes the output cur-rent, IOUT:

Because the base current, IB, appearstwice with opposite signs and cancels,the equation simplifies to: IOUT(VREF/R1).

To optimize the circuit’s perform-

ance, use the following resistor ratios:R2/R1R5/R4, R5R6, R3R4, R5R4, and R3R1. Using standard 1%-tolerance resistors in the circuit of Fig-

ure 3 reduces the error from Q1’s basecurrent to about one-one-hundredthofits uncompensated level. Withoutcompensation, a low-gain power tran-sistor with a typical current gain of 25at Q1 would introduce a full-scale cur-rent error of 4%. The circuit correctsthe error to 0.04% and raises Q1’s cur-rent gain to an effective current gain of2500. Perfect matching would result inan immeasurably small base-currenterror. Note that IC1’s input common-mode-voltage range must include thenegative-supply-voltage rail. Equalresistances at both of IC1’s inputs bal-ance the op amp’s input-bias currents.The minimum power-supply voltagedepends on IC1’s maximum current-sourcing capability and on the sum ofthe worst-case voltage drops across Q1’sbase-emitter junction, R1 and R2. Thecircuit’s maximum output current de-pends on Q1’s worst-case minimum cur-rent gain times IC1’s worst-case mini-mum output current.

To ensure stable operation, use aunity-gain-stable op amp for IC1.When the circuit operates within itsnominal current range, an op ampwhose response time is substantially

designideas

84 EDN | JULY 6, 2006

IC1

IC2

CCOMP

VREF

R41k

R547k

R247k

R31k

R11

R647k

R747k

R847k

R947k

VCC

VC

_

__

__

+

++

++

Q1

2N3020

REGULATEDCURRENT

Figure 2 Adding base-current error compensation improves the circuit’s per-formance. Using perfectly matched resistors simplifies the output-current equa-tion to IOUT(VREF/R1).

IC1

CCOMP

VREF

R41k R2

47

R647k

R31k

R11

R547k

VC

_

__

+

++

Q1

2N3020

REGULATEDCURRENT

Figure 3 You can further simplify the current sink’s design by adding only tworesistors, R5 and R6, to the original in Figure 1. The output-current equationremains IOUT(VREF/R1), as in Figure 2.

In a three-phase ac system, apower source with three wires

delivers ac potentials of equal fre-quency and amplitudes with respect toa zero-potential wire, each shifted inphase by 120 from one wire to thenext. Two possibilities exist for estab-lishing a phase sequence. In the first,voltage on the second wire shifts by120 relative to the first, and, in thesecond, a 120 shift occurs withrespect to the first wire. Phase orderdetermines the direction of rotation ofthree-phase ac motors and affects otherequipment that requires the correctphase sequence: a positive 120 shift.You can use a few low-cost passivecomponents to build a phase-sequenceindicator.

Figure 1 shows a conceptual circuitthat can detect both phase sequences.

For certain component values, the fol-lowing conditions apply: The voltagesacross R1 and C2 are equal—that is,their magnitudes and phases are thesame—only when VS2 occurs exactly120 ahead of VS1, which indicates thecorrect phase sequence. In this case, thevoltage between points A and B is zero.Conversely, the voltages across C2 andR3 are equal only when VS2 is ahead ofVS3 by 120, which corresponds to areversed sequence.

Referring to the phasor diagram inFigure 2, when the voltages across R1and C2 are equal, VC1VR2, VC1VR1VS1, and VC2VR2VS2. The fol-lowing equations satisfy these condi-tions: |VR1||VC2|(1/2)|VS2|(1/2)|VS1|, and |VC1||VR2|cos(30)|VS1|cos(30)|VS2|. Youcalculate the component values by

solving the following equations:|XC1|tan(60)R13R1, andR2tan(60)|XC2|, where XCj[1/(2fC)], and f represents thefrequency of the VS voltages.

Also, to ensure detection of areversed phase sequence, C1C3, andR1R3; that is, the components in the

longer than Q1’s generally doesn’trequire installation of compensationcapacitor CCOMP. However, a small

capacitor of a few tens of picofaradsguarantees stability under all condi-tions—for example, when the circuit’s

output current and the feedback volt-age across R1 approach zero.

The circuit in Figure 3 works equal-ly well if you use a Darlington transistorfor Q1 because its higher current gainfurther improves the circuit’s operation.If you use two discrete bipolar transistors,you can improve the composite Dar-lington transistor’s turn-off time by con-necting a resistor between the outputtransistor’s base and emitter to removeits excess base charge (Figure 4).

You can use either a fixed or anadjustable reference-voltage source, butfor the smallest possible error, the ref-erence source’s output impedanceshould be fairly low to sink feedbackcurrent from R4. You can also propor-tionally increase the values of resistorsR3 through R6 to reduce the amount ofcurrent that the reference sourceabsorbs. It’s amazing what you canachieve by adding only two resistors toan already-simple circuit.EDN

designideas

Metodi Iliev, University of California—Berkeley

86 EDN | JULY 6, 2006

R11

R31k

R247

R647k

RSPEEDUP470

Q2

Q1

2N3020

2N3020

REGULATEDCURRENT

TO REMAINDEROF CIRCUIT

Figure 4 Adding RSPEEDUP improves the performance of a two-transistorDarlington output stage.

Phase-sequence indicator uses few passive components

Figure 1 This conceptual circuit candetect both phase sequences.

VS2

R2

C2

VS1

R1

C1

I1

VS3

R3

C3

A I2 B I3 C

third branch are identical to those inthe first branch. The phase-sequence-detection circuit in Figure 3 eliminatesthe requirement for an accessibleground wire by adding resistors R4 andR5 that connect in parallel with the firstand third branches. Eliminating theground-wire requirement also dictatesa ratio between |XC1R1| and|XC2R2|. For no current to flow toground from Node G, the sum of cur-rents in the branches must equal zero,and, if you disconnect Node G from

ground, its potential with respect toground is also zero.

As long as the proportions of XC1 toR1, XC2 to R2, and XC3 to R3 remain asnoted, the balance of voltage dropsremains across R1, C2, and R3. Multi-plying the impedance of any branch bya constant influences only the magni-tude of the currents through the respec-tive branch. The current through anybranch presents the same phase angleas the voltage across a resistor in thebranch. The phasor diagram in Figure4 shows the currents in Figure 3. Fromthis diagram, if |I2|tan(60)|I1|,then I1I22I3. Thus, I3 has halfthe magnitude of and an exactly oppo-site direction from (I1I2).

A vector diagram of the currentsshows that adding two currents, eachwith magnitudes equal to I3 and thesame phases as VS1 and VS3, produces asummed current with the same magni-tude and phase as I3; therefore, the totalcurrent at Node G is zero: I1I2I3I1I3I1I22I30. To makethe sum of the currents equal zero,R4R5|R1XC1||R1j[1/(2fC1)]|. The two LEDs in Figure 3indicate correct or reversed-phasesequence. When LED2 lights and LED1remains dark, the voltage betweennodes A and B is 0V, which corresponds

to a correct phase sequence. A re-versed-phase sequence lights LED1while LED2 remains dark. The diodesconnected in parallel with the LEDsprotect against exceeding the LEDs’reverse-breakdown voltages, and resis-tors R6 and R7 limit forward currentsthrough the LEDs. For greater sensi-tivity, you can replace the LEDs withhigh-input-impedance ac-detector cir-cuits.

The circuit’s final version includesindicators that show whether all threephases carry voltage. In the circuit inFigure 3, a phase that carries 0V lightsboth LEDs. Depending on your appli-cation, you can connect voltage-detection circuits comprising LEDs andprotection diodes in series with current-limiting resistors between VS1, VS2, andVS3 and Node G. You can also use low-wattage neon lamps with appropriateseries-current-limiting resistors.

When selecting components, ensurethat their values conform to the fol-lowing proportions. For an arbitrarilychosen value for C1, R1R2R31/(2fC1tan(60)), C1C3,C23C1, and R4R52R1. Whenyou select a value for C1, the currentsthrough the detection circuitry shouldbe significantly lower than the currentsthrough the branches, which excludesarbitrarily low values for C1.EDN

designideas

88 EDN | JULY 6, 2006

Figure 2 When the voltages acrossR1 and C2 are equal, VC1VR2,VC1VR1VS1, and VC2VR2VS2.

Figure 3 This phase-indicator circuit balances branch voltages and currents andrequires no ground reference. These component values are for a 60-Hz line fre-quency.

VS1 VS2 VS3

LED1

D11N4004

R6499k

R7499k

R346.4k

R593.1k

R246.4k

R146.4k

R493.1k

I1' I1

C133 nF

C2100 nF

C333 nF

LED2

D21N4004

I2 I3 I3'

A B C

G

VS3

VS2

VS1

VC3

VC2

VC1

VR3VR1

VR2

120

60

Figure 4 I3 has half the magnitudeand an exactly opposite direction to(I1I2) in Figure 3.

VS3

VS2

VS1

I3

I3'

I1

I1'

I2

120

60

I1+I2

Instrument designs featuring adigital display may benefit from

a secondary display that provides ananalog version of the displayed param-eter. A bar-graph display provides aneasily interpreted graphical indicatorthat allows comparison with its full-scale value, but a conventional micro-controller-based design uses at least oneeight-line I/O port to drive an eight-segment-bar-graph LED display.

As an alternative, some microcon-trollers include a PWM (pulse-width-modulated) output. You can minimizethe number of required I/O lines byusing the PWM output to driveNational Semiconductor’s (www.national.com) LM3914 bar-graph-dis-play-driver circuit or an equivalent. Inoperation, the microcontroller’s pro-gram adjusts the PWM output’s pulsewidth such that the average voltagethat feeds to the LM3914 circuit illu-minates the required number of bars inthe display.

The design in Figure 1 obviates theshortcomings of these approaches anduses only one port line to drive aneight-segment bar graph. This designdoes not use a PWM output and hencecan apply to any microcontroller.

Referring to the timing diagram in Fig-ure 2, whenever the bar-graph displayrequires an update, the microcon-troller’s software delivers a pulse trainthrough its output port. The first pulsecomprises a pulse of width T1 that’slonger than the width of the pulse T2,which triggering monostable IC1, a74123 or equivalent, produces. Youapply both pulses to IC3, a 7400 orequivalent NAND gate, which togeth-er with IC1 forms a long-pulse detector.Use the equation in IC1’s data sheet toselect values for C1 and R1 that yield avalue of approximately 1.5 msec for T2’soutput pulse. Typical widths for T1 andT3 are 3 and 1 msec, respectively.

The output pulse from IC3 goes lowfor a duration of T1T2, and this pulseclears IC2, an 8-bit serial-in parallel-outshift register, which forces all of IC2’soutputs to go low and lights all segmentsof the bar-graph array (LED1 to LED8).

To light N segments of the bar-grapharray, the microcontroller immediatelysends a serial train of (8N) pulses ofwidth T3 through the output-port line.Because the width of these pulses is lessthan T2, NAND gate IC3’s output alwaysremains high and thus does not clear theshift register. The rising edge of each of

the microcontroller’s output pulsesloads a high to one of IC2’s outputs.

Note that shift register IC2’s QA out-put connects to the bar graph’s most sig-nificant segment. Hence, the first pulseswitches off the most significant seg-ment. Starting with the most signifi-cant segment, for (8N) pulses, 8Nsegments switch off, and N segmentsbeginning with the least significant seg-ment remain lighted. Using thisreverse logic takes advantage of theshift register’s outputs’ ability to sinkmore current than they can source—8versus 0.4 mA, respectively, and thusproduce a brighter bar-graph displaywithout adding output buffers. Figure2 shows a sample timing diagram thatlights five of eight display segments.

If a second output-port line is avail-able, you can omit using monostablemultivibrator IC1 and NAND gate IC3and use the second port to clear theshift register by outputting a zero when-ever the bar graph requires an update.To obtain finer resolution, you can addsegments to the bar graph by cascadingadditional shift registers. To light N seg-ments of a display that is M segmentslong, the first output port sends MNpulses to the shift register’s clock input.

This design lends itself well to situa-tions in which unused I/O-port lines areat a premium, as is the case for micro-controllers with reduced pin counts, orif you need to retrofit a bar-graph dis-play by adding a daughterboard to adesign.EDN

Microcontroller’s single I/O-port line drives a bar-graph display

designideas

90 EDN | JULY 6, 2006

R Jayapal, PhD, Bharat Heavy Electricals Ltd, Trichy, India

Figure 1 You can add a multisegment bar-graph display to a microcontroller thathas only one output line.

MICRO-CONTROLLER

PORTLINE 2

1 8

7

10

11

12

13

4

3 11 16

15

14

1 2 14

IC1½74123

IC274164

¼IC3A1 GND

Q1

CEXT1

REXT1

VCC

5V5V

5V

C20.1 F

C30.1 F

C1100 pF

R2750

13

3

4

5

6

8

92

CLOCK

CLEAR

GND

R3750

R4750

R5750

R6750

R7750

R140k

R8750

R9750

(QA)

(QB)

(QC)

(QD)

(QE)

(QF)

(QG)

(QH)

MOSTSIGNIFICANT

SEGMENT

LEASTSIGNIFICANT

SEGMENT

EIGHT-SEGMENTLED BAR GRAPH

SERIALIN A

SERIALIN B

Figure 2 During the first pulse of themicrocontroller’s output-pulsesequence, the NAND gate’s outputclears the shift register and lights allof the display’s segments.

QA

QB

QC

QD

QE

QF

QG

QH

NANDOUTPUT(T1T2)

MICRO-CONTROLLER

OUTPUT

LEAST SIGNIFICANTSEGMENT

SEGMENTIS ON(LOW)

SEGMENTIS OFF(HIGH)

LONGPULSE

WIDTH T1 ALL PULSES AREOF WIDTH T3

T2

T1

T3 T4

To produce trains of pulses suit-able for keying transmitters,

testing circuits, and debugging datalinks, designers requiring continuous orevent-driven pulse sequences have tra-ditionally relied on pulse generators orcollections of simple circuits. Today’sinexpensive microprocessors make itpossible to design and build low-cost,dedicated pulse-sequence generatorswith a minimum of resources. In asmall, SOT-23-packaged, 10F200 con-troller from Microchip (www.microchip.com), the design in Figure 1 usesa code-based embedded table algo-rithm to generate an application-set-table period and table-based PWM(pulse-width-modulation) sequence.The application produces a continu-ously pulsed sequence and requiresonly three constants and a pulse-widthprofile table that it copies into themicroprocessor’s assembler-based codebefore compiling (Figure 2).

All code branches undergo equal-

ization to produce a group of 29 con-stant instruction times. During soft-ware development, you can use codedconstants and a table-based approachas a flexible method of modifying thepulse sequence. The three parametersthat Figure 2 highlights include thenumber of PWM cycles that executebetween tabled steps, which the algo-rithm passes as “temp_cntK.” Thisparameter defines how many PWMperiods of a range from one to 255repeat within each tabled step. Forthree cycles per table step, you use#define temp_cntK .3. The nextparameter is the number of 29-instruction loops that execute duringeach PWM period. All branches ofthe coded instructions equalize toconstant 29-instruction periods.When you copy this parameter as“loopsK,” it can range from one to255. Using the 10F200’s internal 4-MHz clock and an 8-bit counter togenerate 1-sec instruction periods,

you can gener-

ate a PWM period range of 58 to 7395sec, which corresponds to a fre-quency range of 17,241 to 135 Hz. Fora 1-msec PWM-cycle period and thesequence in Figure 2, you require 31base loops per cycle, which you obtainby dividing 1 msec by the 29-secinstruction period: #define loopsK.31.

You then equate the total number oftable profile steps to “table_maxK.”The total number of profile steps thata look-up table includes and that youcopy into the code may vary from oneto 252. In this application, five tabledsteps correspond to pulse duty cycles of25, 50, 87.5, 12.5, and 75%. These val-

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

JULY 20, 2006 | EDN 83

Microprocessor generatesprogrammable clock sequencesWilliam Grill, Honeywell BRGA, Lenexa, KS

IC1PIC10F200/202

ENB

VSS

VSS

VDD

ENB PWMOUT PWMOUT

VDD

MODE

1

2

3

6

5

4

2 TO 5.5V

R110k

D Is Inside86 Ceramic output capacitorsenhance internally compensatedintegrated switchers

90 Tapped inductor, boost regula-tor deliver high voltage

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 A microcontroller and a resistor can deliver a com-plex PWM output.

Figure 2 This waveform profile comprises five steps, eachusing one of three PWM cycles. In continuous mode, thecircuit’s output repeats indefinitely.

PROFILESTEP

PWM CYCLE

ues undergo scaling according to thefollowing equation: Duty cycleINT(%TDTY/100loopsK0.5), in whichINT is the integer value and %TDTY isthe percentage of the total duty cycle.In this example, loopsK31. Thenumber of steps in the table passes tothe program as #define loop_maxK .5.

The pulse-duty cycle can vary only inincrements of a single 29-instructionbase loop, and, as a consequence, thepulse duty cycle’s resolution varies asthe number of basic loops for the wave-form’s desired period, which you defineas loopsK31 loops. Thus, the duty-cycle resolution equals 1/(loopsK), or1/(31)3.22% for this application.

You can use a spreadsheet or manu-ally calculate the translated andscaled duty-cycle values and storethem in the data-profile table. Forexample, you calculate the value for a25% duty cycle as INT(25/resolution0.5)=INT(25/3.220.5), where INTrepresents extraction of the integervalue of the computed quantity. Forrequired duty cycles of 25, 50, 87.5,12.5, and 75%, the values that pass tothe data-profile table are retlw_8, 16,27, 4, and 23, respectively. The as-sembly-language program available for

downloading from the online versionof this Design Idea at www.edn.com/060720di1 includes these duty-cyclevalues and the three other parameters.

The program includes two addition-al features: Connecting Pin 1 to groundenables a continuous-output mode.Connecting Pin 1 to VDD evokes asingle output waveform. Pin 3 serves asa high true-output enable when youconnect it to VDD or as a positive-edge trigger input when you pull thepin to ground and release it. Note thatthe program currently includes no con-tact-debounce routines for eitherinput.

In the example in Figure 3, the con-troller delivers a pulse-width-modu-lated output (lower trace), which, afterprocessing by a single-pole lowpass fil-ter, corresponds to a sine wave (uppertrace). Using another version of thecircuit, you can evaluate how a criti-cal midword error affects a serial link’scharacteristics, system timing, andresponse latency.

The waveform in Figure 4 compris-es 100 pulses, 99 of which exhibit anominal duty cycle that varies from 48to 51%, and a single error pulse with a75% duty cycle. The waveform-tableentries use values of loopsK100,temp_cntK1, and table_maxK100to produce a pulse sequence compris-ing 74 pulses with nominal duty cycles,a single pulse with a 75% duty cycle,and a final sequence of 25 clocks withnominal duty cycles. The entiresequence repeats at a 345-Hz rate.

Using a 4-MHz-clock-rate versionof Microchip’s 10F220 controllerconstrains the basic software-timingloop to a 29-sec period. You cancompile the program into an 8-MHz10F220 to reduce the timing loop to14.5 sec and extend the output’susable bandwidth. You can modify thecode in the listing to suit other com-patible microprocessors to obtaingreater bandwidth and integrate addi-tional functions. As is, the circuitrequires only 155 bytes of internalEEPROM and occupies an SOT-23pc-board footprint—not bad for aprocessor that costs less than $1.EDN

designideas

84 EDN | JULY 20, 2006

Figure 3 After undergoing lowpass-filtering, the controller’s pulse-width-mod-ulated output (lower trace) reveals its sine-wave origin.

80

75

70

65

60

55

50

451 8 15 22 29 36 43 50 57 64 71 78 85 92 99

PULSE-POSITION TABLE ENTRIES

DUTY-CYCLETABLE

VALUES

Figure 4 Devised for testing a serial link’s error response, this waveform plotdisplays pulses’ locations within the waveform (horizontal axis) versus theduty cycle for each pulse (vertical axis). The waveform cycle repeats afterpulse 100 ends.

Integrating compensation com-ponents with a power-supply

controller and buck regulator’s powerswitches can minimize pc-board area,improve reliability, and eliminateassembly errors by reducing the num-ber of components and solder joints.However, integration also limits a de-signer’s range of choices in the selectionof output-filter components. Figure 1apresents a typical switching regulatorbased on Texas Instruments’ (www.ti.com) TPS5430. The boxed area in Fig-ure 1b shows a simplified version of theIC’s internal small-signal-equivalentcircuit, which includes an error ampli-fier, E1; passive-compensation compo-nents; and a voltage-controlled volt-

age-source, E2, which represents themodulator and the power switches.Support components external to the ICinclude output-filter components andtheir parasitic resistances, a resistor rep-resenting an external load, and adivider comprising R1 and R2 that setsthe output voltage. The compensation-circuit design accommodates a certainrange of output-filter inductance andcapacitance and their associated para-sitics.

Figure 2 shows Bode diagrams forthe error-amplifier and modulator-gain blocks (2a) and the entire regu-lator system (2b). Envisioning thatend users would specify aluminumelectrolytic capacitors for the output-

filter circuit, the IC’s designer includesa Type 3 compensation circuit to opti-mize the IC’s performance for alu-minum capacitors’ characteristics.Note that a Type 3 compensation cir-cuit includes a pole at the origin of thecircuit’s pole-zero plot to provide highgain at dc and an integratorlike high-frequency roll-off augmented withpairs of poles and zeros to providephase and gain margins at certain fre-quencies (Reference 1).

The regulator’s LC-output modula-tor/filter’s amplitude-response curvepeaks at the resonant frequency set bythe filter’s inductor and output capac-itor, and then it decreases at a 40-dB/decade rate until it reaches a zeroat a frequency set by the output capac-itor and its ESR (equivalent seriesresistance). Beyond that frequency,the output inductor’s and the capaci-tor’s ESRs determine the attenuation

curve’s slope, resulting in a20-dB/decade rate.

For good regulation, theerror amplifier provides a highdc gain at low frequencies.However, to ensure stability,the loop gain must decrease asfrequency increases. The goalis to approximate a 20-dB/decade roll-off at all frequen-cies. Placing two zeros at theoutput filter’s resonant fre-quency helps cancel the twopoles representing the reso-nance. Adding a pole to theerror-amplifier response can-cels the zero that the outputcapacitor and its ESR intro-duce. Adding a final poleabove the power supply’scrossover frequency helps fur-ther increase the regulatorloop’s stability. Figure 2bshows the sum of the gains ofthe error amplifier and modu-lator/filter gain. The powersupply’s characteristics show a30-kHz bandwidth and a 60phase margin that ensures sta-ble operation.

The power-supply-control-

designideas

Robert Kollman, Texas Instruments, Dallas, TX

86 EDN | JULY 20, 2006

Ceramic output capacitors enhanceinternally compensated switchers

Figure 1 This TPS5430 power-supply design includes an aluminum electrolytic output-filter capacitor, C0 (a). A circuit model includes parasitic resistances associated withoutput-filter components L0 and C0 (b).

+

+

E1

+

E2

RINT41000

RIND0.03

RESR0.001

RL

L010 H

C022 F

RINT1332k

RINT23676k

RINT33072k

CINT120 pF

CINT220 pF

CINT41.6 F

CINT31 pF

R12.1k

R21.2k

1V AC

V1

INTERNALTO TPS5430

(b)

VIN

ENA

NC GND

NC GND

GND

BOOT

PH

VSNS

PWPD

IC1TPS5430DDA

C41 F

C50.01 F

L010 H

C022 F

R12.1k

R21.2k

VOUT

D2MBRM140

7

5

2

3

6

1

8

4

9

J2 J1VIN

GNDNC

GND

(a)

(continued on pg 90)

designideas

88 EDN | JULY 20, 2006

Figure 2 Gain (a) and phase (b) plots show that the circuit of Figure 1a includes adequate compensation and phase-angle margin for an aluminum electrolytic output-filter capacitor.

MODULATOR/FILTER

FREQUENCY

ERROR AMPLIFIER

OVERALL GAIN

OVERALL PHASE

60 PHASEMARGIN

100 Hz40

20

0

20

40

1 kHz 10 kHz 100 kHz 1 MHzFREQUENCY

100 Hz80

40

0

40

80

120

160

1 kHz 10 kHz 100 kHz 1 MHz

GA

IN (d

B)

PH

AS

E (

)

Figure 3 Gain (a) and phase (b) plots show that using a ceramic-dielectric output-filter capacitor erodes the phase-anglemargin and pushes the circuit dangerously close to oscillation.

MODULATOR/FILTER

ERROR AMPLIFIER

OVERALL GAIN

OVERALL PHASE

NO PHASEMARGIN

FREQUENCY100 Hz

60

40

20

0

20

40

1 kHz 10 kHz 100 kHz 1 MHz FREQUENCY100 Hz

100

50

0

50

100

150

200

1 kHz 10 kHz 100 kHz 1 MHz

GA

IN (d

B)

PH

AS

E (

)

Figure 4 A few passive components supplement R1 and R2

and stabilize the circuit for use with a ceramic-dielectric out-put-filter capacitor.

+1V AC

V1

R12.1k

R375

R21.2k

C12.5 nF

C20.5 F

TO PIN 4,VSNS, OF IC1

Figure 5 The phase-angle plot for the circuit of Figure 4shows a sufficient phase-angle margin to allow stableoperation with a ceramic output-filter capacitor.

OVERALL GAIN

OVERALL PHASE

45 PHASEMARGIN

FREQUENCY100 Hz

80

40

0

40

80

120

160

1 kHz 10 kHz 100 kHz 1 MHz

GA

IN (d

B) A

ND

PH

AS

E (

)

(a) (b)

(a) (b)

When you face the task of gen-erating a regulated voltage

that’s higher than the availablepower-supply voltage, you may con-sider a boost regulator. Although aboost converter can in theory gener-

ate almost any voltage that’s higherthan its input, practical considerationslimit the output to approximatelyeight times its applied voltage. To gen-erate an even higher voltage, consid-er using a tapped-inductor boost top-

ology. Figure 1 shows an implemen-tation of a converter that boosts a 3Vinput to 100V dc. The connections tothe regulator chip are similar to thoseof a traditional boost converter, but, toachieve the high boost ratio, thisdesign uses L1, a 1-to-6-turns-ratio,tapped inductor.

The waveforms in Figure 2 showthe input voltage, the voltage atpower-switch IC1’s output, Pin 5, andrectifier diode D1’s anode voltage. Asin any boost circuit, inductor L1’s corestores energy when IC1’s internal out-put switch conducts. When theswitch turns off, the voltage across itsterminals and L1A goes higher than theinput voltage. Due to inductive cou-pling and the larger number of turnsthat make up L1B, the voltage at rec-tifier diode D1’s anode and hence theoutput voltage goes much higher.Resistors R2 and R3 form a feedback-voltage divider that closes the regula-tion loop. The R4-C4 network forms asnubber circuit that suppresses theimpact of diode D1’s small parasiticcapacitance. Without the network,

designideas

90 EDN | JULY 20, 2006

Tapped inductor, boost regulatordeliver high voltageDavid Ng and Adam Huff, Linear Technology Corp, Milpitas, CA

Figure 1 Using a tapped inductor extends a boost-topology switching regula-tor’s practical output-voltage range.

IC1LT1949

VIN

SHDN

VC

GND

LBO

LBI

SW

FB

6

3

1

4

NC

NC

8

7

5

2

VIN+3V

C122 F6.3V

C30.1 F250V

R137.4k

C21 nF

GND

1-TO-6 TURNS RATIO

L1COILTRONICSCTX02-17409-R

GND

R312.4k

R21M

L1A L1B

C410 pF

D1BAS21

R42k

VOUT+100V5 mA

loop response (Figure 3) illustrates thecircuit’s behavior when the designincludes ceramic-dielectric output-fil-ter capacitors and the same integrated-compensation components in Figure 1.Ceramic capacitors present a muchlower ESR than do aluminum elec-trolytic capacitors, and their capaci-tance determines the filter’s attenua-tion rather than their ESR. Conse-quently, at high frequencies, the LC fil-ter’s characteristics include a doublepole and a steeper, 40-dB/decadeslope. In addition, filter attenuation in-creases at the desired crossover fre-quency, degrading phase and gain mar-gins. Figure 3b indicates that the powersupply is unstable and, with no phasemargin, will likely oscillate.

Replacing the divider network, R1and R2 in Figure 1 with the passive net-work in Figure 4 stabilizes the regula-tion loop and allows an internally com-pensated controller to use ceramic out-put capacitors. The network’s compo-

nents add two sets of poles and zeros tothe compensation network to cancelthe consequences of using ceramic out-put capacitors. For example, C2 and R3provide attenuation that reduces thecrossover frequency. You select C2 toprovide attenuation at frequenciesmuch lower than the crossover fre-quency. Unfortunately, C2 adds a neg-ative-phase shift that R3 returns tonearly zero at the design’s crossover fre-quency. Adding C1 introduces a phaselead that compensates for the ceramiccapacitors’ negative effects. WithoutC1, the filter’s 180 phase shift wouldreduce the regulator’s phase margin tonearly zero.

The phase angle starts increasing ata frequency that C1 and R1 determine,and they introduce a zero in the phase-plane plot at that frequency (Figure 5).At a frequency that C1 and R3 deter-mine, a pole in the phase-plane plotterminates the phase angle’s increase.The geometric mean of the pole and

zero frequencies determines the maxi-mum phase-angle boost.

As a starting point, you can place thefirst pole, which C2 and the parallelcombination of R1 and R2 determine, ata low frequency, such as 100 Hz. Next,adjust the values of C2 and R3 to set thefirst zero’s frequency at 1 kHz, which ismuch less than the gain curve’s 0-dBcrossover frequency. Finally, set thezero that C1 and R1 introduce to a fre-quency that’s at least a factor of twobelow the zero-gain crossover fre-quency to ensure a 45 phase marginat the crossover frequency. The Bodeplot in Figure 5 features a 30-kHz reg-ulation-loop bandwidth that providesgood transient response and more than45 of phase margin to ensure good sta-bility.EDN

R E F E R E N C E“Optimal Feedback Amplifier

Design For Control Systems,” VenableIndustries, www.venable.biz/tp-03.pdf.

1

JULY 20, 2006 | EDN 91

power switch IC1 “sees” a capacitancethat’s 36 times larger due to the mul-tiplicative effect of the tapped induc-tor’s turns ratio.

Measuring only 5.663.4 mm,Coiltronics’ (www.coiltronics.com)CTX02-17409 tapped inductor, L1,and Linear Technology’s (www.linear.

com) LT1949 monolithic regulator,IC1, available in an eight-lead MSOPpackage, present small pc-board foot-prints. When you implement the cir-cuit on a single-layer pc board, theentire circuit occupies less than 1.9 cm2

of board space (Figure 3). For bestresults, review the board-layout sug-gestions in the device’s data sheet (Ref-erence 1) and use multilayer-ceramiccapacitors for C1 and C3.EDN

R E F E R E N C Ewww.linear.com/pc/productDetail.

do?navId=H0,C1,C1003,C1042,C1031,C1061,P1958.

designideas

Figure 3 The entire boost-converter circuit occupiesa footprint of less than1.51.25 cm on a single-sided pc board.

Figure 2 For a 3V-dc input (lower trace, horizontal line), the voltage at regula-tor IC1’s SW pin reaches a peak of approximately 18V (lower trace, pulsedwaveform). The 1-to-6 step-up turns ratio of inductor L1 further increases thepeak output voltage to 160V (upper trace) to produce 100V dc. The uppertrace’s lower limit goes to 6VIN(18V) due to the tapped inductor.

1

A step-down SMPS (switched-mode power supply) efficiently

converts unregulated power to a regu-lated output voltage. However, un-wanted switching-induced ripple andinput transients may appear on the out-put. Applying noisy power to an RFpower amplifier can inject spurious sig-nals or modulated noise into the broad-cast spectrum. Analog- and RF-systemengineers favor traditional low-noisepower-supply designs that comprise atransformer, rectifier, and filter followedby a linear voltage regulator. A low-dropout linear regulator’s low outputnoise and high PSRR (power-supplyrejection ratio) ensure clean power thatimposes no interference on a poweramplifier’s output.

Unfortunately, a transformer-and-

rectifier power supply delivers a fluctu-ating output voltage that depends on itsinput voltage. As the difference be-tween its input and output voltageincreases, a low-dropout regulator’s effi-ciency decreases, and its power dissi-pation increases. To remain in regula-tion at low ac-line voltages, even a low-dropout regulator requires a certainamount of head-room input-to-outputvoltage.

To overcome the disadvantages in-herent in both circuits, you can use anSMPS to maintain high efficiency anda low-dropout regulator to reduce theoutput noise and ripple voltage of theSMPS. Setting the output voltage ofthe SMPS slightly higher than the low-dropout regulator’s minimum dropoutvoltage reduces the regulator’s power

dissipation, accommodates the voltagemargin you need for good switching-noise rejection, and maintains high effi-ciency. The regulators’ PSRRs add, andthe combined circuits’ PSRR exceedsthat of either the regulator or theSMPS alone.

Figure 1 shows a cascade circuit com-prising an SMPS followed by a linearregulator. This circuit’s output voltageranges from 1.5 to 5V at an output cur-

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

AUGUST 3, 2006 | EDN 81

Low-dropout regulator, SMPS cascadesuppress ripple, maintain efficiencyScot Lester, Texas Instruments, Dallas, TX

IC2TPS62300YED

IC1TPS736XXDCO

FB

ADJ

EN

VIN

VOUT

SYNC

SW

GND

D2 D1

C2

B2

A2

C1

B1

A1

V+

UNREGULATEDINPUT

R3768k

C110 F

C210 F

C40.1 F C3

47 F

L12.2 H

R4100k

RB1k

R131.6k

R210k

RT2.61kVSET

IN

EN

GNDGND

1

5

6

3

2

4

OUT

NRFB

VCCOUTPUT

VOUTVPS

D Is Inside82 Novel circuit isolates tempera-ture sensor from its host

86 Find resistor values for arbitraryprogrammable-amplifier gains

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 Connected in cascade, a low-dropout linear regulator and a switched-mode power supply improve output-volt-age ripple and maintain overall efficiency. (Note: In IC1’s part designation, “XX” represents the regulator’s output voltage.)

Temperature sensors must some-times operate at locations whose

return potentials differ considerablyfrom that of the data-acquisition sys-tem’s common—that is, equipoten-tial—ground. In consequence, the tem-perature sensor’s support circuitry mustprovide galvanic isolation between thesensor and its data-acquisition system.

Also, the data-acquisition system sel-dom provides an isolated source ofpower for the sensor. The circuit in Fig-ure 1 solves both problems by isolatingthe sensor’s signal and power supply.

The complementary, fixed-frequencysquare-wave outputs of a power-trans-former driver—IC1, a Maxim (www.maxim-ic.com) MAX845—drive a Halo

Electronics (www.haloelectronics.com)TGM-010P3 1-to-1-to-1 transformerwith dual primary windings and a sin-gle untapped secondary winding (Ref-erence 1). The secondary windingfeeds a Graetz-bridge rectifier that gen-erates approximately 4.5V to powerIC2, a Maxim MAX6576 sensor. Com-bining a temperature sensor, signal-pro-cessing electronics, and an easy-to-usedigital-I/O interface in a low-cost pack-age, the MAX6576 draws little currentfrom a single supply source and main-tains its specified accuracy over a 3 to5V supply-voltage range.

rent as high as 400 mA. Although afixed 6V supply powers the cascaded cir-cuit, its design accommodates any inputvoltage at least 0.5V higher than thecascaded pair’s desired output voltage.

Adjusting the reference voltage,VSET, over 0 to 1.105V linearly variesthe circuit’s output voltage. Resistors R1and R2 and reference voltage VSETdetermine the low-dropout regulator’soutput voltage and thus the cascadedpair’s output voltage. Resistors RT, RB,R3, and R4 divide VSET to maintain theSMPS’ output voltage, VPS, at a con-stant 0.2V higher than the regulator’soutput voltage, reducing the regulator’spower dissipation to 80 mW at full out-put current and any output voltage.

At its maximum output current of400 mA, the cascaded supply reachesa maximum efficiency of 89% with a6V input and a 4.69V output (Figure2). The overall efficiency decreases asthe output voltage decreases. Figure 3compares the PSRRs of the SMPSalone and of the SMPS cascaded withthe regulator, which improves PSRR by46 dB at 500 Hz—essentially that of theregulator alone at 500 Hz.

Over a frequency range of 100 Hz to100 kHz, the low-dropout regulatorimproves PSRR by at least 25 dB (Fig-ure 3). Circuit-layout and -measure-ment techniques compound the diffi-

culty of making accurate small-signalmeasurements, and the graph’s PSRRvalues may not appear additive. The lin-ear regulator governs the circuit’sswitched-load transient response,

which may represent an improvementover the response of the SMPS. How-ever, the cascade circuit’s low outputripple and high efficiency make the cir-cuit well worth investigation.EDN

designideas

82 EDN | AUGUST 3, 2006

72

76

80

84

88

92

1.5 2 2.5 3 3.5 4 4.5 5

OUTPUT VOLTAGE (V)

EFFICIENCY (%)

Figure 2 The regulator cascade’s combined efficiency improves as theunregulated output voltage increases.

10 100 1000 10,000 100,000 1 MILLION

100

90

80

70

60

50

40

30

20

10

0

PSRR(dB)

FREQUENCY (Hz)

SWITCHED-MODEPOWER SUPPLY

LOW-DROPOUTREGULATOR

CASCADED PAIR

Figure 3 The power-supply rejection ratio improves significantly (blue trace)when you cascade switched-mode (yellow trace) and linear (red trace) volt-age regulators.

Alfredo H Saab and Tamer Mogannam, Maxim Integrated Products Inc, Sunnyvale, CA

Novel circuit isolates temperature sensor from its host

If you connect the sensor as Figure1 shows, it operates as an absolute tem-perature-to-period converter and pro-vides a nominal conversion constant of10 sec/K, which, at room tempera-ture, yields a period of approximately2.980 msec—a frequency of 335 Hz.You can adjust the conversion constantfrom 10 to 640 sec/K. Note thatlonger conversion constants allowmore signal-integration time to mini-mize noise effects. The sensor’s sym-metrical square-wave output drivesNPN transistor Q2’s base through R4, a10-k resistor. A 390 resistor, R3,serves as Q2’s collector load and con-nects to the same lines that deliverpower to the temperature sensor.

When Q2 conducts, it draws an asym-metrical power-supply current thatexceeds the supply current during thesensor output’s positive half-cycle.

In IC1’s sensor output-to-groundreturn on the data-acquisition system’sside, resistor R2 and capacitor C2 shuntQ1’s base-emitter junction. The valuesof R2 and C2 ensure that the sum ofIC2’s current and transformer T1’s mag-netizing current cannot drive Q1 intoconduction. When Q2 conducts, itdraws about 12 mA from the isolated4.5V power-supply line. Reflecting tothe primary, Q2’s conduction currentflows from the 5V supply into IC1, outthrough its ground terminals, and part-ly through R2. The voltage drop across

R2 exceeds Q1’s base-emitter voltagethreshold and supplies sufficient basecurrent to turn on Q1.

Thus, when Q2 conducts, so does Q1,which copies IC1’s isolated square-waveoutput to Q1’s collector circuit. As thewaveforms of figures 2 and 3 show, Q1’soutput rise and fall times, jitter, andpropagation delay total about 2 sec.The equivalent measurement error dueto timing jitter amounts to less than0.1K at the fastest conversion constantof 10 sec/K. Varying the circuit’s sup-ply voltage through a range of 4.5 to5.5V introduces an error of less than0.1K. The output at Q1’s collector cansink several milliamperes at a voltageexcursion of 0 to 5V.

designideas

84 EDN | AUGUST 3, 2006

5V

NOTE: D1 THROUGH D4: MBR0520L.

IC1MAX845

VCC T1

FSD1

D2GND2GND1

SD

IC2MAX6576

VCC

Q22N3904

R410k

R51k

R3390

C31 nF

C220 nF

C410 F

D3

D4

D2

D1

OUT TS0

TS1

GND

0T

5V

Q12N3904

R275

C10.1 F

R12.2k

OUT

INSULATIONBOUNDARY

Figure 1 Transformer T1 isolates the temperature sensor, IC2, from the equipment under test. The period of IC1’s digitaloutput varies as a function of temperature. The circuit’s output period varies at a rate of 10 sec/K. User-selected scalefactors range from 10 to 640 sec/K.

0V

2V/DIV

0V

1 SEC/DIV

MAX6576 OUTPUT

OUTPUTFROM Q1'S

COLLECTOR

Figure 2 Measured from the positive-going edge ofIC2’s output to the circuit’s output at Q1’s collector, therelative jitter averages less than 1 sec.

0V

2V/DIV

0V

1 SEC/DIV

MAX6576 OUTPUT

OUTPUTFROM Q1'S

COLLECTOR

Figure 3 As in Figure 2, Q1’s average output jitter withrespect to IC1’s negative-going output also averagesless than 1 sec.

designideas

86 EDN | AUGUST 3, 2006

When available fixed-gain values match designrequirements, a PGA (programmable-gain-amplifier)

IC offers a drop-in choice, but what does a designer do whena suitable PGA is unavailable? Before the PGA’s advent, acircuit designer who needed selectable, fixed amounts of gainchose a suitable operational amplifier and designed aswitched-resistor gain-setting network. This Design Idea dis-cusses two methods of designing the desired resistive net-work.

Figure 1 shows a series-ladder-resistor network compris-ing a string of resistors whose junctions connect to switch-selectable taps that determine the circuit’s gain. Little cur-rent flows through the switch, and the resistance of theswitch thus doesn’t affect the design. A circuit with N dis-crete-gain values requires an N-position switch, usually ananalog multiplexer, and N1 resistors in its ladder. Equa-tion 1 describes the circuit’s gain in the general case:

You can solve Equation 1 for the resistor summations andexpand a few terms as follows:

and

Find resistor values for arbitraryprogrammable-amplifier gainsSid Levingston, DML Engineering Inc, Aloha, OR

Figure 1 A series-resistor-ladder network and a sin-gle-pole, multiple-throw switch form a custom-valueprogrammable-gain amplifier.

+ VOUT

VIN

R1

R2

S1

R[N+1]

GN TAP

G1 TAP

G2 TAP

Figure 2 In a parallel-resistor-ladder network, connecting oneresistor at a time in parallel with R1 determines the circuit’sgain.

+ VOUT

VIN

R1

R2

RG

S1

SNRN GN TAP

G1 TAP

G2 TAP

This design can accommodate tem-perature-to-frequency converters andother types of temperature sensors.For further information on IC1 andIC2, review the devices’ data sheetsand the data sheet for the MAX845evaluation kit (references 2, 3, and4).EDN

R E F E R E N C E S“PCMCIA DC/DC Conversion

Isolation Modules,” Halo ElectronicsInc, www.haloelectronics.com/pdf/lowpower-oper.pdf.

“Isolated transformer driver forPCMCIA applications,” Maxim Inc,October 1997, http://pdfserv.

maxim-ic.com/en/ds/MAX845.pdf.“SOT Temperature Sensors with

Period/Frequency Output,” Maxim Inc,April 1999, http://pdfserv.maxim-ic.com/en/ds/MAX6576-MAX6577.pdf.

MAX845 Evaluation Kit, Maxim Inc,October 1997, http://pdfserv.maxim-ic.com/en/ds/MAX845EVKIT.pdf.

1

2

3

4

(1)

(5)

(4)

(3)

(2)

(6)

Next, normalize R1 to 1 and solve the equations for R1:

and

A network that synthesizes N gain values results in anNN matrix whose upper echelon equals the desired gainsminus one, in ascending order, and its lower echelon equalsnegative one. To produce the resistor values for the desiredgains, invert the matrix and calculate its dot product witha unity matrix. For example, a circuit requiring four gain val-ues of three, five, 24, and 50 also requires five resistors. Stuff-ing and solving the matrix yields:

Scale the resistors’ values to 1 k and select the closestavailable standard resistor values to produce gains of:

Figure 2 shows a parallel-resistor-ladder network. To selecta gain value, connect an additional resistor in parallel withthe other resistors. A circuit with N discrete gains requiresN resistors in the ladder; an additional gain resistor, RG; andN1 switches. Equation 14 describes the circuit’s gain inthe general case:

and Equation 15 describes the parallel-resistor combinationfor each gain:

The nth value of RP equals the nth1 value of RP in par-allel with the ladder’s nth resistor. Solve the following equa-tions for the nth resistor value:

and

To find the desired network’s resistors, select the desiredgain values and RG and then use Equation 14 to calculatethe parallel values. Use the resulting values to solve Equa-tion 15 and find the required resistor values. As in the pre-vious example, a circuit must produce gain values of three,five, 24, and 50. Four gain values require four resistors. LetRG1. Solving Equation 14 for the parallel-values matrixyields:

Substituting these values into Equation 15 yields the resis-tors’ values:

and

Scaling to 1 k and selecting the closest available stan-dard-value resistors yields gains of:

Reference 1 provides a review of the matrix math.EDN

R E F E R E N C EFreeman, Larry, “Review of Matrices,” Math Refresher,

Dec 19, 2005, http://mathrefresher.blogspot.com/2005/12/review-of-matrices.html.

designideas

88 EDN | AUGUST 3, 2006

1

(7)

(8)

(9)

(12)

(10)

(11)

(13)

(14)

(24)

(15).

(16)

(20)

(19)

(18)

(17)

(21)

(22)

(23)

The ultralow-cost, two-digit-counter circuit in Figure 1 rep-

resents an attempt to reduce the num-ber of components using a mostly soft-ware approach and a low-cost micro-controller, the PIC16F84A. The cir-cuit lacks the current-limiting resistorsthat normally connect to a seven-seg-ment LED display’s pins because a soft-ware routine lights only one of the dis-play’s segments at a time, first in the 10sdisplay and then in the units display.Doing so keeps the circuit’s maximumcurrent consumption at a nearly con-stant level, even if you add a third LEDdisplay to implement a three-digitcounter. The circuit also lacks digit-selection switching transistors that clas-

sic multiplexed circuits’ switchingtransistors typically use, and the circuitincludes one common-cathode and onecommon-anode display. The reason forthis approach is that each of the micro-processor’s I/O Port A and Port B linescan assume one of three states: high,low, and floating—that is, high imped-ance. Programming a line as an inputplaces it in a high-impedance state,which turns the display off.

In addition, the program drives onlyone segment at a time and executes thefollowing sequence: To drive the 10sdisplay, program the line RB0 outputand drive it high to light the corre-sponding segment of the common-cathode display and then program RB0

as an input. Repeat this procedure forlines RB1 through RB6. To drive theunits display, repeat the process whileapplying a low output from RB0 todrive the common-anode display. Fig-ure 2 shows the circuit’s timing dia-gram. The prototype display uses King-bright’s (www.kingbright.com) SC52-11EWA (DS1) and SA52-11EWA(DS2) high-efficiency, seven-segmentdisplays that emit 2000 to 5600 cd ata forward current of 10 mA. At a for-ward current of approximately 5 mA,the displays remain readable.

Early motion pictures displayed at an18-Hz rate, which produces marginalflicker. The software executes at a rateof 180 Hz, or 10 times the minimumflicker rate. Each of the display’s sevensegments must illuminate for an inter-val of 1/(1807) sec, or approximate-ly 0.8 msec. To simplify the timing rou-tine (section Delay3 of Listing 1, avail-able at www.edn.com/060817di1), thesoftware uses a refresh interval of 1msec.

Although this approach providesadequate segment-drive current, thedisplay’s internal LEDs carry a 3V max-imum reverse-voltage rating. Drivingany I/O line high applies forward biasto one segment of the common-cath-ode digit but applies reverse bias to the

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

AUGUST 17, 2006 | EDN 69

Ultralow-cost, two-digit counterfeatures few componentsNoureddine Benabadji, University of Sciences and Technology, Oran, Algeria

VDD

VSS

IC1PIC16F84A

C118 pF

C218 pF

RB0

RB1

RB2

RB3

RB4

RB5

RB6CLK IN

CLK OUT

5

6

11

12

10

9

8

7

F

G

E

D

C

B

A

DS1SC52=11EWA

(10s)

DS2SA52=11EWA

(UNITS)ID

R1180 OR

220

R310k

ID

R2180 OR

220

14

4

15

16

4-MHzCRYSTAL

VCC2.7V

VCC2.7V

VCC2.7V

MC LR

NOTE: SELECT R1 AND R2 FOR DISPLAY CURRENT, ID, OF 5 mA AT OPERATING VCC.

D Is Inside70 Two-wire, four-by-four-key key-board interface saves power

74 Gain-of-three amplifier requiresno external resistors

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 This low-cost, two-digit counter uses few components.

You can use a microcontrollerthat includes an ADC to design

a two-wire-plus-ground keyboard in-terface. For example, you can use aresistive voltage divider to identify apressed key (Reference 1). A micro-controller’s integrated ADC typicallypresents an input resistance on theorder of hundreds of kilohms, and, foradequate accuracy, its keypad divider

should comprise relatively low-valueresistors of 10s of kilohms. However, inbattery-powered systems, a resistivedivider can consume a few hundredmicroamperes, forcing a designer tochoose an alternative classic digital-matrix array of switches and multipleI/O lines. Moreover, portable-equip-ment designs typically place constraintson the number of components.

To satisfy both requirements, the cir-cuit in Figure 1 uses a matrix keypadand a resistor network divided into tworow and column sections. For the four-by-four-key keypad, seven resistors aresufficient to encode any pressed key, andthe circuit consumes power only whilea key remains closed. Conversely, withno keys pressed, the standby currentapproaches zero. Using only two valuesof resistors, let RARBRCR1 andRDRERFRGR2. Assigning valuesfrom zero to three for the keys’ x and yaddresses, you can calculate the voltageacross resistor RG for any key closure bysolving the following equation:

corresponding segment of the com-mon-anode display. The 16F84A re-quires a minimum of 2V for operation,

and thus the circuit must operate in a2 to 3V power-supply range. The assem-bler source code in Listing 1 counts

from 0 to 99 sec and serves as an unop-timized proof-of-concept software testbed for the display.EDN

designideas

70 EDN | AUGUST 17, 2006

RB0 (SEGMENT A)

RB1 (SEGMENT B)

RB2 (SEGMENT C)

RB3 (SEGMENT D)

RB4 (SEGMENT E)

RB5 (SEGMENT F)

RB6 (SEGMENT G)

10sDIGIT

UNITSDIGIT

REPEATED 160 TIMES

DISPLAY ON(349.633 MSEC)

DISPLAY OFF(651.78 MSEC)

HIGH Z

HIGH Z

HIGH Z

HIGH Z

HIGH Z

HIGH Z

HIGH Z

TIME

Figure 2 The timing diagram illustrates segment- and digit-drive intervals.

Stefano Salvatori, University of Rome, Rome, Italy, and Gabriele Di Nucci, EngSistemi, Rome, Italy

Two-wire, four-by-four-key keyboardinterface saves power

Driving the resistor array from VREF,the ADC’s reference voltage, allowsyou to perform a ratiometric conversionthat eliminates errors in key encodingdue to fluctuations in VREF. The fol-lowing equation describes the voltage-division ratio, r(x,y), for any keystroke.

The ratio pR1/R2 represents theratio between row- and column-groupresistors’ values. For p4, you calculate16 values of r(x,y), in the [1/16, 1]range, as a function of the pressed key’sposition. In general, the minimum dif-ference between r partitioning ratios

occurs for the nearest keys as the (3,2)and (3,3) x,y indexes indicate. For anN-bit ADC and a ratio of p4, theADC should have a resolution that sat-isfies the following equation: 2r(3,2)r(3,3)1511612401.Note that the reciprocal of 240(0.0041...) exceeds the reciprocal of 28,and the circuit thus requires an ADCcapable of at least 8-bit resolution(N8 bits).

Unfortunately, standard-value com-ponents with nominal tolerance, T,cannot provide an ideal solution to thisequation. Instead, you calculate a par-titioning-ratio difference, dr(3,2)r(3,3), for the worst-case condition.The lowest value of d occurs for a min-imum value of RG and RD and the max-imum value of RA, RB, RC, RE, and RF.You can account for all the resistors’values and define a generic ratio, p, for

the nominal values of R1 and R2:

The same value of T applies to allresistors. If n8 and p4, the previousequation yields a solution of T0.018,which indicates that resistors of 1%tolerance correctly encode 16 keys.Moreover, if you now impose the cho-sen fixed tolerance, T, you can solve theequation to obtain the required limiton the p ratio between the values of R1and R2. If T0.01, the solution to theequation becomes p4.074.

The circuit in Figure 2 uses Freescale’s(www.freescale.com) Nitron MC68HC-908QT4 microprocessor, which servesas a test bed for a keypad based on theabove-calculated values, and uses pow-

designideas

72 EDN | AUGUST 17, 2006

X

Y3

3

2

1

0

2 1 0

RC RB RA

RD

RE

RF

RG

VOUT

VREF

S(3,3) S(2,3) S(1,3) S(0,3)

S(3,2) S(2,2) S(1,2) S(0,2)

S(3,1) S(2,1) S(1,1) S(0,1)

S(3,0) S(2,0) S(1,0) S(0,0)

Figure 1 A two-wire resistive voltage-divider interfaceencodes a four-row-by-four-column keypad.

IC1MC68HC-908QT4 * 0 D

7 8 9 C

4 5 6 B

1 2 3 A10k

10k

10k

10k

40.2k 40.2k 40.2k VREF=VCC

PERIPHERALS

1

2

8

#

Figure 2 Using the microcontroller’s analog reference-voltageoutput and ratiometric analog-to-digital conversion ensurescorrect encoding of the keypad.

TABLE 2 TWO-KEY OUTPUT CODESKeys pressed Resistance ()

C+# 141 to 142C+0 134 to 135C+* 132B+# 109B+0 98B+9 91B+8 88A+8 76A+7 70 to 71A+6 68

TABLE 1 SINGLE-KEY OUTPUT CODESKeys pressed/resistance ()

X3 2 1 01/ 2/ 3/ A/

3 15 to 16 21 32 63 to 644/ 5/ 6/ B/

2 17 23 36 857/ 8/ 9/ C/

1 18 25 42 127*/ 8/ #/ D/

0 19 28 51 255Note: The figures preceding the slashes representthe keypad’s key labels.

Y

designideas

74 EDN | AUGUST 17, 2006

Analog Devices’ ADA4862-3comprises three wideband am-

plifiers, each configured by an internal,fixed-value resistive-feedback network

as a noninverting gain-of-two amplifi-er. Due to its internal feedback net-works, the device offers a bandwidth of300 MHz and excellent insensitivity tostray capacitance, variations in pc-boardlayout, and proximity of other devices.According to its specifications, each ofIC1’s three internal amplifiers offers

Gain-of-three amplifierrequires no external resistorsMarián Štofka, Slovak University of Technology, Bratislava, Slovakia

er-supply voltage VCC as the resistormatrix’s reference voltage, VREF. To sat-isfy the requirement for p(4.074p4), use R110 k1% toleranceand R240.2 k1% tolerance, bothstandard values that the E48 seriesoffers. Table 1 lists output codes corre-sponding to 16 individually pressed keys,and Table 2 lists data obtained whensimultaneously pressing two keys andillustrates that two-key combinationscan evoke special functions.

If your application requires a micro-controller that lacks an internal inter-

rupt that the ADC generates, you canconnect an external comparator to theoutput voltage in Figure 1. Set thecomparator’s threshold lower than thelowest voltage developed at the outputvoltage—approximately VREF dividedby 16 in the example—and the com-parator’s output serves as a keypad-interrupt source for the microcontroller.

Note that a microcontroller with a10-bit ADC, such as a Freescale MC68-HC908QB or a Texas Instruments(www.ti.com) MSP430F11 can servicea five-row by six-column keypad

matrix encoded by 10 resistors. Re-peating the analysis shows that a row-to-column p ratio of 5 to 5.51 and arequired resistor tolerance of less than4.3% correctly encode the keys. Youcan use values of 10 k for R1 and 51.1k or 53.6 k for R2 of the 1%-tol-erance E48 series.

R E F E R E N C EAmorim, Vitor, and J Simões,

“ADC circuit optimizes key encoding,”EDN, Feb 4, 1999, pg 101, www.edn.com/article/CA56657.

1

Figure 1 A one-IC amplifier with a voltage gain of three provides flat response to more than 60 MHz.

+

A3

R550

R550

+

A1

R550

R550

+

A2

R550

R550

IN

13

10

9

12

1 2 3 14 5 11

8 6 4

7

C14.7 pF

C2100 nF

C347 nF

IC1ADA4862-3

+VS=2.5V

VS=2.5V

OUT

NOTES:CONNECT TO VS FOR ENABLE.CONNECT TO +VS FOR DISABLE.

three gain configurations—two, one, ornegative one (Reference 1). When youconfigure it for a gain of two, a cascadeof two or three amplifiers yields gains offour or eight, respectively. If your appli-cation requires a gain of three, you canuse the circuit in Figure 1. Amplifier A3serves as an impedance converter witha net voltage gain of one and a low-impedance driver for A1’s gain-settingnetwork. Amplifier A2 provides a gainof two at its noninverting input.

In addition, A3 introduces the prop-er time delay (phase shift) in A1’sinverting-input path and thus roughlyequalizes the time delay in A1’s nonin-verting signal path. This configurationimproves the circuit’s dynamic per-formance over that you can achievewhen A1’s inverting input connectsdirectly to the input signal. A 4.7-pFchip capacitor that connects from volt-age follower A3’s output to ground

reduces the voltage follower’s outputimpedance at frequencies of 100 MHzand above to ensure A1’s stability.

If you configure it as a differentialamplifier, A1 amplifies the input signalby a factor of two at its noninvertinginput and by a factor of negative one atits inverting input. The final voltage atA1’s output comprises the algebraic sumof both components: VOUT4VINVIN3VIN. In a conventional voltageamplifier, reducing negative feedbackincreases the overall gain. In contrast,cascading amplifiers with negative-volt-age-feedback networks only slightly

reduces the circuit’s bandwidth. The netgain decrease at a frequency of 65 MHzamounts to 0.1 dB, or approximately1.15% of a single gain-of-two amplifi-er’s dc gain. For the gain-of-three ampli-fier in Figure 1, the gain decrease at 65MHz amounts to approximately 2.3% ofthe circuit’s dc gain.

For the best high-frequency perform-ance, connect the ADA4862’s internalamplifiers as Figure 1 shows to minimizethe lengths of the device’s external inter-connections. You can cascade addition-al ADA4862-3 ICs to produce any gainexpressed as 3M2N, where M and N rep-resent integers, including zero—that is,gains of six, nine, 12, and so on.EDN

R E F E R E N C EADA4862-3 data sheet, Analog

Devices Inc, www.analog.com/UploadedFiles/Data_Sheets/360747397ADA4862_3_a.pdf.

designideas

76 EDN | AUGUST 17, 2006

1

MORE AT EDN.COM

For more Design Ideas, visitwww.edn.com/designideas.

For our best entries, go towww.edn.com/bestofdesignideas.

+

+

The circuit in Figure 1 uses onlyfive I/O lines to drive a dot- or

bar-graph display of 20 LEDs. Althoughthis version of the design uses a smalland inexpensive one-time-program-mable microprocessor, such as a Mi-crochip (www.microchip.com) PIC12-C508A, you can use other micro-processors with N I/O lines to drive asmany as N(N1) LEDs. For softwaredevelopment or modification, you can use a PIC12C508A-JW repro-grammable-EPROM version of thePIC12C508A, or you can substitute aless expensive PIC16F84A with flashmemory.

To avoid application of excessivereverse voltage to the LEDs, the cir-cuit’s power supply, VDD, must notexceed 3V dc. You can drive other types

of loads and provide electrically isolat-ed interfaces by replacing the LEDswith appropriately rated optocouplers.For demonstration purposes, IC1’sinput line, GP3, connects to a push-button display-mode-selector switchand a pulldown resistor that simulatesa digital-input-signal source with a volt-age amplitude of 3V p-p.

Listing 1, available with the onlineversion of this Design Idea at www.edn.com/060901di1, performs a varietyof functions. To conserve batterypower, the basic software drives oneLED at a time in dot or bar mode witha minimum amount of current. Ap-proximately 2 mA flashes a high-brightness LED. The software includesa delay routine that solves the problemof contact bounce. Tests show that a

miniature pushbutton switch requires adelay of at least 1 msec for successfuldebouncing.

Consuming fewer than 256 words,the software avoids a C12C508A pro-gramming restriction that requiresplacement of subroutines only in page0. Other features of the softwareinclude a two-level stack, the use of filescommon to both the PIC12C508A and

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

SEPTEMBER 1, 2006 | EDN 71

PIC microprocessor drives 20-LED dot- or bar-graph displayNoureddine Benabadji, University of Sciences and Technology, Oran, Algeria

VDD

MCLR

CKIN

RB3GP3

5

9

4

8

VSS

RB0GP0

RB1GP1

RB2GP2

RB4GP4

RB5GP5

3V

14 1

4

16

R310k

C20.1 F

IC1

C122 pF

R210k

R456

R556

R656

R756

R856

R14.7k

S1

3V

67

76

85

103

112

PIC12C508A/PIC16F84A

LED8

LED7

LED6

LED5

LED4

LED3

LED2

LED1

LED19

LED20

LED15

LED16

LED17

LED18

LED9

LED10

LED11

LED12

LED13

LED14

VCC

D Is Inside72 PC’s serial port controls pro-grammable sine-wave generator

74 I2C interface connectsCompactFlash card to microcon-troller

76 IC and DMM form direct-read-out temperature probe

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 A dot- or bar-graph display uses either a one-time-programmable PIC12C508A or, for experimentation, a repro-grammable and reusable PIC16F84A. Use high-brightness diodes for LED 1 through LED 20.

This Design Idea describes a cir-cuit that uses a PC’s serial port

to control a sine-wave generator thatcovers a frequency range of 2 Hz to 20kHz in 1-Hz steps (Figure 1). The cir-cuit’s output voltage of approximately2.2V p-p remains constant over theentire frequency range. The circuit’ssignal source, a Linear Technology(www.linear.com) LTC6904, IC1, con-sists of a digitally programmablesquare-wave oscillator that, withoutusing a clock crystal, covers a frequen-cy of approximately 1 kHz to 68 MHzat 0.1% resolution and a few percent-age points of accuracy. The LTC6904features an I2C serial-communicationsinterface that controls the output fre-quency according to: OSCCLK2a

2078 Hz/[2(b/1024)]. The variables“a” and “b” represent 4- and 10-bit dig-ital codes, respectively, and the equa-tion’s frequency unit, OSCCLK, is inhertz.

The OSCCLK output from IC1 at Pin6 drives IC2, a 14-stage 74HC4020binary counter whose outputs at Q4and Q10 serve as the clock and inputsignals for IC3, a Maxim (www.maxim-ic.com) eighth-order, switched-capac-itor MAX291 lowpass filter.

The 3-dB corner of the filter’s fre-quency response occurs at one-one-hundredth of IC3’s clock frequency.Fixed at one-sixty-fourth of the clock-signal frequency, only the input squarewave’s fundamental frequency can passthe filter without undergoing consid-

erable attenuation. The filter’s eighth-order response removes higher orderharmonics, and the filter’s output thusconsists of a sine wave at the input’sfundamental frequency. The filter’sclock and input always occur in a 64-to-1 frequency ratio, and the sinewave’s output amplitude thus remainsconstant over the entire frequencyrange.

To generate a 1-kHz sine wave, thecircuit requires a filter clock at a fre-quency of 64 kHz, which sets the OSCCLK frequency 64 times higher, or1.024 MHz. To satisfy the equation, theLTC6904 requires programming con-stants of a09H and b3d8H to gener-ate an OSCCLK frequency of 1023.94kHz and the nearest output frequencyof 999.9 Hz.

Written for IBM-compatible PCs,the C-language program accompanyingthis Design Idea, which is available atwww.edn.com/060901di2, accepts an

the PIC16F84A in the 0CH to 1FHrange, use of the RETLW 00H instruc-tion instead of Return, and avoidanceof the ADDLW and SUBLW instruc-

tions. The software defaults to the dot-display mode. Pressing and holding S1before and during power applicationselects the bar-display mode. Note that

the configuration settings for theMPASM assembler vary according towhich microprocessor you select forprogramming.EDN

designideas

72 EDN | SEPTEMBER 1, 2006

Yongping Xia, Navcom Technology, Torrance, CA

PC’s serial port controls programmable sine-wave generator

CD

RX

TX

DTR

GND

GND

SDI IC1LTC6904

J1TO PC’sRS-232PORT

SCK

ADR

V

OE

CLK

D11N5232

D21N5232

D31N4148

D41N4148

R120k

R220k

C147 F10V

C20.1 F

DSR

RTS

CTS

RIGND

OUTPUT

C40.1 F

R420k

R320k

C30.1 F

1

1

2

2

3

3

4

4

5

6

8

87

8

9

7

6

5CLK

TO 5VPOWER SUPPLY

CLK

GND

VCC

RST

CLK

V IC3MAX291IC2

74HC4020 OP OUT

OP IN

IN

V

GND

1

2

3

4

79

54613121415123

Q4Q1

Q5Q6Q7Q8Q9

Q10Q11Q12Q13Q14

6

7

8

5OUT16

10

11

Figure 1 Three ICs and a few passive components generate sine waves under the control of a PC’s serial port.

output-frequency request, calculatesthe nearest values of programmingcodes “a” and “b,” transmits the codesto IC1, and shows the calculated fre-

quency on the PC’s display. Althougha PC’s serial port delivers RS-232 sig-nals, diodes D1 through D4 limit thevoltages available at Pin 4, the data-ter-

minal-ready pin, and Pin 7, the ready-to-send pin, to levels compatible withthe I2C bus’s SDI and SCK signals,respectively.EDN

designideas

74 EDN | SEPTEMBER 1, 2006

Logging data from a large num-ber of monitored channels usu-

ally requires a lot of memory for stor-ing the measured data. Unfortunately,smaller microcontrollers offer only lim-ited amounts of internal data RAM andEEPROM and may also lack spareaddress and data ports for adding exter-nal memory. Many low-end microcon-trollers include an industry-standardI2C interface for attaching externalADCs, DACs, real-time clocks, andother peripherals.

The circuit in Figure 1 connects aCompactFlash card to a microcon-

troller’s I2C interface through IC1, a 16-bit I2C I/O extender. In memory-mapped mode, an 8-bit-wide data buscontrols the CompactFlash card. Mi-crocontroller IC1’s Port 1 (I/O lines 0through 7) connects to the Compact-Flash card’s data bus and provides readand write access to the card’s data reg-isters. Port 2 provides the card’s addressand control registers and generates theread and write signals.

To write to a register, configure Port1 as an output and write the data to theport. Next, write the register-controldata three consecutive times to Port 2

while toggling the port’s WRN pin fromLogic 1 to Logic 0 to Logic 1 to gener-ate the “write” signal. Address bits A2,A1, and A0 select the register thatreceives the written data. ApplyingLogic 0 to the CE pin while RDN restsat Logic 1 enables the CompactFlashcard. To read from a register, configurePort 1 as an input port and apply threewrites to Port 2 while toggling the port’sRDN pin from Logic 1 to Logic 0 toLogic 1 to generate the “read” signal.

After the three writes, the micro-controller reads Port 1 and makes thedata available. Address bits A2, A1,and A0 address eight internal registersand allow read and write access (Table1). Register 0x00 contains data forexchange between the host and theCompactFlash card. Registers 0x03,0x04, 0x05, and 0x06 specify the track

I2C interface connects CompactFlash card to microcontroller

Fons Janssen, Maxim Integrated Products Inc, Sunnyvale, CA

Figure 1 A 16-bit I/O extender, IC1, and a CompactFlash connector add external data storage to a microcontroller’sI2C bus.

IC1MAX7311

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

AD2

AD1

INT

SCL

SDA

V+ V+

GND

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

AD0

I/O8

D7

D6

D5

D4

D3

D2

D1 A2

A1

A0

D0

D2

D1

D0

A0

A1

A2

D4

D5

D6

D7

CE

D3

CE

RDN

RDN

WRN

RESETN

WRN

12

3

4

5

6

78

9

10

11

12

13

14

15

16

17

18

19

20

21

22

232425

2627

28

29

30

31

3233

34

35

36

37

38

39

40

41

42

43

44

45

46

47

484950

V+

I2C BUS

TO HOSTMICROCONTROLLER

+C110 F

R110k

D11N4148

J150-PIN

COMPACTFLASHCONNECTOR

SEETEXT

designideas

76 EDN | SEPTEMBER 1, 2006

for reading or writing data. Each trackcontains 512 data bytes. The processorindicates reading and writing tracks andother functions by writing to 0x07, thecommand register, and registers 0x01and 0x07 contain error conditions andstatus information.

Two unused pins, 10 and 11, on Port2 are available to drive LEDs that dis-play circuit activity and status. As analternative, the pins can support a user-installed configuration jumper. In thisconfiguration, IC1’s interrupt outputshould connect to the host microcon-troller’s interrupt input so that instal-lation or removal of the jumper can sig-nal the microcontroller to recognize orignore the CompactFlash card. Select-ing a CompactFlash-card connectorwith hot-plugging contacts allows in-sertion or removal of a card withoutswitching off power or disturbing anongoing data-logging process.

With software modifications, a hostmicrocontroller can switch betweentwo CompactFlash cards. Adding a sec-ond MAX7311 supports an additionalCompactFlash card and expands thecircuit’s storage capacity, and the hot-plug feature supports removal of a fullyloaded card for data processing onanother system. Microcontrollers thatinclude hardware-based I2C interfacescan use two relatively simple I2C soft-ware functions to read and write a Com-pactFlash card through IC1’s I/O ports.

The first function is: Write_MAX3711(slv,prt,dat). This procedure

starts the I2C bus and sends a data byte(dat) to a port (prt) on the MAX7311using a slave address (slv). The otherprocedure, Read_MAX3711(slv,prt),starts the I2C bus and reads a data bytefrom a port on the MAX7311 at a slaveaddress. These functions serve asfoundations for two additional func-tions, which read and write to theCompactFlash card’s registers. Thefirst, Write_CF_REG(reg,dat), usesWrite_MAX3711 to place the data onPort 1. Use the same procedure to placethe register address (reg) and othercontrol signals on Port 2. Executingthis function three times while togglingWRN generates the write signal. TheRead_CF_REG(reg) procedure usesWrite_MAX7311 to address the Com-pactFlash card’s register and generatesthe read signal. Invoking Read_MAX7311 then reads the data from the register.

These functions, which in turn readand write the card’s registers, createfunctions that access the Compact-Flash-card sectors: Write_CF(cyl,head,sec). To perform a write opera-tion, this procedure uses Write_CF_REG to designate the CompactFlashcard’s target cylinder, head, and sector

registers (0x03 to 0x06). Next, writing0x30 to the command register config-ures the CompactFlash card to acceptdata. Executing Write_CF_REG 512times writes data in the microcon-troller’s global array to the data regis-ter. The CompactFlash card automat-ically adds this data to the currenttrack. To perform a read operation, theRead_CF(cyl,head,sec) procedure usesWrite_CF_REG to designate the targetcylinder, head, and sector. Next, writ-ing 0x20 to the command register con-figures the CompactFlash card to deliv-er data to the host processor. ExecutingRead_CF_REG 512 times reads all 512bytes through the data register from thecurrent CompactFlash card’s track andplaces the data in a global array.

If the microcontroller lacks sufficientinternal memory to store 512 databytes, the software can write each dig-itized data-point measurement direct-ly to the CompactFlash card. For addi-tional information on controllingCompactFlash cards, review the mate-rial in Reference 1.EDN

R E F E R E N C ECF and CompactFlash specifi-

cation, www.compactflash.org.

TABLE 1 ADDRESSES AND REGISTERSAddress Register Address Register0x00 Data 0x04 Cylinder low0x01 Error/features 0x05 Cylinder high0x02 Sector count 0x06 Select card/head0x03 Sector number 0x07 Status/command

The simple temperature-meas-urement probe in Figure 1 can

serve as an indispensable tool for trou-bleshooting and debugging electroniccircuits. To measure temperature at several points, you can equip IC1, aMaxim (www.maxim-ic.com) MAX-6610, with a probe, or you can perma-

nently integrate one or more devicesinto a pc board or attach them to com-ponents. Resistors R1, R2, and R3 set thecircuit’s temperature-scaled voltageoutput to various values (Table 1). Fig-ure 2 shows the circuit’s representativeoutput versus temperature.

You can display the circuit’s temper-

ature-proportional dc output voltage onany DVM (digital voltmeter) or hand-held DMM (digital multimeter). Thecircuit draws only 200 A from a nom-inal 3V power supply, such as a pair ofAA alkaline cells. A CR2016 lithium-coin cell can operate the circuit con-tinuously for several hundred hours orfor several years if you equip the circuitwith a normally open, momentary-con-tact pushbutton switch.

To produce the error curve in Figure3, immerse the circuit and a platinum-resistance standard thermometer in a

IC and DMM form direct-read-out temperature probe

Alfredo H Saab and Bich Pham, Maxim Integrated Products Inc, Sunnyvale CA

1

temperature-controlled oil bath. Thecircuit’s relative error with respect tothe standard thermometer varies only4C over 40 to 125C. The MAX-6610’s data sheet includes additionalinformation on temperature-measure-ment error and output range.

To apply the circuit as a temperatureprobe, solder a 5-mm length of 1-mm-diameter, uninsulated copper wiredirectly to a small copper pad at IC1’sGND pin. The wire should make ther-mal and electrical contact with theGND pin and thus provide a path oflow thermal resistance from the sensorIC to the point of probing. Glue thewire to the pc board to add mechani-cal support. Heat loss affects the tem-perature measurement’s accuracy, and,to minimize heat loss from the probethrough the pc board, use long and thincopper traces to make electrical con-nections from IC1 to its supportingcomponents.

Applying the MAX6610 as a pc-board temperature sensor differs some-what from using it as a temperatureprobe. For board-temperature sensing,IC1 must reside in intimate thermalcontact with the board. Connect largecopper areas immediately to the IC’spins and use short, thick traces—ornone at all—between the copper areasand the IC’s pins. The copper areasguarantee accurate temperature read-ings by providing thermal contact with

the board and good heat transfer be-tween the board and the sensor.EDN

R E F E R E N C E“Precision, Low-Power, 6-pin

SOT23 Temperature Sensors and

Voltage References,” MAX6610/6611data sheet, Maxim Integrated Prod-ucts, November 2003, http://pdfserv.maxim-ic.com/en/ds/MAX6610-MAX6611.pdf.

designideas

78 EDN | SEPTEMBER 1, 2006

1

TABLE 1 TEMPERATURE-SCALED VOLTAGE OUTPUT10 mV/C 1 mV/C 1 mV/F

R1 (k) 68.1 68.1 68.1R2 (k) 2.8 2.8 19.6R3 (k) Open 2.21 3.32Note: All resistors are of 10% tolerance.

TEMPERATURE (C)

OUTPUTVOLTAGE

(mV)

1500

1250

1000

750

500

250

0

250

500

75050 25 0 25 50 75 100 125 150

NOTE: SCALE FACTOR=10 mV/C.

Figure 2 The circuit of Figure 1 exhibits a nearly linearoutput-voltage-versus-temperature characteristic.

TEMPERATURE (C)

TEMPERATUREERROR VERSUS

STANDARDTHERMOMETER

(C)

8

10

6

4

2

0

2

4

6

8

1050 25 0 25 50 75 100 125 150

Figure 3 Immersed in a temperature-controlled oil bathand compared with a platinum-resistance standard ther-mometer, the circuit of Figure 1 exhibits 2C error over40 to 125C.

IC1MAX6610C1

0.1 F

VCC

SHDN TEMP

REF

GNDR2

R1

S1

R3

+

+

TO DMM INPUTS

BT1CR2016

3V LITHIUM-COIN CELL

NORMALLY OPEN PUSHBUTTONPUSH TO READ

Figure 1 One IC and a few passive parts directly display temperature on anexternal voltmeter. See Table 1 for values for R1, R2, and R3.

When a system’s specificationscall for a lowpass filter with a

steep frequency-cutoff characteristic,an engineer can opt for a “brick-wall”-filter design that features a sharp tran-sition band. For example, in an FMstereophonic-broadcast system, thelowpass filter in the baseband audio’sleft and right channels should have a3-dB cutoff frequency of at least 15kHz, a passband ripple of less than 0.3dB, a stopband start frequency of atleast 19 kHz, a stopband attenuationgreater than 50 dB, and identical phaseresponse for both channels.

The filter should provide adjustablegain to maximize SNR at the audioprocessor’s first stage. The filter’s fre-quency response should also include anotch at 19 kHz to achieve maximumattenuation at the FM-subcarrier pilot-tone frequency and thus minimizephasing problems. To reduce manufac-turing costs, the filter should require noin-process adjustments. Conventional

analog active-filter designs cannot meetthese goals at reasonable cost and com-plexity without time-consuming adjust-ments. This Design Idea outlines anactive-filter-synthesis approach thatreduces a filter’s sensitivity to passive-component tolerances and enablesconstruction of inexpensive, high-orderand highly selective filters.

The design process begins with selec-tion of an appropriate passive-filtertopology—in this example, a seventh-order elliptic filter with 50 input andoutput impedances (Figure 1). Settingthe beginning of the stopband fre-quency span at 18.72 kHz produces anotch at the 19-kHz stereo-pilot fre-quency. Using the following equationto transform each component’s im-pedance leaves the filter’s amplitude-versus-frequency response characteris-tics unaltered.

As a result of the transformation, allresistors undergo transformation intocapacitors, and adjusting the value ofparameter k yields reasonable capaci-tance values for using 10%-toleranceparts. In this instance, select a value of2.2 nF for C1:

Inductors transform into resistors,and using 2%-tolerance or better com-ponents meets the circuit’s require-ments. Capacitors transform into“supercapacitors” whose impedanceexhibits a 1/s2 dependence:

Selecting a topology for a passive fil-ter that contains the maximum num-ber of inductors and references allcapacitors to ground yields a trans-formed filter that consists of many resis-tors, several supercapacitors, and onlytwo capacitors. You cannot obtain asupercapacitor as an off-the-shelf com-ponent, but its electrical analog com-prises a few operational amplifiers andresistors (Figure 2). The followingequation defines the gyrator’s inputimpedance, ZIN, with respect toground:

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

SEPTEMBER 14, 2006 | EDN 73

“Brick-wall” lowpass audio filter needs no tuningDiego Puyal and Pilar Molina, University of Zaragoza, Zaragoza, Spain

L273.7801 H

L1560.32 H

L381.741 H

L5722.53 H

L7420.89 H

R150

R250

C1270.08 nF

L4365.31 H

C2192.24 nF

L6264.74 H

C3198.41 nF

SIGNALSOURCE

VIN

INPUTTO

FILTER

OUTPUT

D Is Inside74 Fast-settling picoammeter cir-cuit handles wide voltage range

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 1 This seventh-order, elliptic, lowpass, passive-filter prototype featuresa 15-kHz cutoff frequency and stopband rejection exceeding 50 dB.

Evaluating analog switches, mul-tiplexers, operational amplifiers,

and other ICs poses challenges to IC-

test engineers. A typical test scenariorequires application of a test or forcingvoltage to a device’s input and meas-

urement of any resultant leakage andoffset currents, often at levels of 1 pAor less. In contrast to slow and ex-pensive commercially available auto-mated testers, the low-power measure-ment circuit in figures 1 through 3 canforce a wide range of test voltages andoffer fast settling to maximize device-test throughput. Extensive use of sur-face-mounted components minimizes

Selecting Z1Z31/Cs in the equa-tion, setting capacitor value C at 2.2 nF,replacing impedances Z2 and Z5 withR11 k, and setting Z4R4 yield asolution for Di:

Figure 2 shows the filter’s finalschematic. Potentiometer R1 adjuststhe overall gain, and connecting resis-tors R2 and R26 in parallel with capac-itors C1 and C8 prevents dc blocking.The finished filter design uses medi-um-tolerance resistors, only eightcapacitors, and two LF347 quad oper-

ational amplifiers—few amplifiers fora seventh-order active filter thatrequires no component adjustments tomeet its specifications. Thanks to thedesign’s precise implementation of thepilot-tone-rejection notch, the filter’smeasured attenuation at 19 kHz ex-ceeds 60 dB.EDN

designideas

74 EDN | SEPTEMBER 14, 2006

Rob Whitehouse, Analog Devices, Wilmington, MA

Fast-settling picoammeter circuithandles wide voltage range

IC1ALF347

_

+

IC2DLF347

_

+

GAINADJUSTMENT

R1100k

R2270k

R35.1k

R4110

R1311k

R143.9k

R15470

R1611k

R123.3k

R192.4k

R106.2k

R111.2k

R176.2k

R18360

R243.6k

R25150

R26270k

C82.2 nF

C42.2 nF

C52.2 nF

R2710k

R28100k

C12.2 nFINPUT

OUTPUT

IC1DLF347

_

+

IC2ALF347

_

+

ZIN Z1

Z3

Z5

Z4

Z2

R2011k

R213.6k

R22910

R2311k

C62.2 nF

C72.2 nF

IC2BLF347

_

+

IC2CLF347

_

+

R611k

R5560

R75.6k

R8510

R911k

C22.2 nF

C32.2 nF

IC1BLF347

_

+

IC1CLF347

_

+

GYRATOR

Figure 2 The finished circuit design eliminates inductors and substitutes gyrators as “supercapacitors.” Using medium-tol-erance components and quad op amps to reduce component count minimizes circuit cost.

its pc-board-space requirements andallows packaging of multiple measure-ment circuits close to the test fixture.

The circuit comprises a forcing-volt-age buffer/amplifier, a floating-railpower supply, and an IVC (current-to-voltage converter). Applying a forcingvoltage to a device under test inducesleakage current, which the circuit con-verts to an output voltage proportion-al to the leakage current. In a conven-tional IVC, the current to be measureddevelops a voltage across a shunt resis-tor. The IVC uses a feedback-ammetertopology in which operational amplifi-er IC1, an Analog Devices AD795, sub-tracts an unknown current from a feed-back current and delivers an outputvoltage proportional to the unknowncurrent (Figure 1).

In this design, the input’s dc resist-ance consists mostly of R2 and IC1’seffective input resistance, or slightlymore than 100 at dc. At frequenciesin the power-line range of 50 to 300 Hz,the circuit’s ac impedance averages ap-proximately 10 k, or 1000 times lessthan a typical shunt-resistance IVC’sinput resistance of approximately 10

M. The circuit’s 100-M feedbackresistor, R1, provides a current-to-volt-age-conversion ratio that exceeds theshunt-conversion ratio by a factor of 10.This design settles much faster and pro-vides better interference rejection atpower-line frequencies than shuntconverters. It also reduces unwanted

voltage-divider effects when testingoperational amplifiers’ input currents.

R1 produces a current-to-voltage-conversion ratio of 100 V/pA. Amp-lifier IC2, an AD795, provides an addi-tional voltage gain of 10, boosting theratio to 1 mV/pA and reducing theeffect of errors that differential ampli-

designideas

76 EDN | SEPTEMBER 14, 2006

_

+IC4

OPA551

VFORCEINPUT

R347k

RN45k

RN410k

R415

C2220 pF

3

8 7

6

2

3

1

2

4 5 1V

30V

30V

TO D1A, RN1, AND RN3

(FIGURE 1) TO F1

(FIGURE 3)FLAG V

Figure 2 A gain-of-three high-voltage amplifier derives forcing voltages as highas 22V from voltages of 7V from test equipment.

IC1AD795

C110 pF

R1100M

R2100

VCC

NC

NC

NC

NC

NOTE: RN1, RN2, AND RN3 ARE VISHAY MPM-SERIES RESISTOR NETWORKS.

V

V

VEE

VCC

VEE

D1A

D1

D1B

2 7

6

4

5

1

3

IC2AD795

RN210k

RN210k

2 7

6

4

5

1

RN310k

RN310k

3

V

V

15V

15V

IC3OP1177

2 7

6

4

3

RN15k

RN11k

V

V

TO THEJUNCTION OF

R4 AND F1

DEVICE-UNDER-

TESTINPUT

OUTPUT

1

1

1

3

3

3

2

2

2

J1

Figure 1 This IVC uses a feedback-ammeter topology, which subtracts an unknown current from a feedback current anddelivers an output voltage proportional to the unknown current.

designideas

78 EDN | SEPTEMBER 14, 2006

fier IC3’s CMRR (common-mode-re-jection ratio) introduces. Differentialamplifier IC3, an OP1177, subtracts theforcing voltage from the IVC’s outputand provides a ground-referenced out-put signal.

A back-to-back pair of BAV199diodes, D1A and D1B, protects IC1 fromvoltage overloads by shunting high cur-rents to the forcing-voltage amplifier,IC4, and its protective fuse, F1. Whenthe forcing voltage rapidly slews fromone value to another, the diodes great-ly improve the IVC’s settling time byproviding high-drive currents duringhigh-slew-rate intervals.

Operating from 30V supply rails, alightly compensated, gain-of-three,high-voltage OPA551 amplifier, IC4,derives forcing voltages as high as22V from ordinary ATE (automatic-test-equipment) voltages of 7V (Fig-ure 2). In case of a catastrophicallyshorted device under test, fuse F1 pre-vents further damage by limiting faultcurrent from IC4, which can deliver asmuch as 380 mA of short-circuit cur-rent.

The output of IC4 also drives a reg-ulator circuit that produces 5V float-ing-power-supply voltages referencedto the test-input forcing voltage (Fig-ure 3). This part of the circuit dissi-pates less than 100 mW of power with 30V supplies. Vishay/Siliconix (www.vishay.com) SST505 JFET constant-current regulator “diodes” Q1 and Q4 pro-vide 1-mA constant-current sources,which transistors Q2 and Q3 buffer.Each current-regulator diode carries a45V maximum rating, and the buffersprovide overvoltage protection by lim-iting the voltages applied across thediodes to approximately 3V.

Applying 1 mA to resistors R5 and R6develops the 5V rail voltages. DiodesD2 and D3 compensate for the base-emitter-voltage drops across emitter fol-lowers Q6B and Q7B. Transistors Q6A andQ7A provide overvoltage protectionwhen a defective device under testshort-circuits its power supply to theIVC’s input node. Transistors Q5 and

1

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1

20 15 10 5 0 5 10 15 20FORCE VOLTAGE (V)

MEASUREDCURRENT

(pA)

CURRENT MEASUREMENT

LINEARITY

Figure 4 Over a 20V forcing-voltage span, the circuit produces anunloaded-output current-measurement error of 31 fA/V.

Q1

R76.04k

R853.6k

R1212.4k

R13750

R14750

R1512.4k

R54.99k

R64.99k

C31000 pF

C41000 pF

C50.1 F

F1140 mA

D2BAS16

D3BAS16

R11100

Q2

Q5

SST505

BC856

BCB56BDW1T1

BC856

30V

FROM IC4PIN 6

Q8

Q7B

Q7A

Q6A

Q6B

Q4

Q3

R953.6k

R16100

R106.34k

BC846

BC846

BCB46BDW1T1

BC846BDW

BCB856BDW

SST505

C60.01F

D4MMBD301

VCC

VEE

3

5

44

5

3

30V

Figure 3 This floating-regulator circuit produces 5V floating-power-supplyvoltages VCC and VEE referenced to the test input’s forcing voltage.

designideas

80 EDN | SEPTEMBER 14, 2006

Q8 limit the floating supplies’ outputcurrents by shunting the currentdiodes. Diode D4 protects against polar-ity inversion of the floating-supply railsduring unusual start-up conditions.

In operation, the circuit delivers anoutput of 0.999V/nA over a 4-nAfull-scale input range at an effectivetransresistance of 1 G. The circuit’soutput offset corresponds to approxi-mately 143 fA. Beyond the forced-volt-age span of 22V, the floating-supply-rail voltages begin to saturate, theinput-CMRR limitations of IC3become evident, and the IVC’s outputvoltage becomes nonlinear. Figure 4shows the circuit’s current-measure-ment error of 31 fA/V from the cir-cuit’s unloaded output over a 20Vforcing-voltage span. The differentialamplifier comprising IC3, RN2, and RN3contributes most of the circuit’s gain,and IC1’s low input-bias current con-tributes to the low offset error. Output

linearity over the 20V forcing-volt-age range averages 111 fA p-p.

The circuit’s slew-rate capabilityvaries considerably, but in general theoutput faithfully slews the entire 40Vforcing-voltage span in 100 sec or lessas D1 drives the device under test.Once the high-slew period completes,

the IVC comes out of saturation, andits output becomes an exponentialvoltage with a time constant of 1 msec.The output settles to 100 fA in approx-imately 10.6 msec. Under no-load con-ditions, the circuit consumes approxi-mately 10.2 mA from the 30V sup-plies and 400 A from the 15V sup-plies. The prototype circuit’s layoutoccupies approximately 1.5 in.2 on asingle-sided pc board, and placingcomponents on both sides of a double-sided board would reduce the area to1 in.2 For best performance, the layoutmust include guard rings around theinput terminal and all traces attachedto Pin 2 of IC1. The circuit’s size allowsits placement on a device-under-testfixture to minimize lead lengths andpower-line-induced electromagneticinterference. Although able to meas-ure currents as small as 1 pA, the cir-cuit can accommodate larger currentsby reducing the value of R1.EDN

THE CIRCUIT’S SLEW-RATE CAPABILITYVARIES CONSIDER-ABLY, BUT IN GENER-AL THE OUTPUT FAITH-FULLY SLEWS THEENTIRE 40V FORC-ING-VOLTAGE SPANIN 100 SEC OR LESS.

Certain measurement applica-tions, such as for pH (acidity)

and bio-potentials, require a high-impedance buffer amplifier. Althoughseveral semiconductor manufacturers

offer amplifier ICs featuring low biasand offset-input currents, attaching asensor cable to an amplifier circuit caninflict damage from ESD (electrostat-ic discharge). Figure 1 shows one

unsatisfactory approach to ESD protec-tion. Resistor R1 limits an ESD event’sdischarge current, and diodes D1A andD1B clamp amplifier IC1’s input to itspower-supply rails. Unfortunately,when shunting a pH sensor’s 400-Minput impedance, even low-leakagediodes, such as Fairchild Semiconduc-tor’s (www.fairchildsemi.com) MMBD-1503A, introduce significant offsetvoltages.

The circuit in Figure 2 offers analternative approach. An Analog De-vices (www.analog.com) low-input-bias, low-offset-current AD8603 am-plifier, IC1, serves as a unity-gain inputbuffer. For any normal input, the cir-cuit’s output voltage, VOUT, equals itsinput voltage, VIN. Thus, the voltageacross ESD-protection diode D1A or D1Bapproaches 0V, and neither diode’sleakage current affects the sensor’s out-put signal. Depending on the polarityof an ESD event you apply to the cir-cuit’s input connector, its high-voltagespike discharges through diode D1A orD1B into the positive or the negative

READERS SOLVE DESIGN PROBLEMS

EDITED BY BRAD THOMPSON AND FRAN GRANVILLE

designideas

SEPTEMBER 28, 2006 | EDN 191

High-impedance buffer amplifier’sinput includes ESD protectionEugene Palatnik, Waukesha, WI

IC1AD8603

R11k

R21k

R3270

D1MMBD1503A

D2MMBD1503A

D1A

D1B

D2A

D2B

J1VIN

C20.1 F

C11 nF

VOUT_

+

3V

3V

3V

3V

3V

3V

C30.1 F

1

INPUT

LEAKAGE GUARD

D Is Inside192 Composite-VGA encoder/decoder eases display upgrade

194 Solenoid-protection circuit limits duty cycle

196 SPST pushbutton switch combines power-control, user-inputfunctions

198 Electronic circuit replacesmechanical push-push switch

What are your design problemsand solutions? Publish them hereand receive $150! Send yourDesign Ideas to [email protected].

Figure 2 In this alternative design, voltage across both halves of D1 normallyapproaches 0V and introduces no leakage currents. During an ESD event,both D1 and D2 conduct to protect IC1’s inputs.

_

+

IC1

D1A

D1B

VINR1

VOUT

3V

3V

Figure 1 In a conventional ESD-suppression circuit, diodes clamp an amplifi-er’s input voltage to its power-supply rails but introduce unwanted leakagecurrents.

power-supply rail. Capacitor C1 acts asan intermediate “charge reservoir” thatslows the ESD spike’s rate of rise andprotects IC1’s output stage from latch-ing until diode D2A or D2B begins diver-sion of the ESD transient into the pos-itive or the negative supply rail. Ineffect, C1 compensates for D1’s parasiticcapacitance. Resistor R3 allows IC1 todrive the capacitive load that C1 pres-ents without going into oscillation.

During an ESD event, both D1 andD2 can conduct, but the voltage at VINexceeds the power-supply-rail voltageby only two forward-biased diode volt-age drops. Resistors R1 and R2 limit theamplifier input’s currents below themanufacturer’s recommended 5-mAmaximum rating.

When packaging the circuit, pay spe-cial attention to the pc board’s layout.Imperfections in the board’s dielectric

properties can provide parasitic-leak-age-current paths. Adding coppertraces on both sides of the board to form

guard rings around the circuit’s high-impedance nodes diverts leakage cur-rents (Figure 3).EDN

An older computer system fedRGB video and composite-syn-

chronization signals through four 75coaxial cables to an RGB color monitor

150 feet away. To upgrade it, the replace-ment VGA video cards could directlydrive the 75 loads that the VGA mon-itors’ internal terminations presented.

However, the VGA standard uses sepa-rate horizontal and vertical positive-going synchronization signals. Adding anextra coaxial cable to the original cablesto carry the separate synchronization sig-nals presented a difficult and expensiveproposition. An obvious solution wouldbe to combine the separate synchro-nization signals into a composite format.

designideas

192 EDN | SEPTEMBER 28, 2006

Werner Schwiering, Joystick Scoring Ltd, Whitby, ON, Canada

Composite-VGA encoder/decodereases display upgrade

Figure 3 For best performance, place copper traces around the amplifier’shigh-impedance points to intercept leakage currents.

Figure 1 The synchronization-pulse combiner and recovery circuits comprise readily available and inexpensive components.

Q3

2N3904

R74.7k

Q4

2N3904

R81k

12V

VERTICAL-SYNCHRONIZATION

OUTPUT

Q1

2N3904

R54.7k

C20.01 F

C10.01 F

R44.7k

R31k

R22.2k

R175

J2J1

Q2

2N3904

R61k

12V

HORIZONTAL-SYNCHRONIZATION

OUTPUT

0.1 F

SYNCIN

SYNCOUT

D11N4148

D21N4148

D41N4148

D31N4148VERTICAL-

SYNCHRONIZATIONINPUT

HORIZONTAL-SYNCHRONIZATION

INPUT COAXIALCABLE

SIMPLE VGA-COMPOSITESYNCHRONOUS ENCODER/DECODER

Several safety-critical solenoidsin a laser-measurement system

on an automotive-assembly linerequired protection from internaloverheating during normal operation.After a 60-sec activation, the solenoidsrequired 180 sec to cool before theirnext activation. One apparentlystraightforward protection circuitwould comprise a timer based on a

microcontroller, some support compo-nents, and a short program written inC. However, the project wouldrequire evaluation and selection of asuitable microcontroller, purchase orrental of a device programmer, and con-siderable time in programming themicrocontroller and evaluating itsoperational hazards.

As an alternative, I recalled the

words of my tutor: “Decrease the num-ber of dangerous components todecrease the risk of danger.” A simpleanalog circuit would be safer, smaller,and easier to maintain. The circuit inFigure 1 uses a traditional analogmethod of measuring time: the chargeand discharge behavior of a resistance-capacitance circuit.

Figure 2 highlights the circuit’s tim-ing components. Capacitor C2, a tan-talum electrolytic with 10% toler-ance, diode D1, and resistors R2 and R5constitute a double-RC (resistor-

The combiner circuit in Figure 1 offerssimplicity, low cost, and rapid assemblyfrom readily available spare parts.

In operation, two 1N4148 diodes, D1and D2, attenuate the VGA signal’s 5Vlogic-level vertical-synchronizationpulses by 1.4V, and diodes D3 and D4form a diode-logical-OR gate to com-bine the vertical- and horizontal-syn-chronization pulses. The resultant out-put signal comprises an approximate-ly 4.3V horizontal-synchronizationsignal superimposed on a 2.9V vertical-synchronization signal.

At the receiving end, a capacitively

coupled highpass filter extracts the hor-izontal-synchronization signal, and asimple RC (resistor-capacitor) lowpasscircuit removes horizontal-synchro-nization pulses from the directly cou-pled vertical-synchronization signal.Transistors Q1 and Q2 amplify therecovered horizontal-synchronizationpulses, and transistors Q3 and Q4 ampli-fy the vertical-synchronization pulses.The circuit’s resulting outputs consist of clean synchronization pulses thatclosely approximate those of the orig-inal and provide extremely stable syn-chronization pulses for a VGA moni-

tor operating at 640480-pixel reso-lution (Figure 2).EDN

designideas

194 EDN | SEPTEMBER 28, 2006

Figure 2 Applying the diode-gatedcomposite-synchronization wave-form to a 75 load results in cleansynchronization pulses.

Solenoid-protection circuit limits duty cyclePanagiotis Kosioris, Inos Automation Software, Stuttgart, Germany

Figure 1 An externally triggered solenoid driver features an analog duty-cycle limiter.

IC2TC4432

OUT

OUT

VDDVDD

GNDGND

IN

LOCKDIS

2

3

1

845

24V

NC

6

7

R71k

R31k

R410k

R15.5k

R22.2M

R610k

R52.2M

D21N4148

D11N4148

C1100 nF

C268 F

IC1BAD822

Q1

IRL3705N

_

+5

8

7

64

IC1AAD822_

+3

1

2TRIGGER IN

12V

+

TO SOLENOIDS

capacitor) circuit. During solenoidactivation, R2 provides a charging pathfor C2, and diode D1 prevents C2 fromdischarging through the solenoids.When the solenoids are off, the dis-charge path comprises R2 plus R5, whichprovides a longer time constant. The dif-ference between the two time constantsdetermines the solenoids’ activation andrecovery periods. A Schmitt trigger de-signed around one-half of IC1, an Ana-log Devices (www.analog.com) AD822dual operational amplifier, senses thevoltage across C2 and defines the sole-noids’ cutoff- and turn-on-timing in-tervals. An intermediate buffer stage,IC1B, drives a Microchip (www.micro-chip.com) TC4432 MOSFET driver,

which in turn controls the gate of Q1,an N-channel power MOSFET thatdrives the solenoids from 24V.

When Q1 switches on, the voltagelevel across C2 increases, and, after 60sec, the output of the Schmitt triggerfalls from 12 to 0V. The buffer stagedrives the cathode of diode D2 to 0V.The voltage at D2’s anode reaches 0.7Vand is insufficient to trigger MOSFET-driver IC2. Q1 now switches off, re-moving supply voltage from the sole-noids and reverse-biasing diode D1.Capacitor C2 starts to dischargethrough R2 and R5, and the input volt-age you apply to the Schmitt triggerfalls at a slower rate than during thecharging interval. After 180 sec, the

Schmitt trigger’s output rises to 12V,and the circuit awaits arrival of anoth-er external trigger pulse through resis-tor R3.EDN

designideas

196 EDN | SEPTEMBER 28, 2006

D1 R2

R52.2M

C268 F

1N4148

CHARGING

DISCHARGING

2.2M

TO IC1A,PIN 2

FROMSOLENOIDS

Figure 2 A resistance-capacitancecircuit determines on- and off-timeintervals.

This Design Idea describes anenhancement to a previous one

(Reference 1). The circuit in Figure 1uses a normally open SPST pushbuttonswitch, S1, instead of the SPDT switchthat the original design required. Youcan use a membrane switch to signifi-cantly simplify the industrial design ofthe device and enhance its ergonomics.In addition, this circuit slightly reducesthe current drain in active mode byeliminating current flow through theunactuated switch.

In standby mode, MOSFET Q1remains off and consumes less than 1A of leakage current from the battery.Pressing switch S1 turns on Q1 bypulling its gate to ground through diodeD1. Voltage regulator IC1 turns on andsupplies power to microcontroller IC2.The microcontroller boots up andasserts its P1.1 output high, turning ontransistor Q2 and latching on the sys-tem’s power to allow release of S1.Meanwhile, resistor R3 pulls the micro-controller’s input, P1.2, to VCC. Press-ing the switch a second time pulls themicrocontroller’s P1.2 input low

through diode D2 and signals the but-ton-pressed event to the firmware.After completing its program, themicrocontroller asserts its output P1.1low to turn off Q2 and, consequently,Q1, removing power from the systemuntil the user presses S1 and restarts theprocess.

When selecting components, en-sure that Q1’s gate-source breakdownvoltage exceeds the highest possibleinput voltage; otherwise, use a zenerdiode to limit Q1’s applied gate-sourcevoltage. You can omit Q1 if voltageregulator IC1 includes an on/off-con-trol pin. To replace Q1 with a differ-ent power-switching device, such asan NPN bipolar transistor or a relay,specify Q2 to provide the control cur-rent that the switching device re-quires. To further reduce the circuit’scomponent count, replace diodes D1

SPST pushbutton switch combines power-control, user-input functions

Eugene Kaplounovski, Vancouver, BC, Canada

Figure 1 One switch can provide power control and user inputs to a micro-controller-based system.

P1.2

P1.1

GND

VCC

IC2

Q1P-MOSFET

VCC

Q22N3904

D11N914

S1SPST

D21N914

IC1REGULATOR

C110 F

C210 F

R347k

R447k

R210k

R1100k

C310 nF

S

G

D

+ GND

IN OUT+

POWER HOLD

SWITCH

+BT1

BATTERY

designideas

198 EDN | SEPTEMBER 28, 2006

and D2 with a suitable common-cath-ode dual-diode array, such as theBAV70. Omit resistor R3 if IC2 in-cludes built-in pullup resistors, as do

many modern microcontrollers.EDN

R E F E R E N C EHageman, Steve, “Single switch

serves dual duty in small, microcon-troller-based system,” EDN, March30, 2006, pg 96, www.edn.com/article/CA6317068.

Mechanical push-pushbuttonswitches (also known as alter-

nate-action or push-on/push-off switch-es) can be bulky and expensive. As analternative, an electronic version uses acheaper, NO (normally open), momen-tary-on switch (Figure 1). A superviso-ry microprocessor, IC1, serves as a com-bination switch debouncer and intelli-gent controller. Applying power holdsIC1’s LBO output (Pin 4) low, which inturn resets flip-flop IC2’s output to alogic-low state (off) (Figure 2). Pressingthe NO momentary-contact switch, S1,evokes a pulse from the RESET output(IC1, Pin 5), which triggers IC2’s CKinput (Pin 1) and toggles IC2’s output toa logic-high state (on). Pressing theswitch a second time triggers anotherRESET pulse that toggles flip-flop IC2’soutput to a logic-low state (off).

You can add an optional watchdogtimer, IC3, to reset IC2’s output to thelogic-low state after a user-selectableinterval as long as 60 sec. You can selectshorter reset times using IC3’s pro-gramming pins: SET0, SET1, andSET2. The entire circuit costs about $2(1000) and occupies a pc-board areathat’s no larger than its mechanicalcounterpart.EDN

Electronic circuit replaces mechanical push-push switchDonald Schelle, Maxim IntegratedProducts Inc, Sunnyvale, CA

VDD VCC

VCC

VCC

IC1MAX6847

IC3MAX6369

IC2NC7SV74

HTHIN

LTHIN

GND

LBO

RESET

2

8

3 6

5

4

17

2

MR

74

4

81

5

6

7

1

5

3

2

3

6

8

VCC3.3V

VCC3.3V

VCC3.3V

VCC3.3V

C10.1 F

C40.1 F

S1

C20.1 F

R1470kR2

470k

VCC3.3V

VCC3.3V

C30.1 F

CK

D

PR

CLR Q

GND

Q

OUTPUT

NC SET2

SET1

SET0

WDIGND

WDO

OPTIONAL

Figure 1 This simple electronic circuit uses a momentary-contact pushbuttonswitch, S1, to replace a more expensive mechanical push-on/push-off switch.

GND

GND

S1

GND

OUTPUT

VCC

OUTPUT IS ZEROAT START-UP.

TIME

SWITCHBOUNCE

SWITCHBOUNCE

SWITCHBOUNCE

SWITCHBOUNCE

225mSEC

225mSEC

225mSEC

60SEC

225 mSEC

VALID ONLY IF OPTION IC3 IS ATTACHED.

Figure 2 Repeatedly pressing the circuit’s momentary-contact switch togglesthe circuit’s output on and off. After a preselected interval, an optional watch-dog timer resets the output to the logic-low state.

MORE AT EDN.COM

For more Design Ideas, visitwww.edn.com/designideas.

For our best entries, go towww.edn.com/bestofdesignideas.

+

+

1

Most oscillator circuits include a nonlinear amplitude control

that sustains oscillations at a desired amplitude with minimum output dis-tortion. One approach uses the out-put sinusoid’s amplitude to control a circuit element’s resistance, such as that of a JFET operating in its triode-characteristics region. Another con-trol method uses a limiter circuit that

allows oscillations to grow until their amplitude reaches the limiter’s thresh-old level. When the limiter operates, the output’s amplitude remains con-stant. To minimize nonlinear distor-tion and output clipping, the limiter should exhibit a “soft” characteristic.

Based on a waveform shaper that imposes a soft limitation or saturation characteristic, the circuit in Figure

1 comprises a simple RC (resistor-capacitor)-ladder phase-shift oscilla-tor and an amplitude-control limiter circuit. R1, R2, and R3 have values of 10 kV each, and C1, C2, and C3 have values of 1 nF each. The following equation defines output voltage VOUT’s frequency, fO.

The inverting-amplifier block in Figure 1 comprises transistors Q1 and Q2, a differential pair that presents a nonlinear-transfer characteristic, plus an IVC (current-to-voltage converter) based on operational amplifier IC1. For oscillation to occur, the inverting amplifier’s gain magnitude must exceed 29. Selection of appropriate values of bias current, IEE; the transistor pair’s emitter-degeneration resistances, RE1 and RE2; and RE3 produces the ampli-fier’s nonlinear-transfer characteristic, VOUT versus VIN (Figure 2).

A small input voltage produces a nearly linear-amplifier-transfer charac-teristic. However, large values of input voltage drive Q1 and Q2 into their nonlinear region, reducing the ampli-fier’s gain and introducing a gradual bend in the transfer characteristic. A current mirror comprising Q3 and Q4 converts the shaping circuit’s output

october 12, 2006 | EDN 99

readerS SOLVe deSIGN PrOBLeMS

EditEd By Brad thompson and Fran GranvillE

designideasSoft limiter for oscillator circuits uses emitter-degenerated differential pair

Figure 1 A phase-shift RC-oscillator circuit uses an emitter-coupled amplitude limiter.

DIs Inside100 Feedback circuit enhances phototransistor’s linear operation

104 Three-phase sinusoidal-wave-form generator uses PLD

EWhat are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to [email protected].

herminio martínez and Encarna Garcia, technical University of Catalonia, Barcelona, spain

STEVE edn060928DI3902 figure1

_

+

AMPLIFIERBLOCK

VCC12V

VCC12V

VEE12V

VEE12V

VOUT

IEE

RC233k

RE3100k

RG10k

RC133k

RE1100

RE2100

Q32N3906

Q12N2222

Q22N2222

VOUT

VIN

Q42N3906

R110k

FREQUENCY-DETERMINATION NETWORK

R210k

C11 nF

IC1TL081

C21 nF

R310k

C31 nF

Equation for DI

fRC kO

3902

62

62 10 1

39= =× × ×

≈π π nF

kHz.Ω

100 EDN | october 12, 2006

A designer who uses a photo-transistor to convert a modu-

lated optical signal to an electrical signal frequently encounters problems when high-intensity background light saturates the phototransistor. When its base terminal floats, a phototran-sistor’s collector-to-emitter voltage depends only on the photocurrent generated by the superposition of the signal and background light. The phototransistor’s gain and its active-region range depend on R1’s resis-tance. For higher values of R1, the circuit’s gain increases, but the pho-totransistor saturates more quickly. In Figure 1, without background illu-mination, the transistor operates in its linear region at bias point f2, and Q1’s collector voltage varies linearly

designideas

to a single-ended current, which operational amplifier IC1 converts to an output voltage. In the prototype cir-cuit, calibration trimmer RE3 has a value of approximately 33 kV. Figure 3 shows the oscillator’s output voltage for the component values in Figure 1, and Figure 4 shows the sinusoidal output’s spectral purity.

The nonlinear amplifier’s wave-shaping action occurs independently of frequency, and this circuit offers conve-nience for use with variable-frequency oscillators. Note that IC1’s gain-bandwidth product limits the circuit’s per-formance. To use the limiter portion of the circuit with a noninverting amplifier, such as a Wien-bridge oscillator, apply the signal input voltage to Q2’s base, and ground Q1’s base.EDN

Feedback circuit enhances phototransistor’s linear operation JC Ferrer and a Garrigós, University miguel hernández, Elche, spain

Figure 2 The transfer-characteristic output voltage versus input voltage for the nonlinear amplifier shows a gradual onset of limiting at approximately 100-mV input.

Figure 4 The oscillator’s output spectrum shows only a slight amount of third-harmonic output.

Figure 3 For the component values in Figure 1, the oscilla-tor’s output voltage reaches full amplitude in approximately 400 msec, or 15 cycles after start-up.

Figure 1 Varying levels of ambient-light flux affect the bias point of a basic phototransistor circuit. Higher levels force the bias point closer to saturation and compress the desired signal, VOUT.

AMBIENT-LIGHTFLUX

()

CURRENT3

2

1

VCE

IC

IC

IC

VHI VCE

LOAD LINE (1/R1)

BIAS POINT

NC

MODULATED LIGHT PRODUCES

AC-OUTPUT SIGNAL, VOUT

VCE(SAT)

VHIGH

VOUT

Q1

R1

EDN061012DI3851FIG1 MIKE

MAX

102 EDN | october 12, 2006

designideas

around VCE. Its output, VOUT, faithfully repro-duces ampltude fluctua-tions in the modulated optical signal. Applying extraneous steady-state background illumina-tion shifts the circuit’s operating point to bias point f 3, and the output voltage compresses and distorts.

Unlike photodiodes and photovoltaic cells that have only two leads, a phototransistor’s base connection allows a feedback circuit to control the device’s bias point. Diverting current from the base terminal reduces collector cur-rent. In Figure 2, phototransistor Q1 detects an optical signal plus back-ground light that illuminates its base region. A lowpass active filter samples the collector voltage generated by the background light, and a Howland current source alters the circuit’s bias point by draining current from the phototransistor’s reverse-biased col-lector-base junction.

In general, extraneous background illumination fluctuates more slowly than the desired signal. For simplicity, this design uses a first-order lowpass filter, C1 and R2, with a cutoff fre-

quency below the signal frequency to sample Q1’s collector voltage. Apply-ing a reference voltage—VCC, in this example—to R3 sets the filter circuit’s dc operating point midway between the phototransistor’s cutoff and satura-tion voltages. The lowpass filter’s out-put drives a Howland current source to produce a current proportional to the filter’s output. As background illumi-nation increases, Q1’s collector voltage decreases. The current source’s output subtracts from Q1’s base current, which in turn raises Q1’s collector voltage to avoid saturation.

The ratio of R4 to R3 establishes the active lowpass filter’s gain according to the equation AV511(R4/R3), and

R5 sets the current source’s transcon-ductance: GM51/R5. Altering these resistors affects the amount of current drained from the phototransistor’s base and the circuit’s operating point. The phototransistor has much lower capacitance than the filter, ensuring that the circuit in Figure 2 cannot oscillate. However, replacing the first-order lowpass filter with a second-order lowpass filter requires careful selection of the capacitors’ values to avoid oscillation.

Illuminating the phototransistor with a 100W incandescent light bulb provides high-intensity-light back-ground lighting plus a rapidly chang-ing signal due to the applied ac-line

Figure 2 A feedback circuit consisting of a single-pole lowpass active filter and a Howland source diverts current from the phototransistor’s base to avoid saturation at excessive back-ground-light levels.

edn061012di38512 DIANE

+

_IC2

TL082

VCC

R710k

R51k

R810k

R61k

VDD

+

_IC1

TL082

VCC

VCCVCC

VOUTPUT

R347k

R2470k

R11k

Q1BPX43

C1500 F

R418k

VDD

+

Figure 4 A 100W light bulb at a 20-cm distance illuminates the collector-emitter voltage of a phototransistor with a feed-back circuit (a) and with no feedback (b). Saturation of the circuit with no feedback prevents signal detection.

Figure 3 A 100W light bulb at a 40-cm distance illumi-nates a collector-emitter voltage of a phototransistor with a feedback circuit (a) and with no feedback (b). Both bias points remain in the linear region.

voltage. Figure 3 shows Q1’s collec-tor-to-emitter voltage with the light bulb 40 cm from the phototransistor with the feedback circuit active (Fig-ure 3a) and for the circuit with the phototransistor’s base floating (Figure 3b). The responses appear similar be-cause the phototransistor doesn’t satu-rate at the applied light intensity.

Repositioning the light bulb at 20 cm from the phototransistor increases the background-light level and drives the phototransistor closer to satura-tion. When you apply feedback, the phototransistor delivers a higher am-plitude signal, although its bias point remains almost unchanged (Figure 4a). The average dc-voltage level at

Q1’s collector remains almost the same as at the lower light level (Figure 3a). However, with no feedback applied, the phototransistor’s bias point moves close to saturation, and the ac-mod-ulated light variations are barely de-tectable (Figure 4b).EDN

Using the circuit in this De-sign Idea, you can develop and

implement a lightweight, noiseless, inexpensive, three-phase, 60-Hz si-nusoidal-waveform voltage generator.

Although targeting use as a circuit for testing power controllers, it can serve other applications that require three sine waves with a 1208 relative phase difference. A 22V10 PLD (programma-

ble-logic device) at IC1 generates three three-phase, 60-Hz, square-wave voltages. Internal register IC1 and Q0, Q1, and Q2 bits set the

104 EDN | october 12, 2006

designideas

Three-phase sinusoidal-waveform generator uses PLDEduardo perez-lobato, University of antofagasta, antofagasta, Chile

edn061012di39371 DIANE

IC1 Q5

Q4

Q3

Q2

Q1

Q0

CLK

GND

VCC1

2

3

4

5

6

7

8

9

10

11

12

23

24

22

21

20

19

18

17

16

15

14

13

22V10

748 Hz

5V

Q5

Q4

Q3

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Figure 1 An external 748-Hz clock source drives this PLD-based, three-phase sine-wave generator.

edn061012di39373 DIANE

CLK

V

OPOUT

OPIN

IN

V+

GND

OUT

IC2MAX294

2

3

4

1 8

7

6

5

Q35V

1.5k 1.5k

100 nF A PHASE

CLK

V

OPOUT

OPIN

IN

V+

GND

OUT

IC3MAX294

2

3

4

1 8

7

6

5

Q45V

1.5k 1.5k

100 nF B PHASE

CLK

V

OPOUT

OPIN

IN

V+

GND

OUT

IC4MAX294

2

3

4

1 8

7

6

5

Q55V

1.5k 1.5k

100 nF C PHASE6 kHz

Figure 2 Switched-capacitor filters remove all but the sinusoidal fundamental signal from the PLD’s three-phase square-wave outputs.

0 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0

0 1 1 1 1 1 10 0 0 0 0 0

0 1 1 10 0 0

edn061012di3937fig2 mike

0 0 0 01 1 1

0 0 1 01 10 1 1 10 0 0

A PHASE

B PHASE

C PHASE

CLK

Q0

Q1

Q2

Q3

Q4

Q5

0 60 120 180 240 300 360 420 480 540PHASE ()

Figure 3 The timing diagram shows the relationship between the clock and the three-phase outputs.

designideas

Q3 bit to lead the Q4 bit by 1208 and set the Q5 bit to lag behind the Q3 bit by 2408 (Figure 1). Setting IC1’s clock frequency to 748 Hz produces 60-Hz outputs at Q3, Q4, and Q5.

IC1’s three square-wave output volt-ages—Q3, Q4, and Q5—drive IC2, IC3, and IC4, three Maxim (www.maxim-ic.com) MAX294 eighth-order, low-pass, switched-capacitor filters to pro-duce three 2V sinusoidal waveforms (Figure 2). When you connect IC5, a common 555 timer as an astable oscil-lator, it produces a 6-kHz, TTL-level source that clocks all three filters at 100 times the desired 60-Hz output fre-quency. A 100-nF dc-blocking capaci-

tor at each filter’s output ensures that the three-phase outputs swing from 12 to 22V with respect to ground. Note that each filter inverts its output and introduces a 1808 phase shift with respect to its input square wave.

Figure 3 depicts the phase relation-ships among IC1’s outputs and yields Boolean equations (Table 1). The equations translate into set/reset sig-nals that produce 64 logic states when you apply them to a 6-bit sequencer block in IC1. Out-puts Q5, Q4, and Q3 represent the three most-significant bits, and Q2, Q1, and Q0

represent the three least-significant bits. After translation, an emulated Basic program (Listing 1), which you can download from www.edn.com/061012di1, produces fuse-pro-gramming code for IC1’s sequencer and logic states. Although only 16 logic states define the sequencer’s functions, its remaining 48 states also require definition to avoid anomalous operation.EDN

Figure 4 A garden-variety 555 timer IC provides a 6-kHz clock for the switched-capacitor filters.

edn061012di39373 DIANE

IC5555

2

3

4

18

7

6

55V

6 kHz

NC

5V

12k

6.2k

10 nF

edn061012di39374

TABLE 1 BooLEAn EquATionssEt_Q0=Q0 rEsEt_Q0=Q0

sEt_Q1=Q13Q0 rEsEt_Q1=Q23Q13Q0+Q23Q13Q0

sEt_Q2=Q23Q13Q0 rEsEt_Q2=Q23Q13Q0

sEt_Q3=Q33Q23Q13Q0 rEsEt_Q3=Q33Q23Q13Q0

sEt_Q4=Q43Q23Q13Q0 rEsEt_Q4=Q43Q23Q13Q0

sEt_Q5=Q53Q23Q13Q0 rEsEt_Q5=Q53Q23Q13Q0

106 EDN | october 12, 2006

october 26, 2006 | EDN 105

readerS SOLVe deSIGN PrOBLeMS

EditEd By Brad thOMpsOn and Fran GranviLLE

designideasDIs Inside110 Single microcontroller pin senses ambient light, controls illumination

112 Hartley oscillator requires no coupled inductors

EWhat are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to [email protected].

Connecting an LVDT (lin-ear-variable-differential trans-

former) to a microcontroller can prove challenging because an LVDT requires ac-input excitation and measurement of ac outputs to determine its mov-able core’s position (Reference 1). Most microcontrollers lack dedicated ac-signal-generation and -processing capabilities and thus require external circuitry to generate harmonic-free, amplitude- and frequency-stable sine-wave signals. Conversion of an LVDT’s

output signals’ amplitude and phase into a form compatible with a micro-controller’s internal ADC usually requires additional external circuitry.

In contrast with conventional micro-controllers, Cypress Semiconduc-tor Corp’s (www.cypress.com) PSoC microcontrollers include user-configu-rable logic and analog blocks that sim-plify generation and measurement of ac signals. PSoC devices have the unusual feature of being able to generate analog signals without demanding continuous

CPU attention. The PSoC’s flexible analog and digital blocks can drive an LVDT and measure its outputs without requiring any external circuitry. Figure 1 shows the complete circuit of the LVDT interface, and Figure 2 shows

PSoC microcontroller and LVDT measure position

Figure 1 A single PSoC can excite an LVDT, digitize the position of its core, and present the data to an external LCD.

STEVE EDN061026DI3924 FIGURE1

ANALOG-REFERENCE GROUND

REF_CLOCK_TPTRANS TEK#0218-00004-IN. LVDT

YELLOW WHITEPRIMARY

CORE

SECONDARY B SECONDARY A

BLACK ORANGE

BLUE RED

SINE-WAVE DRIVE DC ANALOG OUTPUT

LCD CONTRAST ADJUST

MEASUREMENT SIGNAL

C31 F

C20.1 F

C10.01 F

R110k J1

VCC5V

J2

VCC

POWERCONNECTOR

123

IC1CY8C27443-

24PXI

XRES SMP

P1(1)/XI/SCLK

P1(0)/XO/DAT

P2(6)/VREF

P2(4)/AGND

P1(7)P1(6)P1(5)P1(4)P1(3)P1(2)

P0(7)P0(6)P0(5)P0(4)P0(3)P0(2)P0(1)P0(0)

P2(7)P2(5)P2(3)P2(2)P2(0)P2(1)

19

13

15VDD

VCC 28

101811171216

VSS14

1

9

272

263

254

24

NOTE: IC1 PINS WITH INDICATE NO CONNECTION.

567

21208

123456789

1011121314

23

22

LCD-MODULECONNECTOR

LUMEXLCM-S01602DSR

+

sigurd peterson, sig3 Consulting, aloha, Or

106 EDN | october 26, 2006

designideas

the PSoC microcontroller’s internal circuit blocks.

The PSoC uses pairs of user-con-figurable switched-capacitor blocks to implement both bandpass and lowpass filters. You can create a high-quality sine wave by generating a square wave and applying it to a PSoC switched-capacitor filter through a modulator built into the first switched-capaci-tor block. Passing the square wave through a narrow bandpass filter centered on the square wave’s funda-mental frequency removes most of the harmonics.

To obtain the highest fidelity sine waveform from a PSoC switched-capacitor bandpass filter, use the highest possible oversampling rate—a factor of approximately 33—or 33 steps per sine-wave cycle. The resul-tant sine wave is smooth enough to drive an LVDT, which attenuates any residual higher order harmonics. Scaling the PSoC’s internal voltage reference with a programmable-gain amplifier provides coarse control over the square wave’s amplitude before it undergoes filtering. To compensate for the waveform’s dc-offset voltage, an amplifier buffers the 2.6V internal analog-ground reference and drives an output pin that serves as the LVDT’s analog-ground return.

The LVDT’s output consists of a variable-amplitude sine-wave volt-age whose phase angle with respect to the sine-wave excitation voltage undergoes a significant and variable shift that sometimes exceeds 1808. A signal from the LVDT drives one of the PSoC’s programmable-gain amplifiers, whose output feeds a switched-capaci-tor lowpass filter followed by a modu-lator for synchronous rectification. The rectified signal drives an output pin and one of the PSoC’s switched-capacitor ADCs.

Applying the LVDT’s output to a synchronous rectifier followed by a lowpass filter produces a dc voltage that can feed an ADC or directly drive an analog feedback-control system. In a PSoC microcontroller, a lowpass switched-capacitor filter connected to an ADC requires that the same sample clock drive both circuits, resulting in a conversion rate for the PSoC’s 11-bit delta-sigma ADC that’s approximately one-half of the lowpass filter’s corner frequency. Synchronous rectification produces a ripple frequency twice that of the excitation frequency and thus is easier to remove with a lowpass filter. Relocating the lowpass filter’s corner frequency to one-third of the excita-tion frequency allows measurements of the LVDT’s output to 11-bit resolution

with a standard deviation of 1 LSB (least significant bit) or less.

Dividing the PSoC’s 24-MHz inter-nal system clock with logic blocks configured as counter chains gener-ates all of the digital clock signals the switched-capacitor analog-circuit blocks require. After power application or a reset, the PSoC’s CPU configures all the configured analog and digi-tal blocks and starts their operation. From then on, the hardware excites the LVDT and measures its output at 500 samples/sec without further inter-vention by the CPU. With the PSoC’s CPU running at 12 MHz, processing the ADC’s housekeeping activities and interrupts consumes less than 3% of the CPU’s resources.

Plenty of the PSoC’s resources remain available for calculating the LVDT’s position and for displaying the results in text format on an LCD module. Four analog blocks, five logic blocks, and many I/O pins remain available to support a more demand-ing application. Figure 3 (next page) shows configurable blocks that are available for adding features.EDN

edn061026di39242 DIANE

VOLTAGEREFERENCE

SWITCHED-CAPACITORBANDPASS

FILTER

SINE WAVEOUTPUT

PIN

OUTPUTPIN

CARRIER-FREQUENCYSQUARE-WAVE

GENERATOR

SWITCHED-CAPACITORLOWPASS

FILTER SWITCHED-CAPACITOR

ADC

MODULATOR

MODULATOR

INPUTPIN

PROGRAMMABLE-GAIN AMPLIFIER

SAMPLE-CLOCKGENERATOR

SAMPLE-CLOCKGENERATOR

24-MHzSYSTEMCLOCK

DC

Figure 2 The LVDT-interface circuit requires many analog functions.

1 “Linear variable differential trans-former,” Wikipedia, http://en.wikipedia.org/wiki/Lvdt.

R e fe R e n ce

108 EDN | october 26, 2006

designideas

Figure 3 You can use the unlabeled circuit blocks for expansion.

110 EDN | october 26, 2006

designideas

As in a previous Design Idea (Reference 1), this design uses

an LED as a transducer to measure the ambient-light level and to provide illu-mination. This Design Idea uses the same principle as its predecessor but consists of only one LED, two resistors, one IC, and one 0.1-mF bypass capaci-tor. This circuit for providing ambi-ent-light feedback requires no addi-tional components. Despite requiring only a few components, the circuit in Figure 1 offers considerable flexibility because the microprocessor’s software controls the LED’s brightness and its relationship to ambient-light levels. For night-light applications, one mode turns on the LED when ambient light decreases. Conversely, for power-sav-ing regulation of a portable device’s LCD backlight, a second mode turns on the LED when the ambient-light level increases.

You can download Listing 1, sample code for this Design Idea, at www.edn.com/061026di1. The code provides 64 levels of PWM (pulse-width-modu-lated) intensity control over the LED’s brightness in either mode. In opera-tion, one of the microprocessor’s mul-tifunction pins drives the LED with a

PWM waveform for several hundred milliseconds. After the waveform’s final cycle, the software switches the microprocessor’s pin to input mode and connects the LED to the micro-processor’s internal 16-bit sigma-delta ADC. Ambient light illuminates the LED, producing voltage, which the ADC measures, and the microproces-sor computes the PWM waveform’s parameters for the next series of illu-mination cycles. The cycle rate’s high repetition frequency eliminates any discernible flickering of the LED.

In the listing, when the software and ambient-light level specify that the LED should turn off for an extended interval, the CPU goes into a low-power state for 250 msec. During its sleep mode and for a few hundred microseconds while performing ADC conversions, the circuit draws only about 20 mA and thus suits itself well to battery-powered-system applica-tions.

At start-up, the microprocessor stores an initial voltage level, which the LED produces, and uses this value to scale the PWM levels. Shading the LED or moving the circuit into a darker area immediately increases the

LED’s brightness, which the listing’s 64 PWM levels control in small steps. The MSP430F2013’s ADC presents input impedance of approximately 200 kV. When driving this impedance, an LED occupying a small, 0805, sur-face-mount footprint generates only a few 10s of millivolts. However, the MSP430F2013’s 16-bit ADC resolves the LED’s voltage with sufficient reso-lution to ensure good performance under normal room-lighting levels.

In addition, the MSP430F2013 includes a four-level PGA (program-mable-gain amplifier), offering gains of one, four, eight, and 16 to further amplify the LED’s minuscule output voltage. The circuit also exploits the microprocessor’s onboard low-fre-quency clock oscillator, which allows low-powered operation without an external crystal. The resultant circuit includes only six components, includ-ing a battery. Note: The code can execute on Texas Instruments’ (www.ti.com) eZ430 demonstration board without hardware modifications because the board includes an LED connected to port P1.0.EDN

11

Single microcontroller pin senses ambient light, controls illuminationLoren passmore, Berkeley, Ca

edn061026di39391 DIANE

IC1MSP430F2013

VCC

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

GND

XIN

XOUT

TEST

RST

P1.7

P1.6

1

2

3

5

6

7

4

14

13

12

10

9

8

11

R1330

C1100 nF

R247k

D1GREEN

LED

NOTE: IC1’S PINS WITH INDICATE NO CONNECTION.

VCC

SBWTDIO

P10

Figure 1 An LED, a microprocessor, two resistors, and one capacitor constitute the entire circuit.

1 Myers, Howard, “Stealth-mode LED controls itself,” EDN, May 25, 2006, pg 98, www.edn.com/article/CA6335303.

R e fe R e n ce

112 EDN | october 26, 2006

designideas

Editor’s note: EDN originally ran this Design Idea in its June

22, 2006, issue. However, due to a num-ber of schematic and textual errors, we have decided to run a corrected, up-to-date version here. We apologize for the errors and hope this version clears up any and all confusion.

Examine a traditional Hartley oscil-lator circuit, and you’ll note its trade-mark: a tapped inductor that deter-mines the frequency of oscillation and provides oscillation-sustaining feed-back. Although you can easily calcu-late the total inductance required for a given frequency, finding the coupling coefficient, k, poses technical diffi-culties and may require experimental optimization, also referred to as the “cut-and-try” method. This Design Idea presents an alternative equivalent circuit that allows you to model the circuit before building the prototype.

Figure 1 shows the Hartley oscil-lator’s equivalent tuned circuit and component values for an 18- MHz oscillator. The mutual induct-ance is LM=k=L13L2. For the equiv-alent circuit, the equations are: LA=1LM, LB=L21LA=L2+LM, and LC= L11LA=L1+LM. The rest of the equa-tions for the equivalent circuit are:

and

Unfortunately, a truly equivalent circuit requires a negative inductance, LA. However, for frequencies near the resonant frequency f0, you can replace the negative inductor with a capacitor as (Figure 1c), where CA replaces LA. Note that the equivalent circuit’s derivation neglects parasitic winding resistances and capacitances.

Figure 2 illustrates an oscillator and output buffer using the equivalent circuit. When constructed, the circuit generally performed as expected from an initial Spice simulation. During testing, several components’ values required tweaking, and multiple iterations of Spice analysis ultimately yielded the final design.

The oscillator’s tank circuit consists of LB, LC, C4, and C5, plus the capacitance provided by the voltage divider C6, C7, and C8—approximately 6 pF, including Q1’s and Q2’s input capacitances and some stray capacitance. The total tank capacitance of 66 pF approximates the calculated value of 67 pF. Capacitors that connect to the tuned circuit feature ceramic-dielectric construction with NP0 temperature coefficients.

Inductors LB and LC consist of air-core coils mounted with their axes at right angles to each other to minimize stray coupling. However, vibration

affects their inductances, and, in a final design, both should consist of windings on dielectric cores or on toroidal cores, providing that the toroids’ temperature coefficients of inductance are acceptable for the intended application.

The information in Reference 1 provided basic designs for both inductors, and adjusting the spacing of their turns tuned the oscillator to exactly 18 MHz. For a more rigorous design, you can measure the inductors before installation, but parasitic effects may require some adjustment of the inductors.

The capacitive voltage divider, C6, C7, and C8, applies the proper signal levels to Q1 and Q2. Because the divider’s effective capacitance as “seen” by the tank circuit amounts to only 6 pF, you can replace the remaining 60 pF consisting of C4 and C5 with a variable capacitor if the design calls for a tunable oscillator. In this example, the output stage consisting of Q3 and its associated components would require modification to provide more bandwidth if the oscillator requires a tuning range exceeding 62 MHz.

Capacitor C3 bootstraps Q1’s Gate 2 to its source, which provides additional gain and reduces Q1’s Gate 1 input capacitance below its already-low value of approximately 2.1 pF (Reference 2). An 8.3-mH inductor, L2, of less than 2V dc resistance connects to Q1’s source and presents a relatively high impedance at 18 MHz and provides a dc path from Q1’s source to ground through R3. At 18 MHz, L2 has an impedance that consists of an inductive reactance of about 940V

Hartley oscillator requires no coupled inductorsJim McLucas, Longmont, CO

edn060608di38541 DIANE

C67 pF

L2815 nH

L1168 nH

k=0.250LM=92.5 nH

C67 pF

LB907.5 nH

LB907.5 nH

LA92.5 nHLC

260.5 nHLC

260.5 nH

CA845 pF

C67 pF

(a) (b) (c)

Figure 1 A traditional Hartley oscillator’s resonant circuit consists of a tapped inductor and resonating capacitor (a). Allowing for mutual coupling between windings produces an equivalent circuit containing a negative inductance (b). Replacing the negative inductance with a capacitor yields an easily modeled equivalent circuit (c).

114 EDN | october 26, 2006

designideas

in parallel with a resistance of about 3.5 kV, which results in a very-low-Q choke. Provided that its inductance and reactance approximate L2’s original values, you can substitute a physically smaller inductor for L2. Inductor L1’s properties are less critical, but it should present a low Q of 4 to 6 and a dc resistance of approximately 5V or less. You can use a standard-value choke for L1 if it meets these requirements.

Source follower Q2 drives the output stage, which uses a pi-matching network to transform the 50V output load to 285V at the collector of Q3. Bootstrapping Q2’s Gate 2 by one-half of the stage’s output voltage increases the source follower’s gain and dynamic range and reduces its input capacitance.

You can use potentiometer R15 to adjust the circuit’s output level from about 0.9V p-p to approximately 1.5V p-p across a 50V load. At a constant room temperature of about 238C, the frequency remains stable, and the circuitry that controls output level remains stable even with no load on the output. For a fixed-frequency

application, the output circuit’s loaded Q of 4 provides adequate bandwidth to eliminate retuning of the output circuit for small changes in frequency.

To set the output level to a safe maximum, connect a 50V load to the output, and then adjust the output to 1.5V p-p. The drain-to-source voltage applied to Q1 will remain at a safe level for all loads from 50V to no load, even though the output-voltage level increases as the load resistance increases. To avoid exceeding Q1’s specified maximum 12V drain-to-source-voltage rating, do not exceed an output-voltage setting of 1.5V into a 50V load. Note that zener diode D1 reduces Q1’s drain voltage to provide an additional safety margin.

In a previous Design Idea, an operational amplifier and a diode-rectifier circuit set the oscillator’s gain through a control voltage applied to Q1’s Gate 2 (Reference 3). In this design, a simple passive circuit serves the same purpose. A portion of the signal at Q3’s collector drives a voltage doubler consisting of D2, D3, C20, and C21. Part of the negative

voltage developed by the voltage doubler drives the junction of R18 and C19, the control-voltage node, which also receives a positive voltage from variable resistor R15 through R17, and the resultant voltage sets the output signal level. At start-up, only a positive voltage is present at Q1’s Gate 2, and Q1’s maximum gain easily starts the oscillator. When the output reaches a steady state, the control voltage reduces and maintains oscillation at the signal level determined by the output level control.EDN

edn060608di38542 DIANE

9.5V2% C1

0.01 F

C20.01 F

C3560 pF

C100.01 F

D11N4370A

Q1BF998 Q2

BF998

G2

G2

G1

G1

L18.3 H

L28.3 H

R163.01k

R1773.2k

R1843.2k

R339

R2100k

R110k

R155k

C184.7 F

C190.22 F

C90.01 F

C20220 pF

C718 pF

C610 pF

C839 pF

CA845 pF

LB0.9075

H

LC0.2605

H

C21220 pF

D3SD101C

D2SD101C

OUTPUT-LEVEL

ADJUSTMENT

D

D

S

S

+

CONTROL VOLTAGE

LOADR1950

OUTPUT

C16240 pF

C150.01 FC13

0.01 F

C120.01 F

C17200 pF

C14560 pF

C11220 pF

C427 pF

C533 pF

L3620 nH

R14220

R1113k

R822

R1310k

R9220

R547k

R44.3k

R10220

R727k

R610k

R1222

Q32N3904C

A=680 pF+150 pF+15 pF=845 pF.

TANK

NOTES:L1, L2: SIX TURNS AWG #22 WIRE ON A FAIR-RITE 2643002402 CORE.L3: FIVE TURNS AWG #26 WIRE ON A CWS BYTEMARK FT-23-61 CORE.LB: 11 TURNS AWG #22 WIRE AIR CORE, 0.450-IN. AVERAGE DIAMETER, LENGTH=0.450 IN.LC: SEVEN TURNS AWG #22 WIRE AIR CORE, 0.300-IN. AVERAGE DIAMETER, LENGTH=0.275 IN.AVERAGE DIAMETER IS THE DIAMETER OF THE CORE PLUS ONE WIRE DIAMETER.

Reed, Dana G, Editor, “Calculating Practical Inductors,” ARRL Handbook for Radio Communications, 82nd Edi-tion, American Radio Relay League, 2005, pg 4.32.

“Practical FET Cascode Circuits, Designing with Field-Effect Transis-tors,” Siliconix Inc, 1981, pg 79.

McLucas, Jim, “Stable, 18-MHz oscillator features automatic level control, clean-sine-wave output,” EDN, June 23, 2005, pg 82, www.edn.com/article/CA608156.

R e fe R e n ce s 1

2

3

Figure 2 This buffered-output, 18-MHz oscillator features a resonant circuit that doesn’t rely on mutual coupling for operation.

november 9, 2006 | EDN 125

readerS SOLVe deSIGN PrOBLeMS

EditEd By Brad thompson and Fran GranvillE

designideas

In addition to their customary roles as indicators and illumi-

nators, modern LEDs can also serve as photovoltaic detectors (references 1 and 2). Simply connecting a red LED to a multimeter and illuminating the LED with a source of bright light, such as a similar red LED, produce a reading of more than 1.4V (Figure 1). One model for a reverse-biased LED comprises a charged capaci-tor that connects in parallel with a light-dependent current source (Ref-erence 1). Increasing the incident light increases the current source and more rapidly discharges the equivalent capacitor to the supply voltage.

Figure 2 shows a method of using an LED as a photovoltaic detector. Con-necting one of the microcontroller’s outputs, Pin 2, to the LED’s cathode applies reverse bias that charges the LED’s internal capacitance to the sup-ply voltage. Connecting the LED’s cathode to Input Pin 3 attaches a high-impedance load to the LED. Illu-minating the LED generates photocur-

rent. Originally charged to the supply voltage, the LED’s internal capaci-tance discharges through the photo-current source, and, when the volt-age on the capacitor falls below the microcontroller’s lower logic thresh-old voltage, Pin 3 senses a logic zero. Increasing the incident-light intensity more quickly discharges the capacitor, and lower light levels decrease the dis-charge rate. The microcontroller, an Atmel AVR ATtiny15 (www.atmel.com/dyn/products/product_card.asp?part_id=2033), measures the time for Pin 3’s voltage to reach logic zero and computes the amount of ambient light incident on the LED. In addi-tion, the microcontroller flashes the same LED at a frequency proportional to the incident light’s intensity.

Figure 3 shows a 3-mm, super-bright-red LED, D1, from Everlight Electronics Co Ltd (www.everlight.com), which comes in a water-clear encapsulant as an ambient-light sen-sor. Having only four components, the circuit operates from any dc-

power source from 3 to 5.5V. The circuit uses only three of six of the AVR ATtiny15’s I/O pins, and the remaining pins are available to con-trol or communicate with external devices. The sensor LED connects to the AVR microcontroller’s port pins PB0 and PB1; another port pin, PB3, produces a square wave with a fre-quency proportional to the incident-light intensity. The circuit operates by

LED senses and displays ambient-light intensity

Figure 1 Two identical LEDs, closely spaced in a light-shielded housing, form a photovoltaic-characterization fixture. Choose resistor R and voltage source V to apply nominal forward current to the illuminating LED.

edn061109d839801 DIANE

DIGITAL VOLTMETER RED LEDAS SENSOR

V

R

RED LEDAS EMITTER

dhananjay v Gadre and sheetal vashist, ECE division, netaji subhas institute of technology, new delhi, india

edn061109di39802 DIANE

R

LED

PIN 2

PIN 3

PIN 1

VCC

INPUT

MICRO-CONTROLLER

Figure 2 Connecting one of the microcontroller’s outputs, Pin 2, to the LED’s cathode applies reverse bias that charges the LED’s inter-nal capacitance to the supply voltage. Connecting the LED’s cathode to Input Pin 3 attaches a high-impedance load to the LED. (Note that pin numbers are repre-sentative only and not actual pin numbers.)

DIs Inside128 AC line powers microcon-troller-based fan-speed regulator

130 Simple circuits sort out the highest voltage

EWhat are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to [email protected].

126 EDN | november 9, 2006

designideas

first applying forward bias to the LED for a fixed interval and then applying reverse bias to the LED by changing the bit sequences you apply to PB0 and PB1. Next, the microcontroller recon-figures PB0 as an input pin. An inter-nal timing loop measures the interval, T, for the voltage you apply to PB0 to decrease from logic one to logic zero.

Reconfiguring pins PB0 and PB1 to apply forward bias to the LED com-pletes the cycle. Time interval T varies inversely with the amount of ambient light incident on the LED. For lower light, the LED flashes at a lower fre-quency, and, as the incident-light inten-sity increases, the LED flashes more fre-quently to provide a visual indication of the incident-light intensity.

For low values of forward current, an LED’s light-output intensity is

fairly linear (Reference 2). To test the circuit, couple the light output of a second and identical LED to the sensor LED, D1, in Figure 3. Ensure that external light doesn’t strike the sensor LED by enclosing the LEDs in a sealed tube covered with opaque black tape. Varying the illuminating LED’s forward current from 0.33 to 2.8 mA produces a relatively linear sensor- flash-frequency plot (Figure 4).

The efficiency of an LED as a sensor depends upon its reverse-biased inter-nal-current source and capacitance. To estimate the reverse photocurrent, connect a 1-MV resistor in parallel with a sensor LED and measure the voltage across the resistor while apply-ing a constant level of illumination from an external source. Replace the 1-MV resistor with 500- and 100-kV

resistors and repeat the measurements. For a representative LED under con-stant illumination and shielded from stray ambient light, we measured a photocurrent of approximately 25 nA for all three resistor values. For the same level of illumination applied to the sensor LED, measure the frequency generated at Pin PB3.

To calculate the LED’s reverse-biased capacitance, substitute the delay-loop time, the LED’s photovol-taic current, and the microcontroller’s logic-one and -zero threshold volt-ages into the equation and solve for C, the LED’s effective reverse-biased junction capacitance: (dV/dt)=(I/C), where dV is the measured logic-one voltage minus the logic-zero voltage, dt is the measured time to discharge the LED’s internal capacitor, and I is the calculated value of LED’s photo-current source. The calculated values for the selected LED range from 25 to 60 pF. This range compares with the data in references 3 and 4, although Reference 3 reports only the current source’s values. You can download the AVR microcontroller’s assembly-lan-guage firmware, Listing 1, from this Design Idea’s online version at www.edn.com/061109di1.EDN

Figure 3 An LED doubles as a light-level sensor. Output PB3 delivers a square wave whose frequency increases as light intensity increases.

edn061109di39803 DIANE

VCC

D1

GND PB0

PB1

PB3

R1100

3

6

5

SQUARE-WAVEOUTPUT

(FOUT)

IC1ATTINY15

4

8

C110 F16V

VCC3 TO 5.5V

00

20

40

60

80

100

120

0.5 1 1.5 2 2.5 3

ILLUMINATING LED FORWARD CURRENT (mA)

IC1 PIN 3 OUTPUT

FREQUENCY (Hz)

EDN061109DI3980FIG4 MIKE

R e fe R e n ce s Dietz, Paul, William Yerazunis, and

Darren Leigh, “Very Low-Cost Sens-ing and Communication Using Bi- directional LEDs,” Mitsubishi Re-search Laboratories, July 2003, www.merl.com/reports/docs/TR2003-35.pdf.

Petrie, Garry, “The Perfect LED Light,” Resurgent Software, 2001, www.resurgentsoftware.com/perfect_ led_light.html. Miyazaki, Eiichi, Shin Itami, and Tsu-tomu Araki, “Using a Light-Emitting Diode as a High Speed, Wavelength Selective Photodetector,” Review of Scientific Instruments, Volume 69, No. 11, November 1998, pg 3751, http://rsi.aip.org.

“Optocoupler Input Drive Circuits,” Application Note AN-3001, Fairchild Semiconductor, 2002, www.fairchild semi.com/an/AN/AN-3001.pdf.

Figure 4 The frequency of the circuit’s square-wave output exhibits good linearity versus light level for identical sensor and source LEDs.

1

2

3

4

128 EDN | november 9, 2006

designideas

A microcontroller requires dc operating power in the 2 to

5.5V range, an amount that a battery or a secondary power source can easily supply. However, in certain situations, a microcontroller-based product must operate directly from a 120 or 220V-ac power outlet without a step-down trans-former or a heat-producing, voltage-decreasing resistor. As an alternative,

a polyester/polypropylene film capaci-tor rated for ac-line service can serve as a nondissipative reactance (Figure 1). Capacitor C1, a 2-mF AVX (www.avxcorp.com) FFB16C0205K rated for 150V rms, provides a significant ac-voltage drop that reduces the voltage you apply to a diode-bridge rectifier, D1. A flameproof metal-film resistor, R1, limits current spikes and transient

voltages induced in the ac-power line by lightning strikes and abrupt load changes. In this application, the ac current does not exceed 100 mA rms, and a 51V, 1W resistor provides ade-quate current limiting. R2, a 5W, 160V Yageo (www.yageo.com) type-J resistor, and D2, a 1N4733A zener diode, pro-vide 5V regulated power for the micro-controller, a Freescale (www.freescale.com) C68HC908QT2.

The schematic shows a represen-tative circuit for a microcontroller-based fan-speed regulator in which a thermistor senses air temperature and the microcontroller drives a

AC line powers microcontroller-based fan-speed regulatorabel raynus, armatron international inc, malden, ma

Figure 1 C1 provides capacitive reactance, which limits ac-input current without dissipating excessive heat in this dc fan-speed controller.

steve EDN061026DI3912 FIGURE 1

120VAC

120VAC RETURN

C12 F250V

R151 R2

1605W

R410k

R3100kLED

1

8

7

33

1

2

2

TH1D1

KB152

C2100 F

D21N4733A

IC1MC68HC908QT2

Q1IRF520

DC LOAD

DC LOAD_

+

_++

COOLINGFAN

Figure 2 A two-diode rectifier and lamp-control bidirectional thyristor share a common return path to the ac line.

steve EDN061026DI3912 FIGURE 2

120VAC

120VAC RETURN

C13 F250V

R151

R23305W

PR1VT90N1

R420k

R3470 Q1

LZ004F31

D4

1

8

7LED

3 31

2

2D11N4003

D21N4003

C2100 F

D31N4733A

IC1MC68HC908QT2

AC LOAD

AC LOAD

+

130 EDN | november 9, 2006

designideas

fan’s motor. Figure 2 illustrates a light-intensity regulator based on an inexpensive two-diode rectifier and a bidirectional-thyristor-lamp con-troller that share a common ground.

IC2, a Fairchild (www.fairchildsemi.com) MOC3021-M bidirectional-thyristor-driver optoisolator, sepa-rates the lamp-return path from the microcontroller’s ground return (Fig-

ure 3). In each of the three circuits, the Kingbright (www.kingbright.com) W934GD5V0 LED indicator includes a built-in current-limiting resistor (not shown).EDN

The cIrcuIT deLIVerS aN aNaLOG-OuT-PuT VOLTaGe equaL TO The hIGheST Of Three INPuT VOLT-aGeS ThaT drIVeS a dISPLay fOr cONTIN-uOuS TeMPeraTure MONITOrING.

Figure 3 An optoisolator separates the bidirectional thyristor’s high-current ac-line return path from the microcon-troller’s power supply.

steve EDN061026DI3912 FIGURE 3

PR1VT90N1

R420k

R3470

R4180

120VAC

120VAC RETURN

C12 F250V

R151 R2

1605W

LED

1

8

7

3

1

2

6

4

2

D1KB152

C2100 F

D31N4733A

IC1MC68HC908QT2

IC2MOC3021M

AC LOAD

AC LOAD

31

2Q1

L2004F31_

++

In a water-cooled power con-verter, analog-output sensors

measure the cooling water tempera-ture at three locations. If any of the three temperatures rises above a pre-set threshold, an alarm sounds and attracts the attention of the system’s operator. When the alarm activates, knowing which measurement site has reached the highest temperature saves troubleshooting time and prevents system damage. The circuit in Figure 1 delivers an analog-output voltage equal to the highest of three input voltages that drives a display for con-tinuous temperature monitoring. LED indicators identify which of three sen-sors shows the highest temperature. An external adjustable-threshold comparator (not shown) monitors the

analog-voltage output and activates an audible alarm.

Each of three analog input signals spans a range of 0 to 10V. Driven by the highest-voltage input, which you

apply at IN1 in this example, opera-tional amplifier IC1A functions as a voltage follower with diode D1 in its feedback path. The op amp’s open-loop gain divides the diode’s forward-voltage drop to a fraction of its nomi-nal value, producing an “ideal diode” with a voltage drop of millivolts.

Op amps IC1B and IC1C function as high-input-impedance inverting com-parators. Each “sees” the highest input voltage on its inverting input and one of two lower input voltages, IN2 and IN3, on its noninverting input and delivers an output voltage near that of the negative-supply-voltage rail. Thus, only IC1A delivers a positive-voltage output to MOSFET Q1’s gate, and IC1B and IC1C deliver negative outputs to the gates of Q2 and Q3. Q1 turns on, lighting LED D4 and drawing approximately 5 mA to develop 11V across R3, which guarantees that Q2 and Q3 and their corresponding LEDs remain off. The voltage that develops across R1 represents the largest voltage of the three inputs, and resistor R4 and

Simple circuits sort out the highest voltageEzio rizzo, nova snC, Genoa, italy, and vincenzo pronzato, Felmi srl, Genoa, italy

132 EDN | november 9, 2006

designideas

capacitor C1 form a lowpass filter that reduces high-frequency noise that the sensor cables pick up. Voltage follower IC1D buffers the filter’s output voltage. Figure 2 (pg 136) shows the results of an LTSpice simulation featuring three sinusoidal inputs and the resultant analog output summed with a small dc-offset voltage for clarity.

The breadboarded circuit works as designed. Given its electrically noisy location near a 300-kHz, 30-kW switched-mode power converter, it

uses slow-switching 1N4004 diodes to avoid malfunctions, which the rectifi-cation of stray high-frequency inter-ference introduces. In less noisy envi-ronments, use any small-signal diode whose peak-inverse voltage exceeds at least 30V. Most varieties of operational amplifiers work well in the circuit, but for greater high-frequency immunity, use a JFET-input quad op amp, such as Texas Instruments’ (www.ti.com) TL084.

Although the circuit’s prototype

uses red-LED indicators, LEDs of other colors work well. To change the LEDs’ current to another value, change the values of R2 and R3, keeping approxi-mately the same 3-to-2 ratio. For example, values of 1.8 kV for R2 and 1.2 kV for R3 drive the “on” LED with approximately 10 mA. If you increase the LED current, note that the resis-tors continuously dissipate power. For greatest reliability, choose resistors rated for twice the calculated power dissipation.EDN

Figure 1 This circuit’s output voltage tracks and indicates the highest of three input voltages and can drive an external strip-chart recorder or alarm comparator.

edn061026di39151 DIANE

IC1ALM324

IC1BLM324

IC1CLM324

R122k

15V

15V

15V

IN1

IN2

IN3

3 4

1

7

8

5

6

9

10

IC1DLM324

13

1412

2

11

D11N4004

D43-mmREDLED

D53-mmREDLED

R23.3k

D21N4004

Q12N7000

Q22N7000

Q32N7000

D31N4004

R32.2k

R422k C1

10 nF

15V

D63-mmREDLED

15V

OUT

_

+

_

+

_

+

_

+

136 EDN | november 9, 2006

designideas

Figure 2 Three sine waves of different frequencies provide input voltages (lower traces) that evoke the greatest-of-three response in the current through R2 (top trace, in which colored horizontal segments match the largest inputs).

Certain medical and scientific instrumentation applications

require amplification and measure-ment of microvolt-level signals. For example, accurately measuring the output of a thermopile-based micro-calorimeter demands an amplifier that achieves high gain and exhibits excel-lent thermal stability and low noise.

Figure 1 illustrates how combining two amplifiers yields a programmable-gain amplifier that provides selectable gains of 160 to 10,240. The circuit also

offers typical offset voltage of 5 mV, off-set drift of 20 nV/8C, and equivalent input-noise voltage of 9 nV=Hz at 0.1 Hz. IC1, a Cirrus Logic (www.cirrus.com) CS3301 low-voltage, differen-tial-input, differential-output, chopper-stabilized programmable-gain amplifier, serves as an input-amplifier stage and drives IC2, a higher voltage INA114 instrumentation-amplifier output stage. The CS3301 provides seven pro-grammable gains of one to 64, and the INA114 provides a fixed gain of 160.

The combination achieves gains of 160 to 10,240. A thermopile produces a 1-mV signal, yielding 10.24V output from the INA114. To select other values of

Chopper-stabilized amplifier cascade yields 160 to 10,240 programmable gain

Figure 1 Combining a programmable-gain, chopper-stabilized amplifier with an instrumentation amplifier delivers high gain and low noise over a subaudible frequency range.

edn061109di39861 DIANE

IC2INA114

IC1CS3301

R3316

R11k

R21k

C10.1 F

15V

7

2

5

15V

4

1510

11

13

OUTPUT

2

10

11

3

151918 13 17 14

680

680

680

680

GAIN0

GAIN1

GAIN2

TO MICRO-CONTROLLEROR DIP-SWITCHGAINSELECT

TO MICRO-CONTROLLER

OR DIP-SWITCH

INPUTSELECT

5

400

400

MULTIPLEXER 0

MULTIPLEXER 1

INA+

INB+

INA

INBIN1

IN2

IN1

VA

IN2

24

23

6

7

4 12 9

5

8

2.5V

VA

2.5V

VD

3.3V

1 16

DGNDPWDNLPWR

Jerome E Johnston, Cirrus Logic Corp, Austin, TX

november 23, 2006 | EDN 75

readerS SOLVe deSIGN PrOBLeMS

EdiTEd By BrAd Thompson And FrAn GrAnviLLE

designideasDIs Inside76 Current-mode instrumentation amplifier enhances piezoelectric accelerometer

78 Low-cost RF sniffer finds 2.4-GHz sources

80 Triangle waves drive simple frequency doubler

EWhat are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to [email protected].

76 EDN | november 23, 2006

designideasgain, change the value of the INA114’s gain-setting resistor, R3.

External DIP switches and pull-up resistors, which connect to the 3.3V supply (not shown), program the CS3301’s gain- and multiplexer-control pins. A microcontroller that can drive 3.3V logic can also control these control inputs. Connecting the CS3301’s outputs and the INA114’s inputs, an RC lowpass filter composed of R1, R2, IC1’s output resistors, and C1 limits noise above 500 Hz.

Figure 2 illustrates the combined amplifiers’ measured input-referred noise performance at a gain of 10,000. With its 1/f noise corner at 0.08 Hz, the amplifier cascade achieves an equivalent input-noise voltage of about 9 nV=Hz at 0.1 Hz. The noise-versus-frequency plot represents the results of FFT processing of more than 2 million output samples over an 18-

hour period. For simplicity, the sche-matic doesn’t show power supplies and bypass capacitors. Due to the circuit’s extreme amplification factor, use con-

struction techniques that maintain thermally balanced component place-ment and electrically balanced pc-trace lengths.EDN

Figure 2 A three-octave plot displays the cascaded amplifiers’ low equivalent-input-noise voltage versus frequency.

A typical piezoelectric sen-sor comprises a disk of PZT-

5A ceramic material with metallized electrodes on its surfaces. Applying

electrically conductive epoxy to the electrodes connects external wiring to the sensor. An insulating adhesive attaches the assembly to the struc-

ture under test and isolates the sensor from ground-referenced potentials. The disk faces the direction of the expected acceleration. When you mount the piezoelectric disk on a tar-get structure, it serves as a simple force sensor and accelerometer by produc-ing a voltage that’s directly propor-tional to the force acting parallel to the disk’s direction of polarization. A piezoelectric disk’s capacitive imped-ance presents a large reactance at

Current-mode instrumentation amplifier enhances piezoelectric accelerometerdave Wuchinich, modal mechanics, yonkers, ny

edn061123di39941 DIANE

IC1INA121

IC3TL081

IC2TL081

VSS

iei

VSS

7

6

8

VSS

7

VSS

7

4

VSS

4

VSS

eO

46

1

2

3

3

2

2

RG100

R210M

R410k

R310k

R510k

C10.1 F

R110M

eoAei

CS

VCMES/2

ES/2

3 6E

PIEZOELECTRIC-SENSOR-EQUIVALENT CIRCUIT

Figure 1 Three amplifiers and a handful of passive components suppress stray noise pickup on a piezoelectric accel-erometer and its wiring.

78 EDN | november 23, 2006

designideaslow frequencies, making the disk and its wiring susceptible to interference that surrounding electrical equipment and power lines produce. Placing the sensor in a remote location requires shielded interconnecting cable, but even shielding is not entirely effective in removing common-mode signals because noise pickup can still occur at the disk’s conductive surfaces.

One method of extracting the sen-sor’s signal employs an instrumenta-tion amplifier, which amplifies only the potential the sensor produces; the amplifier rejects common-mode-cou-pled noise potential that appears on each of the sensor’s terminals.

A typical miniature piezoelectric- disk sensor that’s 0.125 in. in diameter and 0.0075 in. thick presents a capaci-tance of approximately 500 pF. If the measurement application requires a dynamic response to force excitation frequencies of 10 Hz or below, the sensor’s output reactance ranges into the tens of megohms. The circuit’s pc-board insulating substrate and ambient humidity impose a practical limit of approximately 10 MV on the amplifier’s input resistance.

You must carefully choose insulation and apply guarding potentials, and you must use an amplifier with picoampere input-bias currents. Otherwise, the sensor’s capacitance and the amplifi-

er’s input-bias-current resistors impose a phase shift on the signal you apply to the instrumentation amplifier. To eliminate guarding and elaborate insulation requirements, the circuit in Figure 1 uses an instrumentation amplifier with feedback to measure the sensor’s short-circuit current and not its open-circuit voltage. VCM, the common-mode voltage between the sensor and the signal ground, results from nearby noise sources resulting from stray capacitive coupling. The following equation relates the sensor’s output current, i, and its open-circuit output voltage, ES:

where A represents IC1’s voltage gain, and R5R15R2 in Figure 1. Resistors R1 and R2 provide feedback and input-bias-current-return paths for IC1, an INA121 instrumentation amplifier, and resistor RG sets the amplifier’s gain. The INA121’s input-bias-offset current of 0.5 pA produces 5 mV of voltage offset across its 10-MV feed-back resistors. At an amplifier gain of 500, IC1’s output offset amounts to 2.5 mV. Amplifier IC2, a TL081, pro-vides unity-gain signal inversion.

If 2A11..2RjvCS, then i> jvCSES, and amplifier IC1’s input volt-age, VI, vanishes because the ampli-fier’s input terminals act as a virtual short circuit across the sensor. Taking the sum of voltages around the loop comprising the instrumentation and inverting amplifiers’ output, the two feedback resistors and the instrumen-tation amplifier’s input terminals, whose potential difference is zero, yields eO5jvRCES, where eO repre-sents IC1’s output and also the nega-tive value of IC2’s output.

An operational-amplifier-based integrator, IC3, delivers the value for ES at IC3’s output, E9 in the following equation.

For the component values in Figure 1, IC1 provides a gain of 500. Resis-tors R1 and R2 are equal at 10 MV, and the piezoelectric sensor’s capaci-tance measures 500 pF. For the high-est frequency of interest, 10 Hz, the quantity 2RvCS50.6,,2A115501 and the sensor’s output, ES, appear without phase error as E9. This cir-cuit can measure quasistatic force changes; the circuit’s ability to sus-tain a charge on C1 imposes the ulti-mate limit on the circuit’s frequency response.EDN

Equations for DI

Equation

iA

RA

j CS

3994

1

2 1

22 1

=+

+ +

( )

ω

′ =

E

Equation

ERC EC R

S

S S

,

( ).

2

5

Equations for DI

Equation

iA

RA

j CS

3994

1

2 1

22 1

=+

+ +

( )

ω

′ =

E

Equation

ERC EC R

S

S S

,

( ).

2

5

Whether you measure or use RF circuits that operate in

the popular 2.4-GHz ISM (indus-trial/scientific/medical) band, cord-less telephones, Wi-Fi access points, Bluetooth devices, and microwave ovens can radiate RF signals, causing unwanted interference. A spectrum analyzer remains the instrument of choice for detecting and identifying interference sources, but analyzers are expensive, bulky, and sometimes not readily available.

The circuit in Figure 1 shows an easily assembled, low-cost, and porta-

ble RF “sniffer” that provides a quick and reliable reading of the ambient-RF-signal level in the 2.4- to 2.5-GHz frequency band. At the circuit’s heart, a Linear Technology (www.linear.com) general-purpose LT5534 RF-power detector, IC1, measures RF-signal strengths from 255 to 25 dBm and provides an RSSI (received-signal-strength-indicator) dc-output voltage (Reference 1).

An antenna for this frequency band drives FL1, a Toko (www.toko.com) fil-ter (Part No. TDFU2A-2450T-10A), which restricts the circuit’s passband

to 2.4 to 2.5 GHz and limits out-of-band interference. The filter drives IC1, whose internal circuitry comprises a cascade of RF detectors and limiters. The detectors’ and limiters’ summed outputs generate an accurate logarith-mic-linear voltage proportional to the RF input in decibels. A single discrete transistor, Q1, converts IC1’s RSSI output to a current that drives a low-current-LED signal-strength indicator. You can connect a digital voltmeter to IC1’s RSSI output to provide a digital readout of signal strength or rely on the lighted LED to visually indicate an RF signal. Two 1.5V alkaline bat-teries or three nickel-cadmium cells provide 3V power for the circuit.

The LT5534’s frequency range of 50 MHz to 3 GHz covers the VHF, UHF, 800-MHz-cellular-telephone,

Low-cost RF sniffer finds 2.4-GHz sourcesvladimir dvorkin, linear technology Corp, milpitas, Ca

80 EDN | november 23, 2006

designideas

902- to 928-MHz-ISM, 2-GHz-PCS (personal-communications-system)/UMTS (Universal Mobile Telecom-munications System), and 2.4-GHz-ISM bands. For the 2.4- to 2.5-GHz range, use a Laird Technologies (www.lairdtech.com) BlackChip antenna or a Toko dielectric antenna (Part No. DC2450CT1T). To build a sniffer for the 915-MHz band, replace the anten-na with Part No. ANT-916-JJB-ST from Antenna Factor (www.antenna factor.com) and replace the input filter with a Toko 4DFA-915E-10 ceramic filter that provides 26 MHz of bandwidth centered on 915 MHz.EDN

R e fe R e n ceLT5534 data sheet, Linear Technol-

ogy, www.linear.com.

Figure 1 For best results, assemble this 2.5-GHz circuit on a double-sided pc-board layout according to the LT5534’s data sheet and application notes.

edn061026di39751 DIANE

ANTENNA

FL1 RFBANDPASS

FILTERTDFU2A-2450T-10A

RF DETECTORS

6

2, 5

RF DETECTOR LT5534IC1

D1VCC

3

VOUT 1k

24k

1 nF

180

4 1

EN

VCC3.6V

1 FLED

Q1

MMBT3904

RSSIOUTPUT

1

If you use a function generator, you may occasionally require

a sine-wave output at a higher fre-quency than the generator can pro-vide. If your function generator also produces a triangle-wave output, you can use a frequency doubler to extend the generator’s available frequency by as much as a factor of two. A previ-ously published Design Idea describes a triangle-wave-driven frequency-dou-bler circuit employing op amps that produce output frequencies limited to about 20 kHz (Reference 1).

This Design Idea describes a fre-quency doubler that provides a sine- wave output with a frequency of 4 to 6.7 MHz, with an output level that can range from 110 mV p-p to 1.30 V p-p into a 50V load. As Refer-ence 1 describes, applying a sym-metrical triangle wave to a full-wave rectifier produces a triangle wave of twice the input frequency and offset by a dc level. Any asymmetry in the input waveform allows some of the input signal’s fundamental frequency to pass through to the output. Also,

the circuit’s input transformer, T1, may cause amplitude or phase imbalance, allowing some of the input signal to pass through to the output.

To construct a wideband trans-former with good amplitude and phase balance, twist three AWG #30 enameled wires together at about 10 twists/in. Wind seven turns of the bundled wires onto a Fair-Rite (www.fair-rite.com) 2643002402 toroidal core. (Each pass through the core’s central opening counts as one turn.) Connect the wires as shown in Figure 1. (Refer to Reference 2 and Figure 2 for additional information on this type of transformer.) This technique results in a wideband transformer with good amplitude and phase-balance charac-teristics.

To achieve maximum input-fre-quency attenuation, use a matched pair of Schottky diodes for D1 and D2. However, the prototype produced high-quality signals with unmatched Schottky diodes. In Figure 1, diode D3 applies a small negative bias to D1 and D2 that allows operation at low

signal levels. Capacitor C1 passes the rectified and frequency-doubled tri-angle wave to the bases of a comple-mentary emitter follower comprising Q3, Q4, and associated components. A simple, two-element lowpass filter at the follower’s output removes higher frequency harmonics. Use any 1.6-mH inductor with a Q of 20 or greater for L1. Although an inductor with a Q as low as 10 will not noticeably change the filter’s frequency response, a value lower than 20 increases the inductor’s insertion loss and decreases the maximum available output-signal amplitude.

A simple, two-element, lowpass output filter provides adequate per-formance for a symmetrical-triangle-wave input because the output’s fre-quency components consist of the doubled input frequency signal and only the desired output signal’s odd harmonics. For a 5-MHz output, the third harmonic occurs at 15 MHz with an amplitude of 219 dB relative to the 5-MHz signal. The lowpass filter imposes 15 dB more attenuation at 15 MHz, diminishing the 15-MHz sig-nal to 234 dB relative to the 5-MHz output signal and attenuating higher order harmonics to even lower levels.

The complementary emitter follow-er’s unfiltered output signal consists

Triangle waves drive simple frequency doublerJim mclucas, longmont, Co

82 EDN | november 23, 2006

designideas

of a triangle wave of twice the input signal’s frequency, plus odd harmonics of the doubled input frequency. For example, applying a 2.5-MHz triangle wave to the circuit’s input produces a 5-MHz triangle-wave signal at the lowpass filter’s input. For a nearly per-fect triangle wave, the filter’s input consists of a 5-MHz fundamental and only its odd harmonics. At 219 dB below the 5-MHz signal, the 15-MHz

third harmonic represents the closest spurious signal and one that you can easily filter.

To use the circuit at higher frequen-cies, divide the values of output-filter components L1 and C8 by a factor of FNEW/5, where FNEW represents the desired output frequency in mega-hertz. For example, a nominal output frequency of 20 MHz requires division of the values of L1 and C8 by a factor of

four, producing new values of 0.4 mH and 140 pF, respectively. Simulating the circuit with the revised filter in Spice shows adequate harmonic rejec-tion over an output range of 16 to 26.8 MHz. Although designed for 5-MHz operation, the remainder of the circuit works well at 20 MHz without addi-tional modifications. This frequency doubler also accepts a sine-wave input signal. However, the circuit’s unfil-tered output contains higher levels of the desired signal’s even- and odd-order harmonics and requires addi-tional filtering to produce a high-qual-ity sine-wave output.EDN

R e fe R e n ce sBelousov, Alexander, “Frequency

doubler operates on triangle waves,” EDN, March 14, 1996, www.edn.com/ archives/1996/031496/06di4.htm.

Demaw, MF “Doug,” Applying Toroidal Cores: Ferromagnetic-Core Design and Application Handbook, ISBN: 0133140881, Prentice Hall, 1996, pg 97.

edn061123di39721 DIANE

Q4Q3

R915

L11.6 H OUTPUT

C8560 pF

C50.01 F

C30.01 F

C20.01 F

C60.01 F

C40.01 F

C70.01 F

C10.01 F

R4750

R7750

R6500

R822R3

1500D3

1N914

D1SD101C

D2SD101C

R2750

R1220

R522

R1050

LOAD

2N39042N3906

10V

10V

T1

EF

C

A B

D

T1: SEVEN TURNS OF #30 AWGWIREWOUND TRIFILAR

ON A FAIR-RITE 2643002402 CORE.

INPUT50

SIGNALGENERATOR

L1: EIGHT TURNS OF #28 AWG WIRE, WOUND ON AN AMICON FT-23-61 CORE.

INPUT-SIGNAL SPECIFICATIONS:2- TO 3.35-MHz FREQUENCY0.5 TO 5V P-P INPUT

0.11 TO 1.30V P-P OUTPUT

E

EA

AC C

FB DB

DF

TRIFILAR-WOUND TRANSFORMER

EDN061123DI3972FIG2 MIKE

Figure 2 Transformer T1 from Figure 1 consists of three windings on a toroidal ferrite core. For ease of assembly, twist three wires of different colors into a bundle to form the windings.

1

2

Figure 1 A full-wave rectifier, buffer, and lowpass filter produce a sine-wave output at twice the frequency of a triangular-wave input.

December 1, 2006 | EDN 97

readerS SOLVe deSIGN PrOBLeMS

EDItED By BrAD thoMPSon AnD FrAn GrAnvILLE

designideasDIs Inside98 Get power from a telephone line without disturbing it

100 Active-filter circuit and oscilloscope inspect a Class D amplifier’s output

102 Voltage-to-pulse-width con-verter spares microprocessor’s resources

104 Precision voltage reference delivers 80 mA

EWhat are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to [email protected].

Although relatively expensive, monofilar-wound, bipolar step-

per motors provide strong torque for a given physical size. However, each of the motor’s two windings requires eight driving transistors connected in groups of four in an H-bridge configu-ration. Each transistor must withstand and quickly recover from overloads and short-circuit conditions, and a driver must consequently include complex and large discrete-compo-nent protective circuitry.

As an alternative, Figure 1 shows a motor-driver circuit based on Maxim’s (www.maxim-ic.com) MAX9715, a tiny, surface-mount, 2.8W Class D au-dio amplifier, which typically drives 4 or 8V speakers. Each of IC1’s two out-puts consists of a MOSFET H-bridge that drives a pair of output lines, OUTR1 and OUTR2 and OUTL1 and OUTL2, that connect to the stepper motor’s A and B windings, re-spectively. Each pair delivers a differ-ential-pulse-width-modulated signal

with a nominal switching frequency of 1.22 MHz. The circuit’s low-inter-ference design eliminates the require-ment for output-line filters.

Capacitors C1, C3, C4, and C6 pro-vide bypassing for IC1’s power input and bias pins, and C5 and C7 pro-vide bulk-holdup capacitance for the Class D power amplifiers’ out-puts. Capacitors C8 and C9 limit the amplifiers’ input bandwidth to 16 Hz, and L2 and L3 suppress electri-cal-noise pickup by the long input cables. Comprising C1, C2, and fer-rite bead L1, a pi-section noise filter suppresses noise on IC1’s power-sup-

Two-channel audio amplifier drives stepper motor

Figure 1 A single surface-mount circuit and a few passive components can drive a bipolar, monofilar-wound stepper motor.

edn061201di38891 DIANE

C40.1 F

C31 F

C21000 pF

C10.1 F

C81 F

C91 F

VDD

VDD

C5100 F

C60.1 F

VDD

C7100 F

4

1

2

3

9

12

10

11

BLUE

RED

B

A

YELLOW

WHITE

STEPPERMOTOR

IC1MAX9715

PVDD

PVDD

PGND

PGND

OUTL+

OUTR+

OUTL

OUTR

VDD

GND

BIAS

14

7

13

16

15

INL

INR

8

6

5NC

GAIN

SHDN

VDD5V

L1FERRITE

L2FERRITE

L3FERRITE

B STEP

A STEP

NOTES:L1, L2, AND L3 ARE TDK PART NO. MPZ1608S101A.IMPEDANCE IS 100 AT 100 MHz. DC RESISTANCE IS 50 m, AND MAXIMUM CURRENT IS 3A.

Phill Leyva and Bill Quach, Maxim Integrated Products, Sunnyvale, CA

TABle 1 A_STeP AnD B_STeP PUlSe SeqUenCe

Step A_Step B_Step

0 H l

1 l l

2 l H

3 H H

4 H l

98 EDN | December 1, 2006

designideas

ply input. A suitable controller feeds digital pulses to IC1’s A_Step and B_Step inputs, which respectively drive the motor’s right and left chan-nels. Internal short-circuit and ther-mal protection guards the amplifier against overcurrent and short cir-cuits caused by the stepper motor or its connecting leads.

Table 1 illustrates the A_Step and B_Step pulse sequence that rotates a typical stepper motor in one direc-tion by continuous application of steps 0 through 4. Step 4 returns the motor’s shaft to its starting position and completes its 3608 rotation. To reverse the motor, begin at the bot-tom of the table to reverse the pulse pattern and work upward. You can disable both of the amplifier’s chan-nels by applying a logic-low signal to Pin 8, IC1’s active-low SHDN input. Figure 2 illustrates the circuit’s input and output waveforms.EDN

Figure 2 Waveforms from the circuit in Figure 1 include the A_Step input (Chan-nel 1), B_Step input (Channel 2), outputs OUTR1 (Channel 3) and OUTR2 (Channel 4), and the signal that arrives at the motor’s windings (OUTR1 minus OUTR2, middle trace), which the oscilloscope’s math function computes.

An idle telephone line tempts designers to use its 48V poten-

tial as a power source. However, Part 68 of the US Federal Communications Commission’s telecommunications regulations states that any device that connects to the phone line and is not actively communicating must present

a resistance of at least 5 MV (Refer-ence 1). To meet this requirement, a device’s continuous-current drain must not exceed 10 mA. Fortunately, many devices that connect to the phone line do not require continuous power and can remain off for long intervals, awakening only for a short time before

relapsing into power-off mode. Pro-viding power for these applications from the phone line presents obvious advantages by eliminating the need for a battery or another power source and the cost of battery maintenance.

The circuit in Figure 1 charges a 1.5F supercapacitor, C1, from the phone line through a diode bridge and a 5.6-MV resistor. A Maxim (www.maxim-ic.com) MAX917 nanopower comparator, IC1, consumes only 0.75 mA from its power supply. Resistors

Get power from a telephone line without disturbing ityongping Xia, navcom technology, torrance, CA

edn061201di39971 DIANE

IC1MAX917 IC2

LTC3459

L122 H

NC

NC

NC

REF

IN+

VEE

VCC

OUT

1

2

3

4

8

7

6

5

D1 TO D4 +

+

TOPHONE

LINE

R15.6M

C11.5F2.5V

C20.1 F

C41 F

C347 pF C5

4.7 F

Q1

Q2

Q3

FDN339AN FDN339AN

FDN304PZ

R320M

R5324k

R61M

R91M

R72.2M

R81M

R220M

R420M

G

G

S S

D

G

S D

D

ON OFF

CONTROLINPUTS

SW

GND

FB

VIN

VOUT

SHDN

1

2

6

543

5V

OUTPUT

IN4004

Figure 1 This power-conversion circuit delivers intermittent bursts of regulated voltage from a supercapacitor charged by a trickle of current from a telephone line.

100 EDN | December 1, 2006

designideas

R2 and R3 halve the voltage across C1 and apply it to IC1’s positive input voltage at Pin 3 for comparison with its built-in 1.245V reference. For voltages across C1 that do not exceed 2.49V, IC1’s output at Pin 6 remains low. When C1’s voltage reaches 2.5V, Pin 3’s voltage exceeds the reference voltage, and IC1’s output goes high, turning on Q1 and Q2.

Several days must elapse before C1 becomes fully charged, given its huge capacitance and a charging current of less than 10 mA. The voltage on C1 can never exceed 2.5V because, once it reaches 2.49V, Q1 and Q2 turn on, connecting C1 to a switched-mode-power-supply circuit. Because the power-supply current exceeds the

charging current, the voltage across C1 starts to decrease when Q2 turns on. Transistor Q3 holds Q2 on when C1’s decreasing voltage causes Q1 to turn off.

The switched-mode-power-supply circuit comprises a Linear Technology (www.linear.com) LTC3459 micro-power boost converter, IC2, and its associated components, which deliver 5V at 10 mA. A fully charged C1 can supply power to a 10-mA load for approximately 40 sec. With no load, the circuit can sustain its 5V output for more than 10 hours. For greater out-put current and shorter operating time, select another boost converter that can operate at a low input voltage.

Mechanical switches, open-drain

MOSFETs, open-collector transistors, or a microcontroller’s open-drain out-put pins can drive two external control inputs to force the circuit on and off. Pulling the On input low forces Q2 to turn on and deliver power from C1 to the power converter, and pulling the Off input low turns off Q2 and removes power from the converter. Note that the power converter’s output-return line connects to the telephone line and thus should not connect to an earth ground or to grounded equip-ment.EDN

R e fe R e n ce “Part 68,” Federal Communications Commission, www.fcc.gov/wcb/iatd/part_68.html.

1

The increasing acceptance of Class D amplifiers has helped

them gain market share from their

linear Class AB brethren. That acceptance is no surprise; the advan-tages of Class D amplifiers are legion,

but such amplifiers also require new techniques for evaluation. For example, consider a basic sine-wave test of a linear amplifier. You apply power, apply a sine wave of suitable amplitude to the input, and connect an oscilloscope probe to the output. You’ll see a replica of the input, usu-ally offset by about half the power-

Active-filter circuit and oscilloscope inspect a Class D amplifier’s outputJohn Guy, Maxim Integrated Products Inc, Sunnyvale, CA

+

+

STEVE EDN061201DI3963 FIGURE 1

IN

IN

VDD

OUT

GND

C210 F

R88.06k

R58.06k

R922.1k

R1122.1k

R128.06k

R108.06k

C41.5 nF

C111.5 nF

C5100 nF

C3100 pF

C7100 nF

C61 F

C1470 pF

R111k

R211k

R611k

R711k

R322k

R4100

_

+

_

+

C101 F

C91 F

C12100 pF

C810 F

IC1MAX9727

VDD VSS

1

2

3

20

19

18

_

+

_

+

SHDN PVSSPVDD C1NC1P PGND

5

6

89

10

131211

7

16

15

14

4 17

GND

GND

Figure 1 Use this third-order, 30-kHz filter circuit to observe a Class D amplifier’s output signal on an oscilloscope.

102 EDN | December 1, 2006

designideassupply voltage. Even if the linear amplifier drives a BTL (bridge-tied load), you’ll still see a recognizable replica of the input at either end of the load, albeit at half of the output signal that’s available.

Testing a Class D amplifier poses more difficulties. The amplifier’s output comprises a PWM (pulse-width-modulated) signal that swings between ground and the supply volt-age at a frequency that’s usually 200 kHz to 2 MHz. However, when you view this PWM output on an oscillo-scope, you’ll see no resemblance to the sine-wave input.

You can observe a Class D audio amplifier’s output if you introduce the filter circuit in Figure 1. Based on Maxim’s (www.maxim-ic.com) MAX-9727 quad-audio-line driver, IC1, the circuit combines separate single-ended filters—one for each of the BTL outputs’ phases—with a third amplifier that provides a differ-ence signal with additional filtering. The first stage of each single-ended-filter section contributes the com-

plex-conjugate pole pair of a third-order, 30-kHz multiple-feedback Butterworth filter, for which many design guidelines and equations are available. Each third-order-filter sec-tion comprises a complex-conjugate pole-zero pair and one real pole.

To improve the match between the signal paths, the two separate mul-tiple-feedback filters share a real pole, which 470-pF capacitor C1 and 11-kV resistors R1 and R6 provide. The circuit implements that pole as a difference amplifier, thereby producing a filtered output that presents a single-ended version of the BTL amplifier’s outputs. The filters’ signal paths present 5.5-kV impedances to each of the A and B amplifier sections’ inputs. By inspec-tion, the net 5.5-kV impedance from Section B’s output to C1 comprises the Thevenin-equivalent impedance of resistors R6 and R7. Similarly, the net impedance from Section A’s out-put to C1, also 5.5 kV, comprises the Thevenin impedance of resistors R1 and R2. Note that the virtual ground from Amplifier D’s inverting input

effectively grounds resistor R2.Matched resistors attenuate each of

Amplifier D’s differential inputs by 6 dB (IN1 by R1 and R2 and IN2 by R6 and R7). A 22-kV feedback resis-tor, R3, provides Amplifier D with a gain of two, which sets a unity-gain-transfer function in the circuit’s pass-band. The circuit’s single-ended out-put with respect to ground allows the oscilloscope’s ground to also serve as the output signal’s ground. A version of this circuit using conventional op amps would require a negative-power-supply-voltage source, but Maxim’s MAX9727 already includes a nega-tive-voltage source, which its inter-nal charge-pump circuit generates. When you operate the circuit from a 5V supply, the circuit’s output deliv-ers more than 2.5V rms. Although its third-order filter is inadequate for precise measurements of distortion or noise, the circuit provides an excel-lent tool for troubleshooting and evaluating Class D-amplifier circuits and inspecting their outputs on an oscilloscope.EDN

Although not an ADC in the classic “stream-of-ones-and

zeros” sense, this voltage-to-pulse-width converter produces a logic-level output pulse whose variable width represents an analog of the input voltage. Based on Atmel’s (www. atmel.com) AT89LP4052 micropro-cessor, IC1, this circuit makes efficient use of the target microprocessor’s limited analog-port pinout and code space by using a modified version of the classic timed-discharge-RC (resis-tor-capacitor) ADC design.

The timed-RC ADC allows a capacitor to charge through a resis-tor while the microprocessor incre-ments a counter. When a compara-tor detects that the capacitor voltage

and analog- input voltage are equal, the count terminates, and its stored value represents the ADC’s output. However, an RC network’s exponen-tial charging characteristic produces a nonlinear conversion. Various soft-ware and hardware techniques can partially correct the nonlinearities, but all entail adding code, increas-ing the circuit’s development time, or consuming additional I/O-port pins required for other purposes.

To produce a linear-charging characteristic that needs no correc-tion, the circuit in Figure 1 uses an LM334 constant-current source, IC2, to drive capacitor C2, which connects to IC1’s AIN0 analog-input port. An internal timer in the microcontroller

measures the elapsed time from the charging ramp’s start to the instant when the ramp voltage crosses the analog-input-voltage threshold at IC1’s AIN1 port.

In this application, potentiometer RV1 provides an analog-input voltage proportional to its position. The width of the positive-going pulse at the out-put, P1.5, varies in proportion to the analog-voltage input. Note that I/O-port pin AIN1 serves a dual purpose as an analog input and as an open-drain output that discharges ramp-forming capacitor C2 before the next conver-sion cycle.

An 8-bit voltage-to-pulse-width- conversion cycle completes in less than 4 msec. The code performs the conversion function and outputs a pulse train at IC1’s port P1.5 (Pin 17) with a period of 100 msec and a positive-going pulse width propor-tional to the analog-input voltage at Pin 13 (AIN1). Programming con-nector J1 provides access to IC1 for

Voltage-to-pulse-width converter spares microprocessor’s resourcesJames Christensen, Kris Design Co, El Cajon, CA

104 EDN | December 1, 2006

designideas STEVE EDN061201DI3977

VDD

VDD

VDD

7

13

VV

LM334IC2

R36.04k

R117.4k

R

C22200 pF

C330 pF Y1

12 MHz

C430 pF

C110 F

R222k

J1

RV125k

R4499

2.8 mSEC

10 mV

00 1 mSEC

V (IC1, PIN 12)

4.25V

TIME

IC1AT89LP4052

P1.0/AIN0

P1.3P1.4

P3.7

P1.1/AIN1

XTAL1

XTAL2

VCC

VDD

VDD5V

VDD

P1.5P3.2/INT0

P1.7

P3.1P3.0

P1.2P3.5

P1.6P3.4/T0

RST/VPP

GND

P3.3/INT1

11

7

1

3

5

9

8

2

4

6

10

15

12 12176

1923

18

18

10

149

16LSS

5

4

LMOSI

LSCK

LRST

LMISO

LMOSINC

NC

LSCK

LSS

PROGRAMMINGCONNECTOR

LRST

LMISO

VOUTVARIABLE-WIDTH OUTPUT PULSE

VOUTTIME

Figure 1 An analog-voltage-to-pulse-width converter features minimal parts. Subgraphs show timing-network and output-voltage waveforms. IC1’s unlabeled pins are available for user functions.

uploading the compiled code. The AT89LP4052 microprocessor typi-cally executes one instruction per clock cycle, and a 10-msec timer routine can perform the required

housekeeping functions with plenty of time left over for other program tasks, including a future application that requires a binary-coded analog-to-digital output. You can download

Listing 1, which is written in C for the Keil Software (www.keil.com) compiler, from the online version of this Design Idea at www.edn.com/061201di1.EDN

Large analog systems that pres-ent many loads to a voltage-ref-

erence source can often demand more current than a single reference IC can deliver. However, if the reference IC includes force and sense terminals, you can easily add a buffer to the circuit’s

feedback loop without affecting the reference’s accuracy. For example, the circuit in Figure 1 provides the same 0.04% initial accuracy and 7-ppm/8C temperature coefficient as IC1, a stand-alone MAX6033. The buffer circuit delivers as much as 80 mA.

When you design a buffer stage for a force/sense-control loop, the buffer must provide unity-voltage gain with no phase inversion. In addition, the circuit’s power supply must provide head-room voltage to accommodate the reference voltage plus voltage drop across the buffer stage. The sim-plest buffer circuit comprises an NPN transistor that connects as an emit-ter follower, which requires a drive voltage that exceeds the reference’s output voltage by one transistor base-

Precision voltage reference delivers 80 mAJames horste and Gary Staiman, Maxim Integrated Products Inc, Sunnyvale, CA

106 EDN | December 1, 2006

designideas

emitter voltage drop. If you add the required minimum power-supply voltage plus the maximum allowable base-emitter voltage, the configura-tion runs out of head room. Using a PNP stage to drive the emitter drive stage solves the head-room problem but inverts the output voltage and prevents the force/sense loop from functioning. Adding a second PNP stage cancels the phase inversion but destabilizes the force/sense loop by adding excessive gain.

The modified complementary Dar-lington, or Sziklai, connection (Refer-ence 1) in Figure 1 solves both prob-lems by providing an emitter follower’s unity-voltage gain with no inversion. The output PNP stage provides plenty of head room, but the NPN stage does not. You can easily overcome this drawback by adding diode D1 to shift the NPN transistor’s emitter voltage downward by a diode drop. Thus, to a first approximation, the diode’s voltage drop and the transistor’s base-emitter voltage cancel one another, leaving plenty of voltage head room.

Transistor Q2, a 2N2907, provides lim-ited current gain, which in turn limits the circuit’s maximum output current to 80 mA. Substituting a higher gain transistor can increase the output cur-rent to any reasonable level.

For stability, the MAX6033 requires 0.1-mF ceramic bypass capacitors on its In and OutF pins. Capacitor C2 deter-mines the circuit’s response speed, but the buffer circuit exerts no significant effect on transient response. Most dc-

reference-voltage ICs cannot accom-modate a fast-changing load-cur-rent step; thus, the circuit’s transient response and its ability to supply fast current spikes depend on the output capacitor, CLOAD. Values of CLOAD as high as 10 mF do not affect the cir-cuit’s stability.EDN

R e fe R e n ce “Sziklai Pair,” Wikipedia, http://en.wikipedia.org/wiki/Sziklai_pair.

edn061201di39311 DIANE

GND

IC1MAX6033A

D11N4148

R22.7k

R110k

C20.1 FC1

0.1 F

INOUTF

OUTS

5V

CLOAD

Q2

Q1

2N2907

2N2222

RLOAD

5V

VOUT =4.096V

Figure 1 Add a two-transistor output buffer to a 4.096V, 15-mA reference IC to boost its output current to 80 mA or higher.

1

december 15, 2006 | EDN 67

readerS SOLVe deSIGN PrOBLeMS

EDItED By BRAD tHOMpSON AND FRAN GRANVIllE

designideasDIs Inside70 Magnetic-field probe requires few components

72 Dynamic siphon steals current from USB port

EWhat are your design problems and solutions? Publish them here and receive $150! Send your Design Ideas to [email protected].

Based on a previously pub-lished Design Idea (Reference

1), the circuit in Figure 1 uses on-ly three I/O lines to drive 12 LEDs. In this application, the circuit serves as a tachometer for a motor-vehicle engine and displays relative engine speed on an array of LEDs arranged in a line or a circular arc. Three pairs of inverse-parallel-connected LEDs (D2 and D3, D4 and D5, and D6 and D7) receive drive current from IC1’s ports through current-limiting resis-tors R5, R6, and R7. Two groups of

three LEDs, D8, D9, and D10 and D11, D12, and D13) connect among IC1’s ports and two voltage dividers that supply reference voltages VREF1 and VREF2. Varying the values of resistors R5, R6, and R7 adjusts the brightness of the middle six LEDs, and R1, R2, and R4 control the brightness of the outer six LEDs. In general, this cir-cuit can use N of a host micropro-cessor’s I/O lines to drive as many as N(N21)12N LEDs, or 2N more LEDs than the circuit in the original Design Idea could drive.

The circuit uses Microchip’s (www.microchip.com) PIC10F200 micro-controller, IC1, a small, inexpensive, six-pin device that provides only three I/O pins and one input-only pin. The I/O pins—GP0, GP1, and GP2—drive a 12-LED bar graph comprising

Three microcontroller ports drive 12 LEDs

Figure 1 A PIC microprocessor and a 12-LED bar-graph display form a simple tachometer circuit. (The decoupling capaci-tors are not shown.)

Nedjeljko lekic and Zoran Mijanovic, University of Montenegro, Department of Electrical Engineering, podgorica, Montenegro

STEVE EDN061215DI3993 FIGURE 1

VCCVCC5V

VDD5

6

2

4

3

1

GP3INPUT

VSS

NOTE: LEDs ARE PANASONIC SSG LN224 SERIES (RED), LN324 SERIES (GREEN), AND LN424 SERIES (YELLOW).

GP2

GP1

GP0

R3390k

R5100 R1

3.3k

R22.7k

R42.2k

Q2BC213C

VREF2

Q1BC182C

R6100

D8 D9

D6

D7

D2

D11 D12 D13

D3

D4

D5

D10

VREF1

R7100

IC1PIC10F200

D11N4148

68 EDN | december 15, 2006

designideas

four yellow LEDs, four green LEDs, and four red LEDs driven in multi-plexed mode (Figure 2).

The microprocessor’s input-only pin, GP3, serves as the input for puls-es coupled from the ignition coil’s pri-mary terminal. Resistor R3 and diode D1 provide input-signal conditioning, and a software-debouncing routine re-moves ringing effects from the pulses. Given R3’s high value of 390 kV, the circuit tolerates high-voltage input spikes and prevents latch-up of the PIC10F200. Port GP3, which serves as the processor’s programming port, differs from the processor’s other ports because it incorporates an internal protection diode. The 20-mA diode prevents GP3 from negative-going transient voltages. The circuit oper-

ates reliably, but you can add an ex-ternal protection diode for enhanced protection against transient-induced latch-up. Connect the diode’s anode to ground and its cathode to pin GP3 of IC1.

You can configure the bar graph to indicate engine speed by the number of LEDs turned on (bar mode) or by illuminating only one or two LEDs (dot mode). The color scheme in Fig-ure 2 uses yellow LEDs to indicate too-low speed, green LEDs for nomi-nal speed, and red LEDs for excessive speed. Figure 3 shows the indicator software’s flow chart. The processor’s internal clock drives Timer0 to over-flow every 512 msec, which repre-sents one time slot—that is, a mul-tiplexing phase. Of eight time slots, one drives the three upper LEDs, and a second drives the three low-er LEDs. For software simplicity, the last six time slots drive the middle

LEDs one by one. At the start of the main loop, the microprocessor counts clock pulses and waits for Timer0 to overflow. After overflow occurs, the output ports drive the LEDs accord-ing to their assigned time slots. After eight time slots elapse, the processor sets the ports to the same state. After 200 time slots, the processor counts incoming tachometer pulses and sets the LED pattern according to the in-coming pulse count—that is, accord-ing to input frequency.

The tachometer indicates rotary speed as high as 120 cycles/sec. The accompanying software listings avail-able at www.edn.com/061215di1 in-clude files in C language (led12.c.pdf) and in assembly language (led12.asm.pdf). The source zip file contains a complete MPLab project. Figure 4 shows the waveforms, which a digital oscilloscope captured at ports GP0, GP1, and GP2.EDN

Figure 4 A digital oscilloscope captures the waveforms of GP0, GP1, and GP2 (upper to lower traces, respectively), which show a transition in the LED pattern from Case 7 to Case 8 (lines 62 and 63 in Listing led121.c.pdf).

STEVE EDN061215DI3993 FIGURE 3

START

INITIALIZATION

COUNT INCOMINGPULSES

TIMER0OVERFLOW?

NO

NO

YES

YES

NEXT LED’SDRIVE TIME

SLOT

KK1

K0

SET LED PATTERNVERSUS

PULSE COUNT

K200?

Figure 3. This flow chart shows the LED-driver software routine. (See the listings at www.edn.com/061215di1 for the complete tachometer routine.)

EDN061215DI3993FIG2 MIKE

Figure 2. The bar graph display’s 12 LEDs can form a linear array or circular arc (not shown).

70 EDN | december 15, 2006

designideas

Popularly known as “gauss me-ters,” various makes and mod-

els of magnetic field meters are avail-able on the market at prices that make them unaffordable to many hobbyists and engineers. This Design Idea com-bines a commonly available DMM (digital multimeter) with a single semi-conductor component to measure mag-netic-flux density and, in turn, mag-netic-field intensity.

Figure 1 illustrates the measurement equipment, comprising a probe, its bat-tery pack, and a DMM. The probe’s ac-tive element consists of a linear Hall-effect sensor. Although virtually any linear Hall sensor will work in this ap-plication, this version of the probe us-es an Allegro MicroSystems Inc (www. allegromicro.com) A1323 sensor, which produces a voltage proportion-al to an applied magnetic field (Refer-ence 1). Operating from a power sup-ply of 4.5 to 5.5V, the A1323’s quies-cent output voltage (zero-field output) rests at 50% of the supply voltage. Giv-en its nominal sensitivity of 2.5 mV/gauss, the A1323 provides a full-scale range of 1800 gauss (4.5V/2.5 mV/gauss51800 gauss) for a supply volt-age of 4.5V.

Applying a magnetic field orient-ed south of the sensor’s face increases the sensor’s output voltage in propor-tion to the applied field perpendicular to the sensor’s branded face, and apply-ing a magnetic field north of the same face causes a proportional decrease in output voltage. For a supply of 4.5V, the sensor’s quiescent output voltage of 2.25V can increase to 4.5V for a 900-gauss, due-south field or decrease to 0V for a 900-gauss, due-north field. Although the sensor can detect the in-tensity and polarity of a dc magnetic field, its ac-field bandwidth extends to 30 kHz.

The probe’s breadboard version com-prises a small piece of pc board of suf-ficient length to fit the operator’s hand (Figure 2). The sensor’s leads connect to a length of high-quality, three-con-ductor shielded cable and two 10-nF surface-mounted decoupling capaci-tors. The sensor’s power supply compris-es three series-connected, miniature, 1.5V batteries for a total of 4.5V. For

a larger full-scale-measurement range, use a 9V battery to feed a 5V regulator IC, such as a 7805 voltmeter and add an on/off switch if desired. Place the batteries near the meter. Otherwise, the batteries’ steel cases will disturb the magnetic field under observation. Use 10-nF SMD capacitors to decouple the sensor’s input and output pins. Al-though any DMM offering high dc ac-curacy and an ac bandwidth exceeding 50 kHz can display the sensor’s output, a DMM with a RELD (“relative-differ-ence-from-reference-reading”) func-tion, such as a Fluke (www.fluke.com) model 187 DMM, eases measurement

Magnetic-field probe requires few componentsRama Sarma, EMI-EMC Centre, RCI, Hyderabad, India

Figure 1 A digital multimeter and a Hall-effect sensor form an easily assem-bled magnetic-field probe.

STEVE EDN061215DI3942 FIGURE 1

_ +

PC BOARD

SHIELDEDCABLE

BATTERY PACKTHREE 1.5V CELLS

A V COMM

TWO 4-MMBANANA PLUGS WITH

19-MM SPACING

RED

BLACK

WHITE

SHIELD

PROBE

LINEAR HALL-EFFECT SENSOR(ALLEGRO PART NO. A1323)

DIGITAL MULTIMETER

PACKAGE LH(SOT-23W)PIN 1 VCCPIN 2 VOUTPIN 3 GND

IC1

1

C10.01F

C20.01F

2

3

REL

72 EDN | december 15, 2006

designideas

and polarity detection of a dc magnetic field (Reference 2).

After assembling the circuit, connect the probe’s output to the DMM using two 4-mm banana plugs. Allow a one-minute warm-up and place the probe’s sensor in a magnetically shielded en-closure. (Editor’s note: You can use sal-vaged steel, or “tin,” concentrically fit-ting food cans to build a magnetically shielded enclosure. Arrange the cans so that their unopened ends point in opposite directions. Drill a small open-ing in the larger can’s unopened end to accommodate the sensor’s output cable.) Press the DMM’s RELD func-tion key. The DMM’s display will show the sensor’s quiescent voltage output of 2.25V as 0.0000V, indicating that the probe is calibrated for a zero magnetic field and ready for use.

Remove the probe from the shield-ed enclosure and measure the magnet-ic field under observation. To achieve maximum sensitivity, place the sensor’s face perpendicular to the field. If the field’s direction is unknown, rotate the probe about its longest axis to search for maximum voltage. To calculate the magnetic-flux density, divide the out-

put-voltage reading by the sensitivity (2.5 mV/gauss). For example, if the meter reads 21.9800V, then the mag-netic field is 792 gauss due north. For an ac-magnetic-field measurement, use the DMM’s true-rms mode to read the sensor’s ac output voltage.

You can calculate a magnetic field’s intensity in air by applying the follow-

ing formula: B5m03H, where B rep-resents magnetic-flux density in tes-las, H represents magnetic-field in-tensity in amperes per meter, and m054p31027H/m (the permeability of free space). Given that the tesla rep-resents a relatively large measurement unit, a 1T field is quite strong.

For greater measurement resolution, apply the following conversion factors to use the gauss, a more popular unit: 10,000 gauss51T, 1 gauss579.6 A/m, 1.2560 mT51 kA/m. Applications for the magnetic-field sensor include troubleshooting moving-magnet lin-ear-position detectors, fabrication of dc motors and audio speakers, inves-tigation of low-frequency-magnetic-field interference, and designing and fabricating electromagnetic-interfer-ence shields.EDN

R e fe R e n ce S A1323 Ratiometric Linear Hall-Effect Sensor Data Sheet, Allegro MicroSystems Inc, www.allegromicro.com/sf/1321. User’s Manual, Model 187 & 189, True RMS Multimeter, Fluke Corp, www.fluke.com.

Figure 2 The digital multimeter’s relative-change mode (RELD) displays a near-zero magnetic field reading and the sensor’s nominal zero-field output voltage of 2.25V.

1

2

A USB port offers a handy source of 5V power for auxilia-

ry devices. A USB port not only sup-plies power to a microcontroller and other essential circuitry, but also pro-vides enough extra current head room to charge a small battery or supercapac-itor energy-storage element. One typi-cal approach to exploiting a USB port’s leftover-current capability begins with an estimation of the essential circuit-ry’s maximum current drain. You then place an appropriate current-limiting

Dynamic siphon steals current from USB portDonald Schelle, Maxim Integrated products Inc, Sunnyvale, CA

edn061201di39431 DIANE

ESSENTIALCIRCUITRY

ENERGY-STORAGEELEMENT (BATTERY,

CAPACITOR)

CURRENT-LIMITINGDEVICE

LIMITS CURRENTTO 200 mA

300 mA MAXIMUM TO100 mA TYPICAL

USB PORT

USB CURRENTHIGH POWER=500 mA MAXIMUMLOW POWER=100 mA MAXIMUM

Figure 1 In this typical method for drawing power from a USB port, the stor-age-element current is limited to a fixed value that is less than optimal.

74 EDN | december 15, 2006

designideas

device in the path of the energy-stor-age device (Figure 1). Although easy to implement, this method doesn’t use all of the current available from the USB port, and the energy-storage de-vice slowly charges or recharges.

The circuit in Figure 2 uses all avail-able USB power by dynamically ad-justing the amount of current deliv-ered to the energy-storage device and thereby siphoning a relatively constant and maximum current from the USB port. IC1, a Maxim (www.maxim-ic) MAX4173FEUT; IC2, a Maxim MAX-6123AEUK25; and the load-switch circuit comprising Q1, Q2, R2, and C4 form a control loop that limits the cur-rent flowing through Q1. The circuit maximizes current flowing to the en-ergy-storage element (Figure 3) by ensuring that the sum of battery and essential-circuitry currents never ex-ceeds the maximum of 500 mA for a high-power USB device. To reconfig-ure the circuit for low-power USB op-eration of 100 mA maximum, you can replace IC1 with a MAX4173HEUT, a device with 100V/V gain, and R1 with a 0.25V resistor.EDN

Figure 3 These waveforms taken from Figure 2 show that the sum of the essential-circuitry current (middle trace) and storage-element current (bottom trace) never exceeds the 500 mA maximum that the USB port (top trace) specifies.

edn061201di39432 DIANE

IC2MAX6129-AEUK25

IC1MAX4173-

FEUT

R10.11%

C6150 F

10V

IN OUT

OUT

NCNC

3

1

1

3

4 5

6

6

2

4

31

5

2

5

4

2GND

C20.1 F

C10.1 F

C30.1 F

C41 F

R21k

Q2

FDN359AN

C5150 F

10V

+

VUSB

RS+ RS

VCC

GND GND

5V FROM USB PORT

2.5V REFERENCE

MAX4238AUT

VUSB

Q1

FDS66794

3 5 6 7 821

TO ENERGY-STORAGE ELEMENT

TO ESSENTIALCIRCUITRY

+

IC3

_

+

0 TO 500 mA=0 TO 2.5V

Figure 2 This circuit continuously monitors the total current drawn from the USB port and dynamically adjusts the storage-element current to avoid exceeding the port’s maximum output capability.