EDN Design Ideas 2003

The circuit tracer in Figure 1 is ahandy tool for finding connectivitypaths on a pc board. Because the

sense voltage you use to measure the pathis lower than a transistor’s V

BEvoltage,

you can use the design in circuits con-taining semiconductor elements withoutaffecting the measurement. The tracer’s

output takes the form of audio tones. Anopen circuit produces ticks at the rate ofapproximately one per second, and ashort circuit results in a 2-kHz tone. Anaudible sensing device is ideal for a cir-cuit tracer, because your eyes can focuson the circuit paths you’re tracing andnot on a meter movement. If you wantto find the connections to a circuit point,a useful technique is to attach a lead tothat point and just scan the other leadover the other sections of the circuit.When you hear a high-pitched tone, thenyou know that you have a pc-board con-nection.

With practice, you can quickly deter-mine the quality of the circuit path bydiscerning the wide dynamic range ofticks to tones. You can also detect thepresence of capacitors, which produce asweeping tone as they charge. The circuitin Figure 1 is sensitive enough to pro-duce a noticeable audio change if you

make contact with a circuit with wet fin-gertips. R

1produces a 0.4-mA current to

bias the current mirror comprising Q1

and Q2. Q

1, the resistance-sense transis-

tor, is the heart of the circuit. The resist-ance between its emitter and V

CCdeter-

mines C2’s charge current. Because C

2

receives current from a constant-currentsource, the waveform on the capacitor isa linear ramp. When C

2 charges and pass-

es IC1’s threshold, IC

1generates an out-

put pulse. R2

determines the dischargerate for C

2. IC

2, a 74C74, converts the

NE555 pulses to symmetrical squarewaves to differentially drive the piezo-electric speaker. With normal, day-to-dayuse, the 9V battery should last approxi-mately a year.

SHORT1

101001 k

10 k100 kOPEN

193318881541741190305.6~1

RESISTANCE

TONE FREQUENCY

(Hz)

VCC RESET

DISC

THRES

TRIG

GND

OUT

CTRL1

6

TEST LEAD 1

TEST LEAD 2

D1

Q1 Q2

D2

C1

0.1 F0.1 F 10 F

C2

0.047F

0.1 F

R1

20k

R2

100

1N4148

2N3906 2

7IC1

NE555

IC2

74C74

8 4

5

3

3

CLRD Q

CLK

PRE

Q

+

4

2

1

1 2S1

B1

9V

6

5

PIEZO SPEAKER

RADIO SHACK 273-073F igure 1

Design makes handy audible circuit tracerJerry O’Keefe, Cupertino, CA

Use your ears to test continuity with this audible-tone circuit tracer.

Is this the best Design Idea in this issue? Select at www.edn.com.

www.edn.com January 9, 2003 | edn 71

ideasdesign

Design makes handy audible circuit tracer......................................................71

Design a visible optical link for RS-232C communications ....................72

Hot-swap structure offers improved redundancy ..................................72

Embedded processor directly drives LCD..........................................76

Publish your Design Idea in EDN. See theWhat’s Up section at www.edn.com.

Edited by Bill Travis

72 edn | January 9, 2003 www.edn.com

ideasdesign

For redundancy purposes, a num-ber of power supplies, using ORingdiodes, can work into the same load.

During maintenance, when you can re-move any power supply, the minimumpossible power perturbation at the loadis desirable. To compensate for the volt-age drop across the ORing diodes, youmust connect the power-supplyfeedback lines after the diodes, atthe load. Thus, the feedback con-nection is common for all participatingpower supplies (Figure 1). Because ofnatural variations in each power supply,only the one with the highest V

OUTis ac-

tive. The others, sensing the “higher”out-put voltage, try to reduce their own outputs, effectively turning off their reg-

ulation. If you remove the “active” mod-ule from the setup similar to Figure 1, it

causes VOUT

to dip (Figure 2). Figure 2aapplies to a linear module that compris-es two regulators that have independent3.339 and 3.298V output voltages. Bothhave loads of approximately 10 in par-allel with 100 F. Figure 2b applies to aboost configuration that comprises tworegulators with 5.08 and 4.99V outputs,each loaded with approximately 2.5 inparallel with 100 F. The sags and glitch-es in the voltages arise from the inevitabledelay for another power supply to step inand to start the regulation. Costly power-supply bricks deal with this problem byusing current-sharing techniques. Thetechniques provide roughly equal out-put-current distribution among all pow-er modules, thus keeping all modules ac-

PS1

R1A

D1

D2

R1B

R2A

R2B

OUTFB

PS2

OUTFB

VCC LOAD

F igure 1

Hot-swap structure offers improved redundancySamuel Kerem, Corvus Corp, Columbia, MD

A standard redundant configuration of power-supply modules uses ORing diodes at the out-puts.

Design a visible optical link for RS-232C communicationsShyam Tiwari, Sensors Technology Ltd, Gwalior, India

The design in Figure1 is a visibleoptical link

for those who need to seethe transmitted data. Anisolation figure of morethan 5000V is a bonus.Tests of the system usedthe COM input of adata-acquisition system,as well as a standard PC’sCOM port. The MC1489converts the RS-232Cdata to TTL signals. A7404 gate then invertsthe signal. The output ofthe 7404 drives Q

1, a

2N3055 power transistor. The transistordrives the set of three LEDs to form alight source. When no data exists on theRS-232C port, the LEDs remain off.When data transmission takes place, theLEDs glow at the rate of the data trans-mission. Keep the optical receiver 50 cm

away from the LEDs to obtain maximumisolation. The MRD5009 phototransistordirectly converts the light to a TTL out-put. (A TIL99 phototransistor also workswell.) You should also isolate the powersupply to the MRD5009/TIL99 and theMC1488 from the power supply of the

receiver circuit. The MC1488 is a TTL-to-RS-232C converter.


2

5

Rx

RS-232CCOM PORTRECEIVE

D31N4007

D41N4007

12V

12V

12VAC

12VAC

MC1488

5V

TIL99MRD5009

R54.7k

R222

R322

R422

5V

SUPER-BRIGHTLEDS

LM78053

2

1

Q1

R11k

2N3055

12V

7404MC1489

Tx235

RS-232CCOM PORTTRANSMIT

110V60 Hz

D11N4007

D21N4007

F igure 1

This circuit provides a visible indication of RS-232C data transmission.


ideasdesign

(a) (b)

When you remove one supply from the redundant configuration, you incur sags (a) and glitches (b) in the output voltage.

F igure 2

tive. The configuration in Figure 3 addslittle cost to a power system. Theimprovements in performanceare evident in Figures 4a and 4b, repre-senting the two types of redundant pow-er-supply modules.

An instrumentation amplifier, IC1,

measures and produces a voltage,V

C, proportional to the current going

into the regulator. VC

in turn controls V

OUT, pushing the regulator into active

mode. For most adjustable controllers,V

OUTV

REF(1R

A/R

B), where R

Ais R

1A,

and RB

is R1B

for module 1. If no currentflows through R

SENSE, IC

1’s output is close

to ground, paralleling R1B

with the re-sistances of D

1.2, R

11, and R

12, thereby

making RB

smaller and VOUT1

conse-quently higher. The increase needs onlyto compensate the V

OUTvariation be-

PS1

VCC

D1.1

D1.2

R1A

VOUT1

R1B

D2.1

VOUT2

C1R12

R11VC

R13

OUTFB

VCC

LOAD

HOTSWAP

MODULE 2

MODULE 1

R1SENSE

R2SENSE

OUT

IN+

RG

RG

IN

IC1

F igure 3

(a) (b)

F igure 4

The addition of an instrumentation amplifier and a few passive components provides sag- andglitch-free redundant performance.

Linear (a) and boost (b) regulators use the scheme in Figure 3 to eliminate sags and glitches in the output voltage.

tween same-configuration power sup-plies. This variation is only a few per-centage points. If the current into theload rises,V

Calso rises, reducing the cur-

rent through D1.2

and consequently re-ducing V

OUT1. When IC

1’s output rises

and differs from VFB

by less than the di-

rect voltage drop across D1.2

, no currentflows through D

1.2. Thus, V

OUT1, for any

higher current, stays at the value theabove equation defines. With the properselection of R

3(the instrumentation am-

plifier’s gain-setting resistor), R2

and R1

from other modules provide the required

current into the load from all power sup-plies, guaranteeing that they stay in activecondition.


ideasdesign


Driving a bare LCD does not nec-essarily require specializedinterface circuitry or pe-

ripherals. This Design Idea describes analternative drive scheme, which you caneasily implement using the general-pur-pose outputs of a microcontroller. Manyembedded-system applications need tointeract with a user by displaying simplenumeric or alphanumeric characters.Seven- or 14-segment LED displays arereadily available at low cost and in manysizes. However, their relatively high pow-er requirements and limited readabilityin direct sunlight restrict their use in bat-tery-powered, portable devices. LCDmodules driven by HD44780-compatiblecontrollers offer simple interface charac-teristics, low power consumption, andgood readability. However, their cost isrelatively high, and their large dimen-sions sometimes preclude their use insmall enclosures. Bare LCDs overcomethese disadvantages. However, their driverequirements are usually nontrivial. Fig-ure 1 shows the usual waveforms you useto drive an LCD with four backplanes.The algorithm uses four discrete voltagelevels for all LCD signals. Synthesis ofsuch signals without dedicated periph-erals or an external controller is difficultand requires many components. Fortu-nately for users of general-purpose mi-crocontrollers without specialized on-chip peripherals, an alternative exists.Figure 2 shows the alternative wave-forms.

The algorithm uses only three voltagelevels on the backplane pins and only twovoltage levels on the front-plane pins ofthe LCD. Such waveforms are easy to syn-thesize using the general-purpose pins of

F igure 1

Embedded processor directly drives LCDDaniel Malik, Motorola, Czech Republic

In the standard waveforms for driving LCDs, the algorithm uses four discrete voltage levels for allLCD signals.


ideasdesign

a microcontroller. Figure 3 shows a typ-ical application of the alternative algo-rithm, using a general-purpose micro-controller. You implement the BPx(backplane) connections using general-purpose, tristatable outputs of the mi-crocontroller. The FPx (frontplane) connections require only ordinary, gen-eral-purpose outputs. You obtain theV

DD/2 voltage on the BPx pins by tristat-

ing the microcontroller’s pins. (You canusually obtain this result by configuring

the pins as inputs.) Modernmicrocontrollers operatefrom a wide range of power-supply voltages. Altering themicrocontroller’s power-sup-ply voltage is an effective wayof adjusting the LCD’s con-trast. Figure 4 shows exam-ples of LCDs driv-en by general-pur-pose microcontrollers fromMotorola (www.motorola.

com). Figure 4a shows a display withtwo11-segment organization; for Fig-ure 4b, the organization is four16 seg-ments. Figure 5 shows the modificationof the waveforms for the smaller displayof Figure 4a, using only two backplanes.

F igure 2

VDDVDDVDDVDDMICROCONTROLLER

BPO..3

FPxx

F igure 5

You can use a general-purpose microcontroller to drive anysize LCD.

A general-purpose MC68HC908GP32 drives a two11-segment LCD (a) and a four16-segment LCD (b).

This modification of an LCD has only two backplanes.Alternative LCD-drive waveforms use only three voltage levels on the backplane pins.

F igure 4

F igure 3


(a)

(b)

Some applications require a cir-cuit to indicate that a bat-tery’s voltage has fallen below

a certain value. However, if you don’t fre-quently check the indicator, the low-bat-tery indicator itself can easily dischargethe battery. The circuit in Figure 1 indi-cates when the battery voltage hasdropped below a preset value. The circuitdraws less than 50 A, regardless ofwhether the indicator flashes. IC

1Aoper-

ates as a simple comparator. IC2, a low-

current voltage reference, supplies thereference voltage to Pin 2 of comparatorIC

1A. Resistor R

1provides an adjustable

trip point. A potentiometer setting of124 k yields a trip point of approxi-mately 10.3V. When the power-supplyvoltage is above the trip point, IC

1A’s Pin

1 is high, forward-biasing diode D1

andholding the flasher in the off state. R

2

provides approximately 300 mV of hys-teresis for the detector. IC

1Bprovides the

flashing of the LED. C1

charges throughR

3, and, when its voltage exceeds the volt-

age at IC1B

’s Pin 5, Pin 7 pulls low, dis-charging the capacitor through the LED.Resistors R

4and R

5provide a voltage ref-

erence, and resistor R6

provides hystere-

sis of approximately one-third of thesupply voltage.

The circuit’s current consumption is45 A at 10V, climbing to 48 A at 12V.The state of the flasher does not affectcurrent consumption, because the LEDreceives its power via the capacitor. Youhave to make a number of trade-offs toachieve this low current consumption:

For example, discharging the capacitorthrough the LED allows the circuit toreuse the capacitor’s charge, instead ofdumping it to ground. It also eliminatesthe current spikes that occur when driv-ing the LED from the supply rail. How-ever, the charge on the capacitor limitsthe resulting LED brightness, so youshould use high-efficiency LEDs whenpossible.

Another trade-off is that the LED af-fects the minimum operating voltage be-cause of the forward voltage drop of thediode. In the prototype, a red LED worksdown to a lower operating voltage of4.3V. A yellow LED in the same circuitoperates down to 6.4V. Additionally, thehigh resistances on the board, most no-tably the resistors attached to IC

1B’s Pin

5, require careful attention to boardcleanliness. Small leakage currents cansignificantly affect circuit operation andcurrent drain. You can reduce the valuesof these resistances to improve manufac-turability at the expense of higher currentconsumption.

LMC6762AIC1A

_

+LMC6762A

IC1B

510k

IC2LM28.5-1.2

3

2

R1250k

CW

940k

30M

R2

1 5

6

7

C11 F

R31M

D1

470

R6

10M

R410M

R510M

+

_

F igure 1

Fleapower flasher draws less than 50 AGary Butterfield, IEC Electronics Technology Center, Newark, NY

This fleapower flasher indicates a low-battery condition with a flashing LED.


www.edn.com January 23, 2003 | edn 75

ideasdesign

Fleapower flasher draws less than 50 A ..............................................75

PC-based configurable filter uses no digital potentiometers ..................76

Frequency source feeds entire lab ............80

Circuit sequences supplies for FPGAs ........................................................82




ideasdesign

Modern instrumentation re-quires digital control signals. Thesesignals come from a central mi-

croprocessor or, in modern context, thepopular parallel or serial PC ports. In re-cent times, digital potentiometers haveeliminated the hassles from this interfacefor the analog section. Designers can re-place the resistors of the analog designwith digital potentiometers, thus provid-ing the necessary digital control. Howev-er, digital potentiometers suffer more se-verely from temperature-sensitiveperformance drifts than their manualcounterparts, and they exhibit finitewiper-resistance effects. The design inFigure 1 represents a multifunction, ana-log biquadrature design for automatedmixed instrumentation. You can config-ure the design for both Q factor and cen-ter frequency via a PC’s parallelport. The circuit requires no DACsor digital potentiometers. The circuit,

PC-based configurable filter uses no digital potentiometersSaurav Gupta and Tejinder Singh, New Delhi, India

2

1

3

4

5

6

7

8

9

10

11

12

13

14

16

18

20

22

23

24

25

D0

D1

D2

D3

D4

D5

D6

D7

PARALLELPORT

LE

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

CE

IC174573

GND VCC

VCC

VHP

VBP

R7

R2

R6

VIN

4.7k

IN4D1

D2

D3

D4

S1

S2

S3

S4

IN3 IN2 IN1

2.2k

10k

100k

220

IC5OPA4242

R4

R11k

R34.7k

R54.7k

IN4D1

D2

D3

D4

S1

S2

S3

S4

IN3 IN2 IN1

2.2k

10k

100k

220

V+ V+ GND

+

+

+

IC4DG308A

IC3DG308A

IC2DG308A

IN1

D1

D2

D3

D4

S1

S2

S3

S4

IN2 IN3 IN4

22k

10k

47k

100k

V+ V GND

V+ V GND

0.01 F

0.1 F 0.01 F

0.01 F

14/

IC5OPA42421

4/IC5

OPA424214/

5V

0.1 F 0.01 F

5V

VLP

4.7k

5V

F igure 1

You can use a PC-configurable filter design to select both Q and center frequency.

This user-friendly screen helps you configure the desired filter.

F igure 2

based on a two-integrator config-uration, provides simultaneoushighpass, lowpass, and bandpassoutputs.

By running simple code on thePC, you can choose from morethan 150 programmable combina-tions of Q factor and center fre-quency (Listing 1). You can thusbuild a filter of desired parameterson the fly. The design uses quadanalog switches DG308 from Max-im (www.maxim-ic.com) togetherwith octal latches for programma-bility. A micropower precision opamp, OPA4242, from Burr-Brown(www.ti.com) makes up the ana-

log-filter section. The softwareprovides the data bits on portspin 2 through 9, stored in thelatch that controls the analogswitches and, hence, selects theappropriate resistance combina-tion to select the desired Q and f

0

values. The center frequency andQ values are: f

0[1/C

1C

2R

P6R

P7]1/2

and Q(1RP2

/R1)/3, where R

P2,

RP6

, and RP7

are PC-programma-ble resistances.

Data nibbles from port pins D2through D5 provide ganged-switch settings for R

P6and R

P7,

ensuring that they are alwaysequal. Data nibbles correspon-


ideasdesign

TABLE 1—DATA BITS FOR Q SELECTIOND9 D8 D7 D6 Q

(100k) (47k) (22k) (j10k)1 1 1 1 2.240 1 1 1 2.351 0 1 1 2.50 0 1 1 2.651 1 0 1 2.90 1 0 1 3.121 0 0 1 3.40 0 0 1 3.721 1 1 0 4.70 1 1 0 5.360 1 0 0 61 0 1 0 6.380 0 1 0 7.721 1 0 0 11.011 0 0 0 33.72

LISTING 1—C PROGRAM FOR PC-CONFIGURABLE FILTER


ideasdesign

ding to pins D6 through D9 controlthe value of R

P2; hence, you use them

for Q-value selection. For the givenresistance values, Table 1 shows thedata bits for different values of Q(ranging from 2.24 to 33.72). Table 2shows the data bits for various cen-ter frequencies (159 Hz to 38.70kHz). Figure 2 shows the softwarefront-end screen to make the selec-tion. The design uses an 8.11-kHz fil-ter with Q-factor 2.9 for demonstra-tion and hardware validation.Listing 1 gives the necessary back-end C code. The switches employed havea finite on-resistance, R

DS, of approxi-

mately 150, which the design takes intoaccount. For higher precision, you can

use better switches having on-re-sistances of approximately 35.Note that more switches provide awider range from which to select.You can choose the resistances tosuit the application’s bandwidthrange. You can download the filtersoftware from the Web version ofthis Design Idea at www.edn.com.

TABLE 2—DATA BITS FOR CENTER-FREQUENCY SELECTION

D5 D4 D3 D2 f0 (kHz)1 0 0 0 0.1590 1 0 0 1.5191 1 0 0 1.750 0 1 0 6.370 1 1 0 7.961 1 1 0 8.110 0 0 1 30.680 1 0 1 32.20 0 1 1 371 1 1 1 38.7


Plumbing a laboratory with astandard frequency makes a lot ofsense if the lab uses multiple fre-

quency counters, spectrum analyzers, andother frequency-dependent test equip-ment. Rather than spending time keepingall of the instruments’ oscillators in cali-bration or buying expensive, high-preci-sion oscillators, you can use the circuit inFigure 1 to distribute a single calibratedfrequency source to the external-refer-ence input of each instrument. The cir-cuit represents a simple,10-MHz source and dis-tribution amplifier. Theoutput comes not fromthe emitter or collectorof the Colpitts-oscillatortransistor, Q

1, but rather

from the current flowingin the 10-MHz crystal.The common-base stage,Q

2, converts this current

into a voltage and estab-lishes the correct dc level for the output am-plifier, IC

1. This IC con-

tains four gain-of-two bufferswith 110-MHz, 3-dBbandwidth and can drive

double-terminated 50 or 75 loads.As Figure 1 shows, the outputs use

75 impedance levels to take advantageof inexpensive F-type connector hard-ware and low-cost video coaxial cable. IC

1

also provides good isolation between itsoutputs, so that changes in loading onone output do not affect the other out-puts. The circuit delivers more than 6dBm to each termination. If high accu-racy and low drift are critical needs, youcan substitute Hewlett-Packard’s (www.

hp.com) HP10811A component oscilla-tor for the Colpitts oscillator. Connect theHP10811A’s output through a 510 re-sistor and a 10-nF coupling capacitor, di-rectly to the emitter of Q

2. If you need

more than four outputs, you can dupli-cate the IC

1stage as many times as nec-

essary.

RG-59/U

RG-59/U

RG-59/U

RG-59/U

CLOCKOUTPUTS

IC1LT6551

10 F

47 nF

10k

20k

Q22N3906

47 nF

5V

7 TO 45 pF10k

10k

3.3k 100 pF

100 pF

10 MHz

Q12N3904

47 nF

330

330

75

75

75

75

10 nF

10 nF

10 nF

10 nFF igure 1

Frequency source feeds entire labMitchell Lee, Linear Technology Corp, Milpitas, CA

A laboratorywide distribution system is an alternative to multiple frequency sources.



ideasdesign

System designers must consider thetiming and voltage differences be-tween core and I/O power supplies (in

other words, power-supply sequencing)during power-up and power-down. The

possibility of a latch-up failure or exces-sive current draw exists when power-sup-ply sequencing does not occur properly.The trigger for latch-up may occur if pow-er supplies apply different potentials to the

core and the I/O interfaces. FPGAs andother components with different se-quencing requirements further compli-cate the power-system design.To eliminatethe sequencing problem, you should min-

AGND

VSENSECOMP

PWR80

BOOTPH

PH

PH

PH

PH

PH

PH

PH

PH PGNDPGND

PGND

PGND

PGNDVINVIN

VIN

VIN

VIN

VBIASTRACKIN

ENART

IC2TPS546B0PWP

PWRPAD

1

23

4

5

6

7

8

9

10

11

1213

14 1516

18

19

17

20

21

22

23

24

25

26

27

28

J41.8V

CORE SUPPLY

12

22 F 22 F 22 F

0.68 H

GND

IN

IN

EN

OUT

OUT

OUT

OC

3.3VI/O SUPPLY

12

J3

10 F

1

2

3

4 5

6

7

8

IC1TPS2034D

10kR1

470 pF

301

R29.78k

1 F

10 F

71.5k

R310k

R49.76k

10 F

ENABLEJ2

12

J13.3VINPUT

SUPPLY

12

10 F 10 F

10k

10k

470 pF

12 pF

0.047 F

F igure 1

Circuit sequences supplies for FPGAsDavid Daniels, Texas Instruments, Dallas, TX

This power-supply-sequencing circuit eliminates latch-up problems and reduces FPGA start-up transient currents.

F igure 3

As the I/O-supply voltage rises smoothly toward 3.3V, the core voltageclamps cleanly at 1.8V.

F igure 2

When the I/O-supply voltage decays, the core voltage gracefully followssuit.


ideasdesign

imize the voltage difference between thecore and the I/O supplies during power-up and -down. The power supply in Fig-ure 1 regulates the 3.3V input voltage tothe 1.8V core voltage and tracks the 3.3VI/O during power-up and -down to min-imize the voltage differences between thesupply rails.

The circuit in Figure 1 comprises IC1

and IC2, a TPS2034 power switch and a

TPS54680 step-down switching regulator,respectively. Component IC

1is a high-side

power switch that generates a slow rampthat IC

2tracks during start-up. The ramp

time of 6 msec minimizes the inrush cur-rents to the bulk capacitors on the power-switch and supply outputs. The slow rampminimizes the transient-current draw ofthe FPGA. The power switch ensures thatthe I/O voltage is not applied to the loadbefore IC

2has enough bias voltage to op-

erate and generate the core voltage. As-suming that the input supply voltage is at3.3V on J

1, floating the J

2connector en-

ables component IC1. The I/O supply volt-

age, J3, slowly rises until it reaches 3.3V. As

the I/O voltage rises, the core voltage sup-ply, J

4, rises accordingly until the voltage

reaches 1.8V (Figure 2). The TPS54680device incorporates an analog multiplex-er on the TRACKIN pin to implement thetracking function.

During power-up and -down, when thevoltage on the TRACKIN pin is lower thanthe internal reference of 0.891V, the volt-age on the TRACKIN pin connects to thenoninverting node of the error amplifier.When the TRACKIN pin is below 0.891V,the pin effectively functions as the switch-ing regulator’s reference. The resistor di-vider of R

3and R

4on the TRACKIN pin

must equal the resistor divider of R1

andR

2in the feedback compensation to track

with minimal voltage difference duringpower-up and -down. The TPS2034 hasan on-resistance of 37 m and can supplyas much as 2A output current. TheTPS54680 is a synchronous buck regula-

tor that contains two 30-m MOSFETs.Because the TPS54680 can source and sinkas much as 6A load current at efficienciesgreater than 90%, the output can track an-other power-supply rail during power-down. When the IC

1device becomes dis-

abled by shorting J2

to ground, the I/Osupply voltage decays, and the core sup-ply voltage follows once the I/O voltagefalls below the core voltage (Figure 3).Typically, Schottky diodes connect to theoutput of a dual power supply to clampthe voltage difference between the coreand the I/O supplies during power-down,but most applications do not require thediodes with the power-supply circuit inFigure 1. Using this power-supply designreduces component count and increasesreliability by eliminating the potential forlatch-up and reducing FPGA start-uptransient currents.


www.edn.com February 6, 2003 | edn 85

ideasdesignEdited by Bill Travis

Many electronic-control sys-tems have digital outputsthat use transistors. One

method of improving the security inthese outputs is to use an oscillating sig-nal to represent a logic-high state insteadof a fixed voltage level (Figure 1). Thistype of signal, a dynamic variable, candrive the circuit shown in Figure 2. Thiscircuit connects to the output transistorof the electronic-control system. The dy-namic-variable signal connects to theoutput transistor, whose collector con-nects to a pulse transformer. If the systemcannot produce pulses because of a fault,the relay deactivates. If a fault exists in thedrive circuitry, the output system staysoff. This solution guarantees the securi-ty function when one fault occurs. How-ever, it does not guarantee the detectionof all faults. However, you can use aDPDT relay and connect one ofthe contacts to one of the elec-tronic-control inputs; thus, you can con-firm the relay’s activation or deactivationin the control program.

The circuit in Figure 2 performs effi-ciently if the system can generate a fre-quency greater than 1 kHz to excite the

pulse transformer. Many electronic sys-tems that use an output transistor cangenerate a dynamic variable. Many sys-tems, such as PLCs (programmable-log-ic controllers), have long cycle times and,thus, cannot generate signals of adequatefrequencies. In these cases, you can ob-tain an appropriate signal using the low-frequency dynamic variable from thePLC. To accomplish that task, you mustuse an external oscillator and a pulse de-tector implemented with a monostablemultivibrator. The oscillator produces a

square-wave signal of a frequency thatsuits commercial pulse transformers.This signal drives the MOSFET when thepulse detector receives pulses from thePLC. Because the pulse detector can fail,you must duplicate the external circuitfor redundancy. In this way, the final re-sult is the same as that of Figure 2, ex-cept that the safe output comprises tworelays.

LEVEL 1LEVEL 0 LEVEL 0

STATIC VARIABLE

DYNAMICVARIABLE

Oscillating output improves system securityJorge Marcos and Ana Gómez, University of Vigo, Vigo, Spain

You can improve the reliability of an electronic-control output by using an oscillating, instead ofsteady-state, signal to represent a logic-high state.

FUSE

GATE_MOSMOS

IRFD110G

D

S

TRANSFORMERSKPT25B3

2

3

1N4002

1N5347BZENERVZ10V 1

4

5

6

1N4002

1 F

RELAY16

1

NO1

NC1

NC2

NO2

9

11

8

6

13

4

COM1

COM2

24V

A “dynamic-variable” signal drives the output relay in this circuit.

Oscillating output improves system security................................................85

Polarity protector outperforms Schottky diodes ..............................................86

Circuit offers improved active rectification ..........................................86

Build an adjustable high-frequency notch filter ........................................................90

Bootstrapping allows single-rail op amp to provide 0V output ....................92

Filter allows comparison of noisy signals ..............................................94


F igure 1

F igure 2


86 edn | February 6, 2003 www.edn.com

ideasdesign

The polarity-protection circuit inFigure 1 is a high-performance al-ternative to the usual series diode

(often Schottky). The circuit incurs amuch lower voltage drop than even thebest Schottky diode. The circuit uses

MOSFET devices because of their lowon-resistance. For the transistors in thisdesign, the combined on-resistance is0.013. With a 10A load, the voltagedrop is 0.13V at 25C. Compare this fig-ure with forward-voltage drops of sever-al hundred millivolts for Schottky diodesunder the same conditions.You must usep- and n-channel transistors in series be-cause of their intrinsic diodes. A photo-voltaic isolator provides the appropriategate drive to the MOSFETs. The per-formance is even better at lower currents.You can replace the two discrete transis-tors by a single-package, complementa-ry-MOSFET pair, such as an IRF7389,which has a combined on-resistance of0.108. Resistors R

2and R

3 are necessary

to turn off the transistors when IC1

turnsoff. R

1provides a nominal 12V input.

100k1.2k

D214V FOR

15.5V OVP

+

D1IN4002

IRF7822Q1

IRF7425Q2

IC1PVI5033

1 2 3 4

10k

INPUT

R22.2M

R32.2M

8 6 57R1

OUTPUT TOPROTECTED CIRCUITRY

F igure 1

Polarity protector outperforms Schottky diodesMike Hovenga, BAE Systems, Austin, TX

This polarity-protection circuit incurs lower forward-voltage drop than the best Schottky diodes.Is this the best Design Idea in this issue? Select at www.edn.com.

Rectifiers convert acsignals to dc. You cancombine a diode

and a load resistor tocreate a half-wave rectifier,provided that the amplitudeof the ac source is much larg-er than the forward drop ofthe diode (typically 0.6V).Unfortunately, you can’t usethis method to rectify signalsthat are smaller than a diodedrop. For these applications,active rectifiers using ampli-fiers are available. The diodeis inside the feedback loop ofan amplifier (Figure 1). For V

IN0V, the

diode provides negative feedback, and theoutput, V

OUT2, follows the input (V

OUT2

VIN

). For VIN

0V, the diode does not

conduct, the amplifier is in an open-loopconfiguration, and V

OUT2~0V. Figure 2

shows the response of the circuit in Fig-ure 1. The output is shown in green; the

input is shown in red.If V

IN0V, the amplifier

behaves as a comparator.Its negative input is at ahigher potential than itspositive input, so its out-put,V

OUT1, saturates to V

EE.

When the input again be-comes positive, the ampli-fier has to recover from sat-uration and respond asquickly as its slew rate andsaturation recovery timeallow. This response takessome time, and the inputmay have changed by the

time the amplifier is ready to respond tothe positive input. The signals at V

OUT1

(red) and VOUT2

(green) clarify this point(Figure 3).V

OUT2is the same waveform as

_

+

AD85914 SD V

V

VCC

VCC

VEE

VIN

3

1

1N4154

VOUT1 VOUT2

5k

F igure 1

Circuit offers improved active rectificationReza Moghimi, Analog Devices Inc, San Jose, CA

This circuit is a typical half-wave-rectifier configuration.


ideasdesign

in Figure 2. Note the change in scale fac-tor. V

OUT1is a diode drop higher for pos-

itive inputs and saturates to VEE

for neg-ative inputs. The time delay in theresponse may result in a significant er-ror in the output.

For example, an amplifier that has aslew rate of 2.5V/sec and saturates to2.5V takes at least 1 sec to getready to respond to positive in-puts. During this time, the fast in-put has changed, so rectification starts atthe wrong part of the input. One way tominimize this error is to use a high-slew-rate amplifier, but this solution comes atthe expense of high power consumption.Another option is to use an inverting-amplifier configuration and two diodes,followed by a unity-gain inverting am-plifier to obtain the noninverting recti-fication. This method appears in manytextbooks. The circuit in Figure 4 repre-sents a one-stage, noninverting rectifierthat improves the accuracy of therectification and reduces the pow-er consumption. In this circuit, anAD8561 amplifier acts as a comparator.The AD8591 performs the rectification.

When VIN

0V, the output of theAD8561 is high, and the AD8591 acts asa follower. When V

IN0V, the output of

the AD8561 is low, and the AD8591 shutsdown. This shutdown puts the output ofthe AD8591 into a high-impedance state,so it remains at approximately 0V, ratherthan saturating to V

EEas it did in the pre-

vious circuit. When VIN

goes positive, theamplifier comes out of shutdownand again follows the input. Thisturn-on time (the time it takes to comeout of shutdown) is much shorter thanthe saturation recovery time and slew-rate limiting that occurs in the previouscircuit. Figure 5 shows the signals at theinput (red) and output (green) of the im-proved rectifier circuit.

VIN

4

4

5

1

6

78

2

3

3 V

V

V

V

SD

VCC

VCC VEE

VEE

5k

VOUT1

AD8591

AD8561

1

_

+

_

+

This circuit greatly improves on the performance of the circuit in Figure 1.

These signals appear at the input (red) and output (green) of the circuit in Figure 4.F igure 5


These signals appear at the input (red) and the output (green) of the circuit in Figure 1.F igure 2

These signals are the waveforms at VOUT2 (green) and VOUT1 (red) in the circuit inFigure 1.

F igure 3

F igure 4


ideasdesign

Although you can obtain universal,resistor-programmable switched-ca-pacitor filters that are configurable

as notch filters, most cannot operate atbandwidths higher than 100 kHz. Fur-ther, the typically 16- to 20-pin packagesdo not include a continuous-time, an-tialiasing filter to prevent spurious signalsfrom appearing at the output. By usingan eight-pin, dual operational amplifierand an eight-pin, switched-capacitor

bandpass filter, you can construct a notchfilter (Figure 1). IC

2, a TLC082 is a dual

BiCMOS op amp, replacing the olderJFET-input stage with lower noise CMOSbut retaining the bipolar output for highdrive capability. The gain-bandwidthproduct of the TLC082 is 10 MHz, al-lowing you to use it for filtering at fre-quencies as high as 1 MHz. The mini-mum (V

CCV

EE) span with the TLC082

is 5V, unlike the older TL082, which re-

quired 6V. This supply span matches wellwith IC

1, an MSHFS6, with its 5V nomi-

nal operating voltage. Using half of theTLC082, you can construct a third-order,elliptic lowpass filter.

You set the passband ripple at approx-imately 5 dB to increase the out-of-bandrejection.You set the continuous-time fil-ter for 800 kHz, providing greater than 40dB of rejection at 12.5 MHz. Figure 2shows the frequency response of the

TUNABLE SIXTH-OCTAVE BANDPASS FILTER

THIRD-ORDER, 800-kHz ELLIPTIC LOWPASS FILTER

SUMMING STAGE

IC2B

+

MSHFS6SIC1

FSEL

OUT

TYPE

CLK

IN

GND

VSS

VDD

TLC082

5

64

7

8NOTCHOUTPUT

10kV2

6.25 MHz5V

10k

10k

IC2ATLC082

3

2

4.7k

VDD

100 nF

10 pF

100k

4.7k

47 pF

4.7k

10 pF

1k 470 nF

SIGNALINPUT

20

47k

2.4k

1

4

8

5V

100 nF 47k 10 pF

2.4k

edn021226di30991Heather

_

+

_

+

F igure 1

Build an adjustable high-frequency notch filterJohn Ambrose, Mixed Signal Integration Corp, San Jose, CA

An op amp and a switched-capacitor filter combine to form a highly selective notch filter.

This Bode plot represents the passband of theMSHFS6 filter.

This plot is the frequency response of the third-order lowpass-filter stage.

F igure 2 F igure 3


ideasdesign

third-order lowpass filter using theTLC082. The MSHFS6 switched-capacitor selectable lowpass/band-pass filter with its 12.5-to-1 clock-to-corner ratio allows for distortionmeasurements to 6.25 times thenotch center frequency beforealiased signals cause measurementerror. With the TLC082 lowpass fil-ter set at 800 kHz, you can measuredistortion products as high as thethird harmonic. If the notch centerfrequency is always set lower than260 kHz (MSFS6 clock at 3.3 MHz),then you can set the continuous-time lowpass filter corner toa lower frequency by adjust-

ing the resistor and capacitorvalues. By summing the outputof the bandpass filter with the in-put, cancellation of the input sig-nal occurs at 180 phase shift inthe passband. Figure 3 shows theBode plot of the passband of theMSHFS6 sixth-octave filter set-ting. The output of the other halfof the TLC082 provides thenotch-filter output. Figure 4shows the depth of the notch fil-ter at 50 dB.

Is this the best Design Idea inthis issue? Select at www.edn.com.

The circuit in Figure 1 delivers a 50-dB notch.F igure 4

Many single-supply-powered ap-plications require amplifier-out-put swings within 1 mV—or even

submillivolts—of ground. Amplifier-output-saturation limitations normallypreclude such operation. Figure 1’s pow-er-supply bootstrapping scheme achievesthe desired characteristics with minimalparts count. IC

1, a chopper-stabilized am-

plifier, features a clock output. This out-put switches Q

1, providing drive to the

diode-capacitor charge pump. Thecharge pump’s output feeds IC

1’s V ter-

minal, pulling it below 0V, thus permit-ting an output swing to and belowground. In Figure 2, the amplifier’s Vpin (Trace B) initially rises at supplyturn-on but heads negative when ampli-

fier clocking commences at approxi-mately midscreen. The circuit provides asimple way to obtain output swing to 0V,allowing a true “live-at-zero” output.

LTC1150IC1

V+

5V

CLOCKOUT

2N390439k

100k

5V

1k

10 F

10 F

BAT85V

Q1

+

+

_

+

F igure 1

Bootstrapping allows single-rail op ampto provide 0V outputJim Williams, Linear Technology Corp, Milpitas, CA

This configuration uses bootstrapping to allow a single-rail op amp to oper-ate at 0V output.

This start-up photo shows that the amplifier’sV pin (Trace B, midscreen) goes negative

when the bootstrapping takes hold.


F igure 2

A5V/DIV

B0.2V/DIV

5 mSEC/DIV


ideasdesign

When you need to compare the dclevel of a noisy signal witha reference for further pro-

cessing, the output of the comparatorchanges in a chaotic way when the dc lev-el approaches that of the reference. Youhave a choice of two classic solutions tothis problem: One is to add hysteresis tothe comparator, but, if the noise level ishigh, the hysteresis must be correspond-ingly high. In this situation, you face awide dead-band zone around the com-parison trip point. The second solutionis to add lowpass filtering to the noisy sig-nal. This approach increases the responsetime, slowing down the system. This De-sign Idea proposes a third solution thatavoids the cited drawbacks. In the circuitin Figure 1, the noise adds to the refer-ence through a highpass filter, so thecomparator’s inputs see only the differ-

ence between the two dc levels:VV

DCSIGV

NOISEV

HYS,VV

DCREF

VNOISE

, and VVVDCSIG

VCREF

VHYS

,where V is the voltage on the com-parator’s positive input, V is the voltageon the negative input, V

NOISEis the noise

riding on the signal, and VHYS

is the hys-teresis accruing from the positive feed-back to the positive input.

C1, R

4, R

5, and R

6form the highpass fil-

ter, whose cutoff frequency is fC

1/[2C1(R

4R

5)||R

6]. The cutoff fre-

quency should be lower than the lowestfrequency of the noise band. R

1and R

2es-

tablish the still-needed small amount ofhysteresis. R

3is a pullup resistor for the

open-collector output of the comparator.The comparator circuit worked success-fully in a system that processes the fluc-tuating current generated by an ioniza-tion chamber in a neutron-flux meas-urement system.

LM339

R13.3k 5

4

0.68 FC1

3

12

2

15V

15V

15V

7.5kR3

R2220k

R4

R5

270k

100k

470kR6

VSIG

_

+

F igure 1

Filter allows comparison of noisy signalsMario Milberg, CNEA, Buenos Aires, Argentina

By presenting the noise signal to both inputs ofthe comparator, this circuit can compare the dclevels of the signal and the reference.


www.ednmag.com February 20, 2003 | edn 79

ideasdesign

Deadband circuits find applicationsin servo-control systems.A precisioncurrent source and a half-wave in-

verting rectifier form a positive deadbandcircuit (Figure 1).The REF01, IC

1, is a pre-

cision 10V voltage reference. It forms aprecision current source with the additionof a unity-gain buffer (IC

2A) and resistor

R1. IC

2Aforces the ground pin (Pin 4) of

IC1

to assume the potential at IC2A

’s non-inverting input. IC

1forces its highly accu-

rate reference voltage (10V) across R1, so

the current I1

through R1

is 10V/R1. Be-

cause the inverting input of IC2B

connects

to the output of the current source, thefeedback diode, D

1, becomes forward-bi-

ased with current I1. The forward-biased

diode keeps the output of IC2B

at approx-imately 0.6V. Because the cathode endof D

2stays at virtual ground through R

3,

D2remains reverse-biased.Hence,V

OUTre-

mains at virtual ground (0V).Any positivevoltage applied to V

INfurther forward-

and reverse-biases D1

and D2, re-

spectively, and the output remainsat 0V (deadband zone) for V

IN0V.

Negative inputs tend to forward-biasD

2and reverse-bias D

1. This bias situation

occurs only when the current through R2

(because of the negative VIN

) equals or ex-ceeds 10V/R

1. So, the output is 0V (dead-

band) until VIN

reaches a value equal to10R

2/R

1. If you choose R

120 k,V

OUT

remains at 0V for VIN

(5V); forV

IN(5V), V

OUT(V

IN5V). Figure

2 shows the transfer function for this sce-nario. C

1, C

2, and C

3are decoupling ca-

pacitors for IC1

and IC2. R

4reduces the

offset voltage of IC2B

in the nondeadbandregion. You could realize an alternative

straightforward circuit by prebiasing theinverting half-wave rectifier through aprecision resistor connected to a voltagereference without using the unity-gainbuffer, IC

2A. However, this alternative

would increase the noise gain, thereby in-creasing the offset and noise at the output.

Build a precision deadband circuitV Manoharan, Kochi, India

Build a precision deadband circuit ............79

DDS and converter form signal generator ............................................80

48-input16-output crosspoint IC elimi-nates the need for multiplexer amps ........84

Transmission line tests 1-kW device using only 100W ............................................86



15V 10V

10k

R45k

15V

_15V

58

467

OP271

GND

VIN

IC1

R1 R2

R3

10k

D11N4148

D21N4148

C46.8 pF

I1

I1=10V/R1

VIN

C10.1 µF

IC2A

IC2B

VOUT

VOUT

2

0.1 µF

C30.1 µF

C20.1 µF

6

4

2

+

+

_

_OP271

13

REF01

F igure 1

This circuit exhibits a deadband for signals more positive than an arbitrary voltage, which R1 determines.

VOUT

VIN

4_ 4_ 8 8

8

4

_ 4

_ 8

With R120 k, the circuit in Figure 1 is“dead” for input voltages higher than 5V.


F igure 2

80 edn | February 20, 2003 www.ednmag.com

ideasdesign

Many applications require low-frequency signal generators thatcan deliver high-performance,

high-resolution signals. This Design Ideapresents a circuit that generates frequen-cies of 0 to 1 MHz. Sinusoidal, triangular,and square-wave outputs are available.You can achieve frequency resolution ofbetter than 0.1 Hz and phase resolutionof better than 0.1; thus, you can programexact coherent frequencies. This featureis useful in digital modulation and fre-quency-tuning applications. The circuituses the ADC831 and AD9834 to gen-erate the required frequencies (Figure 1).You can program the microcontrollerfrom either a PC or a Unix-based work-station. You then program the AD9834

using a three-wire serial interface via themicrocontroller. The interface word is 16bits long.

You can program the AD9834 to pro-vide sinusoidal, triangular, and square-wave outputs using the DDS (direct-dig-ital-synthesis) architecture. The chipoperates as an NCO (numerically con-trolled oscillator) using an on-chip, 28-bit phase accumulator, sine-coefficientROM, and a 10-bit D/A converter. Youtypically consider sine waves in terms oftheir magnitude form,A(t)sin(t). Theamplitude is nonlinear and is, therefore,difficult to generate. The angular infor-mation, on the other hand, is perfectlylinear. That is, the phase angle rotatesthrough a fixed angle for each unit in

time. Knowing that the phase of a sinewave is linear, and, given a reference in-terval (clock period), you can determinethe phase rotation for that period:Phase dt; Phase/dt2f, andf(Phasef

MCLK)/(2), where dt1/f

M-

CLK ,and f

MCLKis the master clock.

Using this formula, you can generateoutput frequencies, knowing the phaseand master-clock frequency. The phaseaccumulator provides the 28-bit linearphase. The amplitude coefficients of theoutput sine wave are stored in digital for-mat in the sine-coefficient ROM. TheDAC converts the sine wave to the analogdomain. If you bypass the ROM, theAD9834 delivers triangular waveformsinstead of sinusoidal waveforms. A

8052CORE

ADC DAC0

DAC1

REFERENCE

ADM3202

PHASE ACCUMULATOR

FREQUENCYREGULATOR

DAC

32 33

HC49/4H

16 17 48 13

TO PC

7 8

DVDD AVDD

DVDD AVDD

48 13

R1

R4

R3

R2

8

ADC831

OP AMP

1

OP AMP

3

OP AMP

2

R5 1SINE-

COEFFICIENTROM

SERIALINTERFACE

AD9834

5 4

RDRIVE2724

2619

10

9

131415

8

7 18

OSCILLATOR

VDD AGND DGND

RDRIVE

R6

R7

RDRIVE

R8

R9

C119

16

1

11 12


F igure 1

DDS and converter form signal generatorColm Slattery, Analog Devices, Limerick, Ireland

A DDS chip and a microcontroller combine to form a multiwaveform signal generator.


ideasdesign

square-wave output is alsoavailable on the part.Figure 2 shows thevarious waveforms availablefrom the system. As shown inFigure 1, the sinusoidal/ trian-gular output waveforms areavailable on the IOUT pin (Pin19); and the square wave out-put is available on theSIGN_BIT_OUT pin (Pin 16).You program the DDS by writ-ing to the frequency registers.The analog output from thepart is then: f

OUTf

MCLK/228

(frequency-register word).The outputs of the DDS

have 28-bit resolution, so ef-fective frequency steps on theorder of 0.1 Hz are possible toa maximum of approximately1 MHz. Figure 2 shows thetypical waveform outputs. Twophase registers are availablethat allow 12-bit phase resolu-tion. These registers phase-shift the signal by: Phase shift2/4096(phase-registerword).

A 50-MHz crystal oscillatorprovides the reference clock forthe DDS. The output stage ofthe DDS is a current-outputDAC loaded by an external re-sistor. A 200 resistor gener-ates the required peak-to-peakvoltage range. The output isac-coupled through capacitor C

1. The

MicroConverter contains two on-chip,12-bit DACs. DAC

1varies the current

through R5, adjusting the full-scale cur-

rent of the DDS via the FSADJUST pin.The equation to control the full-scalecurrent of the DDS DAC is: I

OUT(full-

scale)18IR5.

DAC0, the internal reference

of the MicroConverter, and opamp 2 allow for offset controlof the output voltage of theDDS. You can program this dcoffset to 10 V at 10-bit reso-lution. When R

1R

2and the

gain of op amp 28, then theoutput of op amp 2 is: V

OUT

(DAC output(VREF

/2))8,yielding a 10V range.

Resistors R6

through R9

al-low for control of gainthrough op amp 3. The gain ofthe op amp is a function of re-sistor switching, which you en-able using the R

DRIVEpin avail-

able on the MicroConverter.This operation allows for aneffective programmable-out-put amplitude of approxi-mately 10V p-p. Thus, thecircuit allows for programma-ble sinusoidal and triangularwaves, including dc offsets,and the ability to set peak-to-peak amplitude of approxi-mately 10V. The squarewave output on the SIGN_BIT_OUT pin has 0 to 5V am-plitude. For low-frequencyoperation, a lowpass filternormally serves to filter refer-ence-clock frequencies, spurs,and other images. For appli-cations in which the outputsignal needs amplification,

you should use a narrowband filter to fil-ter out unwanted noise before the gainstage. A third-order filter would be goodenough to remove most of the unwant-ed noise. Figure 3 shows a typical spec-tral plot of the output. Applications forthis circuit range from signal-waveformgeneration to digital modulation. Youcan use the system in frequency-sweep-ing and -scanning applications and inresonance applications that use the fre-quency as an excitation signal to deter-mine circuit resonance. Another usefulapplication is as a reference oscillator fora PLL system.


Sinusoidal (a), triangular (b), and square-wave (c) waveforms areall available from the circuit in Figure 1. The 500-kHz waveformsall use a 50-MHz sampling rate.

F igure 3

This spectral plot shows the fundamental, second harmonic, and third harmonic for a 3.857-MHz signal.

F igure 2

(a)

(b)

(c)


ideasdesign

Crosspoint switches are ideal foruse in video-security systems, whichaccept multiple camera inputs while

providing playback and multiple loop-through to multiple monitors. To providevideo loop-through or monitor outputs,these systems often require additionalmultiplexer amplifiers that can drivestandard video loads. Thus, one or moreexternal multiplexer amps often follow acrosspoint-matrix switch. As an alterna-tive, you can employ a 3216 nonblock-ing crosspoint-matrix switch, whose 162-to-1 multiplexers eliminate the needfor extra multiplexer amps (Figure 1).The internal 2-to-1 multiplexers appear

before the video-output buffers, whichcan each directly drive a standard videoload. That configuration eliminates theneed for external multiplexer amps andtheir associated cost, space requirement,and power consumption.

The MAX4358 IC is a fully buffered,32-input16-output nonblocking cross-point switch that includes 16 additionalbuffered analog-video inputs (OSDFILL)intended for the insertion of OSD (on-screen-display) information. (“Non-blocking” means that the IC can routeany input to any output.) The 16 fullybuffered OSDFILL analog inputs areidentical to the 32 inputs of the buffered

crosspoint-switch matrix, so the 16 addi-tional video inputs can implement a sin-gle-chip, 48-input16-output cross-point-switch matrix. The output buffersfeature programmable gain (A

V1V/V

or 2V/V). The programmability allowsversatility in routing short video traces ordriving video-transmission lines. Oper-ating from dual 3 to 5V supplies or asingle 5V supply, the device reduces pow-er consumption by as much as 60% ver-sus standard 5V-only ICs.


32-INPUT16-OUTPUT

NONBLOCKINGMATRIXSWITCH

SERIALINTERFACE

C

C

C

C

IN31

IN1

IN0

32 BUFFEREDINPUTS

16 BUFFERED VIDEO-LINE-DRIVING OUTPUTS

MONITOR 0

MONITOR 1

RECORDER

75

75

75

OUT0

OUT1

OUT15

OSDKEY15 OSDKEY1 OSDKEY0

ASYNCHRONOUS 162-TO-1MULTIPLEXER CONTROL

MULTIPLEXER/QUADVIDEO PROCESSOR

OSDFILL15 OSDFILL1 OSDFILL0

MICROPROCESSORCONTROL

16 BUFFERED INPUTS

16 2-TO-1MULTIPLEXERS

MAX4358

F igure 1

48-input16-output crosspoint IC eliminates the need for multiplexer ampsMike Hess, Maxim Integrated Products, Sunnyvale, CA

Internal buffers allow this IC to implement a 48-input16-output matrix switch without the need for external multiplexer amps.



ideasdesign

A13.56-MHz, ISM (industrial, scien-tific, and medical)-band RF-meas-urement device had the test

requirement of a 50-hour, 1-kWburn-in. The device under test needed tobe simultaneously stressed at an RF po-tential and RF current equivalent to 1kW, but the only spare RF source at handwas a 100W RF generator. Besides, sav-ing energy seemed important. The cir-cuit in Figure 1 develops 1 kW from the100W RF source by storing energy in atransmission line. The circuit comprisestwo 43 sections (approximately 6 feet)of RG-213 coaxial cable with UHF con-nectors at each end. The device undertest, which has an electrical length of 4,connects between the two lines, T

1and

T2, making the total line length 90. An

off-the-shelf amateur-radio antenna

tuner matches the 50 RF generator tothe line’s input impedance.

Circuit operation is simple. The RF en-ergy connects to the line’s input throughthe antenna tuner. The energy travels to

the shorted end of the line, where it is re-flected and travels back to the input. Thereflected energy then reflects off the con-jugate match, which the antenna tunerprovides, and combines with the next

RFSOURCE

ANTENNATUNER

4DEVICE UNDER

TEST

T143 LINE

T243 LINE

VOLTAGEMAGNITUDE

CURRENTMAGNITUDE

F igure 1

Transmission line tests 1-kW device using only 100WDavid Cuthbert, Meridian, ID

As if by magic, this setup allows you to apply 1 kW to a device using only a 100W generator.


ideasdesign

half-cycle of input energy to flow towardthe short again. This process continueswith the stored energy continuing tobuild until the circuit losses equal thegenerator power. Considering the circuitoperation in terms of impedances re-minds you that the input impedance ofa shorted, lossless, 90 transmission lineis infinite. At the shorted end of the line,V/I is zero, and, at the input of the line,V/I is infinite. At the center, where the de-vice under test is located, the magnitudeof V/I is equal to the characteristic im-pedance of the transmission line—50in this case. The RF voltage and currentare 90 out of phase, but that fact does notaffect the burn-in of the device.

Consider how much line input power isrequired to develop 1 kW at the device un-der test. The loss of each 6-foot section ofRG-213 is 0.025 dB,and the device-under-test loss is 0.05 dB.The loss for a wave trav-eling down the line is therefore 0.1 dB. Thereturn loss, R

L, is twice this amount, or 0.2

dB,because the wave must travel down theline to the short circuit and return to the

source. Now, you can calculate the reflect-ed power, P

R, for an incident power, P

IN, of

1000W using the following formula:P

R(P

IN)10(RL/10)(1000)10(0.2/10)

955W.So, when 1000W flows down the line,

955W returns to the input. The line inputpower required is equal to the incidentpower minus the reflected power, which is1000955, or 45W. Because the line lossand device-under-test loss are both 0.05dB, half of the 45W loss is dissipated in thecoax, and half is dissipated in the deviceunder test. The measured antenna-tunerloss is 40W, which makes the total circuitloss 85W. You can determine the line’s in-put impedance by calculating the line-in-put complex reflection coefficient () andsolving for the input impedance using10(RL/20)10(0.2/20)0.9772, and

The antenna tuner must match the50 generator’s output impedance to the4.3-k line-input impedance. You canconfirm the circuit’s operation by meas-uring the amplitude and phase of the de-vice’s voltage and current. The measure-ment uses an oscilloscope with voltageand current probes. A power meter at thedevice under test measures forward andreflected power of 1 kW. Because of thehigh circuit Q, you’ll find that adjustingthe RF-source frequency to obtain circuitresonance is easier than trimming cablelengths to obtain circuit resonance. Theprimary limiting factors with this circuitare the temperature rise of the coaxial ca-ble and the losses incurred in the imped-ance-matching circuit. Coax having low-er loss allows you to achieve a higher“power multiplication” and higher de-vice-under-test power.

Is this the best Design Idea in this issue? Vote at www.ednmag.com.

ZZ

INLINE 1

150 0 9772 1

1 0 97724

= + =

+ ≈

( )

( . )

..

ΓΓ

33 kΩ .

www.edn.com March 6, 2003 | edn 117


Some microcontroller applica-tions usually use too many I/O pinsto read keys or onboard switches; in

many cases, few pins remain available forother uses. Some alternative ways to readkeys yield more free pins. First, considersome ways to effect key reading. Table 1presents a comparison of four methodswith references to circuit configurations(figures 1, 2, 3, and 4). As you can see, thebest choice for reading many keys is to

use the A/D converter that is inherent inmany microcontrollers. This optionneeds many lines of code and is notamenable to resistive buttons, such asflexible key pads (Reference 1). Anotheroption is to read one key with one I/Oport, but it needs as many pins as the keysto read.

Figure 4 shows another possibility, thesubject of this Design Idea. In this config-uration, the microcontroller reads six keyswith only three lines of I/O pins. Thismethod entails the use of a few externalcomponents. The idea is to turn one of thethree lines into output, set it at logic 1, anduse the other two lines as inputs. Then, the

microcontroller scans each input for a log-ic 1, and, if it finds it, a key press has oc-curred. If not, it turns the next line intoan output, sets it, and turns the other twointo inputs, and so on. In this way, you canconfirm each time a key press takes place.R

4, R

5, and R

6are current-limiting resis-

tors, and R1, R

2, and R

3are simple pull-

down resistors. The circuit uses threeLEDs for debugging.

Listing 1 shows the complete pro-gram. An MC68HC908JK3 tested thesoftware, but the routine is probably ap-plicable to other microcontrollers. Theprogram has no debounce function; you

1

2

3

4

5

9

10

18

19

16

17

6

7

8

11

12

13

14

15

68HC908JK3

20

PTB7

PTB6

PTB5

PTB4

PTB3

PTB2

PTB1

PTB0

VCC

IRQ1 RST

VSS

OSC1

OSC2/PTA6

VDD

PTD7

PTD6

PTD5

PTD4

PTD3

PTD2

F igure 1

Key-reading circuit saves I/O pinsGustavo Santaolalla, Digital Precision Systems, Buenos Aires, Argentina

vcc

1

2

3

4

5

9

10

18

19

16

17

6

7

8

11

12

13

14

15

68HC908JK3

20

PTB7

PTB6

PTB5

PTB4

PTB3

PTB2

PTB1

PTB0

IRQ1 RST

VSS

OSC1

OSC2/PTA6

VDD

PTD7

PTD6

PTD5

PTD4

PTD3

PTD2

TABLE 1—VARIOUS KEY-READING SCHEMESNo. of keys No. of pins Notes

Figure 1 N No. of pins 16 pins=16 keysFigure 2 N N/8 With ADC, 16 keys=two pinsFigure 3 NINXNOUT NIN+NOUT 16 keys=eight pins (four inputs and four outputs)Figure 4 N N 16 keys=five pins (four more keys available)

In this simple configuration, you need as manyI/O pins as you have keys. Using the microcontroller’s internal ADC, you need only two I/O pins to control 16 keys.

F igure 2

Key-reading circuit saves I/O pins............117

Synchronous buck circuit produces negative voltage ..........................................120

Rotary encoder mates with digital potentiometer ........................124

Amplifiers perform precision divide-by-2 circuit ......................126


(continued on pg 120)

118 edn | March 6, 2003 www.edn.com

ideasdesign

330

20

Y14 MHz

10M

1N4148 1N4148

1N4148 1N4148

1N4148 1N4148

KEY21

KEY13

KEY31

KEY12

KEY32

KEY23

1

2

3

4

5

27 pF27 pF

330

330

LED

LED

LED

VCC5V

VCC

VCC

VCC

R6100

R5100

R4100

R110k

R210k

R310k

0.1 µF

0.1 µF

13

14

15

19

16

17

RST IRQ1

VSSOSC1

OSC2/PTA6VDD

PTB2

PTB1

PTB0

PTB4

PTB3

PTB2

68HC908JK3

1

2

3

4

5

9

10

18

19

16

17

6

7

8

11

12

13

14

15

68HC908JK3

20

PTB7

PTB6

PTB5

PTB4

PTB3

PTB2

PTB1

PTB0

IRQ1 RST

VSS

OSC1

OSC2/PTA6

VDD

PTD7

PTD6

PTD5

PTD4

PTD3

PTD2

In a matrix configuration, you need eight I/O pins to control 16 keys.

With an expansion of this scheme, five I/O lines control 16 keys with room to add four more keys.

F igure 3

F igure 4

120 edn | March 6, 2003

ideasdesign

can add it for a real application. Theprogram shows the variable KeyVal onthree LEDs. You can probably writemore efficient code that that of Listing1; the code shown is just for testing.Table 1 shows how many pins you need

to read 16 keys. As you can see, with thecircuit in Figure 4, you need only fivepins, but you can add four more keys.You can download Listing 1 from theWeb version of this Design Idea atwww.edn.com.

Reference1. Motorola application note AN1775,

www.motorola.com.

LISTING 1—PROGRAM TO READ SIX KEYS AND DISPLAY RESULTS ON SIX LEDs


Many electronic systems requireboth positive and negative voltagesto operate properly. Generating an

efficient, low-voltage positive outputfrom a higher voltage input typically en-tails the use of a synchronous buck reg-ulator. But when generating a negativeoutput voltage from a positive input volt-age, you’d typically use a flyback topolo-gy, especially at higher output currents.The operation and control characteristicsof a synchronous buck and a negative fly-back (also called a buck-boost) differ sig-nificantly. Figure 1 shows the basic com-

ponents that a negative flyback circuit re-quires. When FET Q

1turns on, the input

voltage appears across inductor L1

withno input current going to the load at thispoint. All the output current delivered tothe load at this time comes from outputcapacitor C

1, because diode D

1is reverse-

biased. The current in the inductor con-tinues building until the control circuitdetermines the proper time toswitch off FET Q

1. At that point,

the voltage polarity across inductor L1re-

verses in an attempt to maintain currentflow, pulling the top side of the inductor

+

L1

CONTROL

Q1

C1

VOUTVIN

D1

Synchronous buck circuit produces negative voltageJohn Betten, Texas Instruments, Dallas, TX

This flyback topology produces negative outputvoltage from positive inputs.

F igure 1

www.edn.com



ideasdesign

negative with respect to ground and forc-ing diode D

1to conduct. The output volt-

age goes negative to within a diode dropof the inductor voltage.

The duty cycle at which the control cir-cuit operates also differs from that of asynchronous buck. Although the operat-ing duty cycle of a synchronous buck isDV

OUT/V

IN, the negative flyback oper-

ates at DVOUT

/(VOUT

VIN

). For exam-ple, if the desired output voltage is halfthe input voltage, the synchronous buckruns at 50% duty cycle, whereas the neg-ative flyback runs at 33% duty cycle. Thecomparisons between the simple negativeflyback circuit of Figure 1 and the syn-chronous-buck-controller negative fly-back circuit in Figure 2 are straightfor-ward. In Figure 2, FET Q

2mirrors the

function of diode D1in Figure 1 but with

a decrease in the forward drop that oc-curs in the diode. This lower drop signif-icantly improves efficiency. Diode D

3

conducts during the small dead time,

when both FETs Q1

and Q2

are off, fur-ther reducing losses. The feedback volt-age appears at the output groundthrough resistor R

1, because the control

circuit is referenced to the negative out-put voltage. R

2typically sets the output

voltage to the desired level, because itdoes not change the feedback compensa-tion network, as changing R

1would. De-

sired changes to the input voltage, theoutput voltage, or both may necessitatean inductor-value change. The minimuminductor value is:

Take note of certain limitations withusing the controller in this type of im-plementation. Because the control cir-cuit is referenced to the negative out-put-voltage rail, the controller musthave an input-voltage rating greater

than VIN

|VOUT

|. The controller mustalso be rated for V

IN(minimum), which

occurs at system power-up when theoutput voltage is zero. A controller thatoperates over a wide input-voltagerange typically works best. The FET’sdrain-to-source rating must also with-stand V

IN|V

OUT|, and the FET carries

peak currents that are greater than twicethe output current. Low-resistance, fast-switching FETs produce the lowest loss-es. High efficiency is the major advan-tage of this circuit. Because the circuituses n-channel FETs, as opposed tohigher resistance and costlier p-channelparts, the circuit achieves peak efficien-cies greater than 90%.


IC1TPS5103

1

2

3

4

5

6

20

19

18

17

16

15

7

8

9

10

14

13

12

11

SOFTSTART

INV

FB

CT

RT

GND

REF

COMP

PWM/SKIP

STBY

LH

OUTU

LL

OUTD

OUTGND

TRIP

VCCSENSE

VCC

VREF5

5VIN

FREQUENCY=250 kHz

R211k

R1100k

220pF

20k

0.01F

33 pF

182k

1 F

0.1 F

D1MBR0530

Q1IRF7811

Q2IRF7811

D2MBR0530

D3MBRS340

1 F

0.01F

1 F 1 F

3.24k

3.3

123

123

5678

5678

4

4

47 H

2.2 F35V

470 F35V

2

112VINGND

2

1 GND12VAT 1A

+10 F16V

10 F16V

330 F16V

+

A synchronous buck controller forms the heart of this negative-flyback configuration.

F igure 2

LV V

f I V VMIN

OUT INMAX

MIN OUTMIN OUT INMAX2

2

=+(

( )

))2.


ideasdesign

In developing electronic systems,designers look for products or ideasthat may benefit from the

better performance, smallersize, lower cost, and improved reliabil-ity that an IC can offer. Toward thatend, the digital potentiometer emergedas an alternative to its mechanicalcounterpart, the mechanical poten-tiometer. The digital potentiometer of-fers most of the cited advantages butfalls short for users of mechanical po-tentiometers, who require a simple ro-tary interface for front-panel adjust-ment or calibration without externalcontrollers. The circuit in Figure 1 rep-resents an attempt to combine the bestof both worlds: the simplicity of a ro-tary interface and the performance of adigital potentiometer. The rotary en-coder in this circuit is the RE11CT-V1Y12-EF2CS from Switch Channel(www.switchchannel.com). This type ofrotary encoder has one ground termi-nal, C, and two out-of-phase signals, Aand B (Figure 2). When the rotary en-coder turns clockwise, B leads A (Figure2a), and, when it turns counterclock-wise, A leads B (Figure 2b).

Signals A and B of the rotary en-coder pass through a quadraturedecoder (LS7084 fromLSI Computer Systems,www.lsisci.com), which translatesthe phase difference between A andB of the rotary encoder into acompatible output, CLK and U/D,that the AD5220 can accept. TheAD5220 from Analog Devices(www.analog.com) is a 128- step,pushbutton digital potentiometer.It operates with a negative-edge-triggered clock, CLK, and an in-crement/decrement direction sig-nal, U/D. When B leads A(clockwise), the quadrature de-coder provides the AD5220 with alogic-high U/D. When A leads B(counterclockwise), the quadra-ture decoder provides the AD5220with a logic-low U/D. The quadra-ture decoder also produces a clock

in synchronism with its output, whichalso connects directly to the AD5220.Youlinearly vary the clock’s pulse width byadjusting RBIAS.

Aside from decoding the quadratureoutput of the rotary encoder and pro-viding a clock signal, the LS7084 also fil-ters noise, jitter, and other transient ef-

fects. This feature is important for thistype of application. Unlike optical en-coders, the RE11CT-V1Y12-EF2CS is alow-cost electrical encoder, in whicheach turn can create some bounce ornoise issues because of the imperfectnature of the metal contacts within theswitch. The LS7084 prevents such erro-

neous signals from reaching theAD5220. The operation of thecircuit in Figure 1 is simple.When the rotary encoder turnsclockwise, the resistance fromthe wiper to terminal B1 of thedigital potentiometer, RWB

1,

increments until the devicereaches full scale. Any furtherturning of the knob in the samedirection has no effect on theresistance.

Likewise, a counterclockwiseturn of the knob reduces RWB

1

until it reaches the zero scale,and any further turning of theknob in the same direction hasno effect. One example of theflexibility and performance thiscircuit offers becomes apparentwhen you consider systems withfront-panel rotary adjustment.You can lay out the compactdigital potentiometer and quad-

QUADRATUREDECODER

ROTARYENCODER

B

C

5V

R110k

1

2

3

4

8RBIAS

VDD

VSS

A LS7084

AD5220CLK CLK VDD

U/D

X4/XT

B

7

6

5

1

2

3

4

8

7

6

5

R210k R3

10k

A

DIGITALPOTENTIOMETER

A1

B1

W1

U/D

GND

A1 B1

W1

CSRWB1

F igure 1

Rotary encoder mates with digital potentiometerPeter Khairolomour, Analog Devices, San Jose, CA

A quadrature decoder and a digital potentiometer form a simple rotary-encoder interface.

A

(a)

(b)

CLOCKWISE

COUNTERCLOCKWISE

B

A

B

F igure 2

In clockwise rotation, signal B leads A (a); in counterclock-wise rotation, A leads B (b).


ideasdesign

rature decoder anywhere in the system.All the ICs need are two digital controlsignals routed to the front panel wherethe rotary encoder is located. This set-up proves impervious to interference,

noise, and other transmission-line ef-fects that arise in traditional designswith mechanical potentiometers. Thesedesigns force the sensitive analog signalto travel all the way to the front of the

panel to be processed and then back toits destination.


The classic implementation of avoltage-halving circuit uses twoequal-value resistors. Using 1% re-

sistors provides a divider out-put with 2% accuracy. Formost applications, this performance iscost-effective and more than adequate.However, when you need extreme preci-sion, this approach requires correspond-ingly accurate resistors and can becomeexpensive. Putting feedback around a fi-nite-gain instrumentation amplifieryields a divide-by-2 circuit with theadded benefit of a buffered output (Fig-ure 1). The operation of the circuit isstraightforward. The instrumentationamplifier has unity gain, so the voltage itsees across its inputs appears betweenV

REFand V

OUT: V

OUTV

REFV

IN()

VIN

(). But, considering the circuit inFigure 1, note that V

OUTV

IN(), and

VREF

0. Substituting in the first equa-tion, you obtain V

OUTV

IN()V

OUT,

2VOUT

VIN

(), or VOUT

1/2 VIN

().Thus, you have a divide-by-2 circuit. Oneof the interesting features of this ap-proach is that the input and the output

offsets of the instrumentation amplifierare divided by 2 as well.

You can implement the circuit on thebench using the LT1167 or the LTC2053instrumentation amplifiers (Figure 2).Although benchtests are unnecessary,you can introduce an RC network intothe feedback path for noise shaping andto guarantee dominant-pole behavior. Totest for LT1167 offset, set V

IN() to 0V

and alternate VIN

() between 0V andV

OUT. This test confirms that the feedback

halves the total offset voltage. Dividing10V to 5V, the LT1167 shows an error of100 V. With the more precise LTC2053,the output error in dividing 2.5V to1.25V is an almost-immeasurable 2.5 V.Using cold spray and a heat gun, you can

degrade this error to 15 V. However,perhaps equally important are the calcu-lated worst-case results.

Worst-case calculations for the LT1167show a maximum 1.12-mV error over 0to 70C with 10V input and 5V output.This figure constitutes a total error of 224ppm over temperature. Resistors thatguarantee this accuracy would need amaximum tolerance of 112 ppm eachover temperature. The error budget of aresistor-divider solution would requirean initial ratio match of approximately 50ppm with a temperature-coefficientmatch better than 1 ppm/C. Worst-casecalculations for the LTC2053 with 2.5Vinput and 1.25V output show a maxi-mum 80-V error over 0 to 70C. Thisfigure constitutes a total error of 64 ppmover temperature. Resistors that guaran-tee this accuracy would need a maximumtolerance of 32 ppm each over tempera-ture. The error budget of a resistor-di-vider solution would require an initial ra-tio match of approximately 15 ppm(0.0015%) with a temperature-coeffi-cient match better than 0.25 ppm/C. Ineither case, resistors of this caliber wouldbe extraordinarily expensive if availableat all. Also, the amplifiers provide the ad-ditional benefits of high input impedanceand output buffering. Moreover, the er-ror calculations include the effects of in-put offset voltage, bias current, gain er-ror, and common-mode rejection ratio,which a resistor op amp would still haveto add.

+

–

VIN

VREF

VOUT

VIN(+)

VIN(–)

INSTRUMENTATIONAMPLIFIER

REFERENCE

1 nF

2

18

35 6

4

7+

_

+

_

10 nF REF RG

5V

8

LTC2053

LT1167

VS_

VS+

OUT7

VOUT =VIN/2VOUT =

VIN/2VIN

CHCS

EN

+IN

_IN

1k

2k

3

2

_15V

15V

5 6 4 1

VIN

(a) (b)

F igure 1

F igure 2

Amplifiers perform precision divide-by-2 circuitGlen Brisebois and Jon Munson, Linear Technology Corp, Milpitas, CA

Practical implementations of the circuit in Figure 1 use the LT1167 (a) and the LTC2053 (b).

An instrumentation amplifier makes a simpledivide-by-2 circuit.




Many precision test-and-measure-ment and high-speed analog appli-cations require an exact targeted

voltage to be delivered to the de-vice under test or intended loadto accurately analyze the device. Designand test engineers are well-aware that thisgoal is sometimes unattainable, becausethe impedance across the traces deliveringthe signal to the load alters the original sig-nal. Traditionally, engineers use a Kelvinconnection to measure the accurate volt-age that the load or the device under testsees at its terminals. The Kelvin-connec-tion method enables you to accuratelymeasure the voltage at the load terminal,but it may not correct for the voltage dropor the phase shift that occurs dynamical-ly across the signal lines with various im-pedances. In high-frequency signals, theRLC (transmission-line effects) of thetraces come into play and cause a signifi-cant signal phase shift. As a result, design-ers always look for the least expensivemethods to correct the voltage drop andthe phase shift across the transmissionlines. The circuit in Figure 1 is a fully dif-ferential line driver comprising a fully dif-ferential amplifier and two high-frequen-cy, high-impedance feedback paths.

The resistance associated with eachtrace causes a voltage drop through thepath. Thus, the signal amplitude deliveredto the load is lower than the signal am-plitude at the output of the fully differ-ential line driver. This voltage drop is pro-portional to the resistance value of thetrace, R

TRACE, and the current flow

through the corresponding trace. For ex-ample, if the output current of the linedriver is 100 mA and the trace resistanceis 10, a 1V drop develops acrossR

TRACE. As a result, if the output am-

plitude is 10V p-p, the load sees a 9V p-psignal. The feedback paths, which work assubtracters, accurately measure this volt-age drop. The feedback paths measure the

voltage drop across RTRACE

. This voltagethen adds to the input of the line driverat the summing Node A. Because the cir-cuit is symmetrical, the same function oc-curs at the opposite corresponding points.As a result, regardless of the value of thetotal voltage drop across R

TRACE, the sub-

+

–

+

–

+

–

+

–

+

–+

–

+

–

+

–

13

3

4

66

THS45XX

VOCM

15V

15V

2

1

11

2

2

1

1

2

2

B CRTRACE

RTRACE

2

1 3

3

LOADDEVICEUNDERTEST

3

4

A

F igure 1

Correct voltage drop and phase shift in transmission linesRon Shakery, Texas Instruments, Dallas, TX

This fully differential circuit compensates for voltage drop and phase shift in transmission lines.

10B 1 nH 1 nH

10 nF

C

This circuit represents a simulated transmis-sion line inserted between points A and B ofthe circuit in Figure 1.

F igure 2

Correct voltage drop and phase shift in transmission lines....................................105

Why limit your power supply’s input range? ..................................................106

Virtual-zener circuit simplifies high-voltage interface ................................108

Multilayer capacitor doubles as varactor ....................................................110

Buck regulator and two inductors make dual-polarity converter....................112



ideasdesign

tracter measures it and adds it back intothe input signal of the line driver. Conse-quently, the output of the line driver in-creases by the measure of the voltage dropacross R

TRACE, and the load sees the exact

voltage it was initially intended to see. Be-cause the circuit is a closed-loop systemand has negative feedback, the circuit re-mains in a stable condition.

The buffers in the feedback paths forma high-input-impedance node to preventany load alteration. For example, withoutbuffers, the series and parallel resistors ofthe subtracter would cause the value of theload to vary. These buffers, in conjunctionwith the subtracter, form an instrumenta-tion amplifier. You can adjust this config-uration for different gains to create varia-tions of this circuit for different appli-cations. The instrumentation amplifiercreates a high-input-impedance path thatworks similarly to the sense lines of aKelvin connection. The main difference isthat the sense line in this circuit measuresthe actual voltage drop across R

TRACEover

various frequencies and adds it back to theoriginal signal. You should pay attentionto the ratio of the line driver’s gain con-figuration and the subtracter’s gain con-figuration to ensure stability of the circuit.Additionally, you should verify that thebandwidths of the feedback-path devicesare greater than the bandwidth of the linedriver to prevent any added errors to thesystem via feedback paths’bandwidth lim-itations. You may choose to design thefeedback paths with much greater band-

width than the line driver(two times greater, for ex-ample). Doing so enablesthis circuit to correct thephase shift across thetransmission line if thetraces manifest RCL char-acteristics.

For exam-ple, assume that you inserta transmission-line mod-el between nodes B and Cin the circuit of Figure 1, asin Figure 2. The bandwidthof the fully differential am-plifier is 300 MHz at unitygain, and the input signal is 2V p-p. Thebandwidth of the feedback paths is 600MHz to prevent any added phase shift tothe signal from the feedback circuit. Con-figuring the test circuit as such lets you seethe phase shift that the transmission linealone introduces. The transmission linecauses a significant phase shift in the sig-nal delivered to the load. Figure 3 showsthe phase-shift curves at Node B beforethe transmission line and at Node C afterthe transmission line, right above theload. These curves show the effect of thefeedback path in correcting the phase shiftat the end of the transmission line wherethe load is located. This circuit configu-ration essentially corrects the phase shiftof the signal that the RCL of the trans-mission line causes. The fully differentialline driver enables you to deliver twice thevoltage swing across the load as opposed

to using a single-ended line driver withthe same power supplies and similar spec-ifications. However, the nature of fully dif-ferential configurations requires that youpay close attention to maintaining thebalance of passive and active componentsto preserve the signal integrity deliveredto the load. Therefore, you should setequal resistor values on the top and thebottom feedback paths. This design cancorrect for voltage drop and phase shiftsacross the transmission lines in low- andhigh-frequency cases. Design simplicityand the fact that the design uses few com-ponents make it cost-effective for manyapplications dealing with voltage-correc-tion and phase-shift issues.


PHASESHIFT(˚)

1 Hz 1 kHz 1 MHzFREQUENCY

NODE BWITH FEEDBACK

NODE CWITHOUT

FEEDBACK

NODE CWITH

FEEDBACK

NODE BWITHOUT

FEEDBACK

1 GHz

300

200

100

0

100F igure 3

Taking only a cursory look at theinput-voltage ratings of your power-supply IC can limit the usable input-

voltage range. With careful examinationof an IC’s operating specifications andcircuit topology, you may be able to workaround that input-voltage limitation. Forinstance, The data sheet for TI’s(www.ti.com) TPS61042 shows that ithas all the functions necessary for pro-viding a constant-current drive to awhite-LED circuit; however, the inputvoltage of the IC does not meet the input-

voltage requirements of this Design Idea.The dual lithium-ion input voltage variesfrom 6 to 8.4V, but the TPS61042 input-voltage range is 1.8 to 6V. Closer exami-nation of the circuit shows that the pow-er stage need not connect to the samevoltage rail as the control IC. Figure 1shows that by separating the input volt-age to the TPS61042 from the powerstage, you can power the LED driver froman input voltage greater than 6V.

The IC can receive power from anyavailable system voltage of 1.8 to 6V by

connecting this voltage to the VIN pin.The input to the power stage can now con-nect directly to the battery. In general, thepower stage can connect to any voltagethat is lower than the required output volt-age.With a boost topology, the input volt-age to the power stage must be less thanthe output voltage, or the inductor anddiode pass the input voltage directly to theoutput. The maximum allowable voltageon the SW pin, 28V, also limits the maxi-mum input voltage to the power stage.

This technique also improves system ef-

Why limit your power supply’s input range?Michael Day, Texas Instruments, Dallas, TX

The phase-shift curves at Node B before the transmission lineand at Node C after the transmission line show the effect of thefeedback path in correcting the phase shift at the end of thetransmission line.


ideasdesign

This design for a photonic switchneeds more than approximately 70Vat the cathode of a duo-lateral opti-

cal position-sensing device.This voltage gets speedy re-sponse at longer wavelengths, such as 980nm. The circuit uses fast transimpedanceamps,“floated”at 70V. Two “virtual-zen-er” circuits step down the high-voltagesignals for subsequent processing in aground-referred differential-amplifierstage (Figure 1). The circuit drops ex-actly 65.58V dc with the component val-ues shown, notwithstanding errors aris-ing from op-amp offset voltages andresistor tolerances (Figure 2). The func-tion of the virtual-zener circuit is to pro-vide a regulated, floating dc voltage dropbetween input and output. The size ofthe drop depends on the ratio of R

1to R

2

and the magnitude of the reference volt-age. The input of the circuit, nominallyat 70V dc, draws a constant 3.65 mA. TheTHS3001 sources or sinks this currentplus any additional current as necessary,adjusting the output voltage until thevoltages at its two inputs are equal. Thisequality occurs when V

Z(V

INV

OUT)

VREF

(1R1/R

2).

The op amp’s power-supply rails andoutput range, along with the voltagedrop across R

3, limit the output-voltage

compliance. C1

bypasses R1. This bypass

swamps the bandwidth-reducing effect of

VIRTUALZENER

SHUNTREGULATOR

70V

70V

60V

80V

5V

I TO V

I TO V

1k

1k

1k

10V POWER(EXTERNAL

GROUND-REFERRED)

ANODES(X AXIS)(GND)

CATHODES(X AXIS)(70V)

DIFFERENTIALAMPLIFIER

DIFFERENTIALAMPLIFIER

POSITION-SENSING DEVICE/DUO-LATERAL SENSOR

HIGH-VOLTAGECIRCUITRY

SUMMINGAMPLIFIER

16-BIT, 500k-SAMPLE/SEC ADC



X POSITION

Y POSITION

TOTAL POWER

1k

80V (EXTERNAL POWER)

(GROUND-REFERRED)

VIRTUALZENER

10V POWER"FLOATING"

AT 70V

I TO V

I TO V

F igure 1

Virtual-zener circuit simplifies high-voltage interfacePhilip Lane, Transparent Networks Inc, Bellevue, WA

“Virtual-zener” circuits simplify the high-voltage interface in this position-sensing system.

ficiency. Efficiency data for this circuitshows that higher input voltages providehigher efficiency. If you have to run theLED driver from a voltage that is lowerthan 6V, the power to drive the LED is“double-converted.”It first converts fromthe raw lithium-ion input into an inter-mediate system voltage and then convertsfrom the intermediate-system voltageinto the LED-drive current. By carefullyexamining the operating specs for the IC,you can get around around its input-volt-age limitation, save cost and board space,and increase system efficiency.

WHITEWHITEWHITEWHITE

SYSTEM 3.3V

BREAKTHIS

CONNECTION

DUAL LITHIUM-IONBATTERY6 TO 8.4V

0.1 µF

2.2 µH

1 µF

13.7

ZHCS400IC1TPS61042QFN

1 23 4

8765

9

LEDRESVINFB

SWOVPGND

CTRLPWP

4.7 µF

F igure 1

This circuit provides a way to get around a power-supply IC’s input-voltage limitations.Is this the best Design Idea in this issue? Select at www.edn.com.


ideasdesign

capacitance at the noninverting input,and it greatly reduces the noise at the out-put. Without C

1, the op amp’s inherent

noise would gain up by a factor of(1R

1/R

2). R

4protects IC

1’s noninverting

input by limiting the transient currentsupplied by C

1during power-up and

power-down. R3

and the output, RLOAD

,

have a similar protective effect on the in-verting input, limiting any transient cur-rent in C

2. R

3is necessary to ensure feed-

back stability of the op amp. Theinclusion of this resistor is standard op-erating procedure for a current-feedbackop amp, such as the THS3001. If you usea voltage-feedback type, you could possi-

bly eliminate R3. Bandwidth is extremely

high. Figure 3 shows the pulse responseat 100 nsec per division. (Blue is the in-put, and red is the output.)

+

+

++

IC1THS3001

VIN 1

IC2

C1

R4

2 6

4

735

TRIM GNDTEMPHEAT

IN

332k 100kR1

332k6.8 µF35V

6.8 µF35V

6.8 µF35V

R3

VOUT

RLOAD

150k

25V

_5V

36

7 1

4 8

2

0.047 µF

0.047 µFC2

0.047 µFR2

2.74kD1

1N5240B

1µF250V

OUT

LT1021-5

TP1

2.74k _

+

F igure 2

This virtual-zener circuit provides a regulated, “floating” voltage between the input and output.


CH1 200 mV BW

1

TEK RUN: 500MS/sSAMPLET [ ]

C1 P-P1.000V

CH2 CH1M 100 nSEC _20 mV200 mV BW

The transient response of the circuit in Figure 2is exceedingly fast.

The main purpose for building thecircuit in Figure 1 is to study the idio-syncrasies of X5R, Z5U, and Y5V

multilayer ceramic capacitors. The circuitis also an inexpensive VCO (volt-age-controlled oscillator) withonly five components. Many types of ce-ramic capacitors for surface-mountplacement are on the market. The partsbecome continually smaller because ofspace problems on the board, and the ca-pacitance values continually increase tocompete with more expensive tantalum-electrolytic units. Unfortunately, capaci-tors with X5R, Z5U, or Y5V dielectricshave some undesirable properties. Theyexhibit voltage-dependent capacitancevalues. The idea behind the circuit in Fig-ure 1 is to check the influence of a dc bias

1

2

VBIAS

J1

fOUT

J2

R2100k

R110k

C110 F

C2CERAMIC

1

1

2

2

IC174HC14

F igure 1

Multilayer capacitor doubles as varactorSusanne Nell, Breitenfurt, Austria

This simple oscillator shows the effect of a dc bias on a multilayer capacitor, C2.

F igure 3

voltage on the frequency of a simple os-cillator. The net result is a low-frequen-cy VCO with a relatively large voltage-gain figure, which depends largely on thetype of capacitor you use.

The circuit is a simple oscillator usinga Schmitt-trigger inverter. The frequen-cy is a function of R

1, C

1, and C

2. C

2is the

ceramic capacitor with voltage-depend-ent capacitance. Using the value of C

1,

you can shift the frequency independ-ently of C

2. This design uses a stable-foil-

type capacitor for C1

to avoid bias-volt-age-dependent effects in the measuredresults. If necessary, you can compensatethe temperature coefficient of the ca-pacitor with a combination of NTC,PTC, and metal-film resistors for R

1.

For measurements, this design usesa simple metal-film resistor. The capac-itance change with temperature is nor-mally less than 10% from 10 to 35C forZ5U and Y5V and much lower for X5R.Figure 2 shows the measured voltage-versus-frequency graphs with differentvalues and types for C

2. For Figure 2,

C110 F; the orange curve represents

a 4.7-F, 10V, Z5U multilayer capacitor,and the purple curve represents a 10-F,10V, Z5U multilayer capacitor. Figure 3shows similar plots for values of C

1(or-

ange: 1 F; purple: 10 F). The moral ofthe story is: Be wary when using high-ca-pacitance ceramic capacitors with highor variable dc bias; the varying capaci-tance can greatly influence circuit per-formance.

ideasdesign

Acommon problem for power-sup-ply designers is to create a compact,dual-polarity step-down converter.

If space and cost are not concerns, the ob-vious solution is a pair of dc/dc convert-ers, one for each output. But space andcost are almost always issues for commu-nications, data-acquisition, and disk-drive applications. Figure 1 shows a sin-gle current-control- regulator approachthat supplies 5V at 700 mA and 5V at500 mA from a 12V system source. Thecircuit features efficiency similar to thatof a two-regulator solution and has nocomponent measuring more than3 mm high. The low profile andlow board real estate that this de-sign requires are almost impossible tomatch using a flyback design or a similardual-output SEPIC design using a trans-former instead of two inductors. Note,however, one important limitation of thiscircuit that makes it inappropriate forsome applications: For the circuit tomaintain regulation, the positive load

must always outweigh the negative load.Figure 2 shows some efficiency curves atvarious positive-output currents.

The dual-polarity output circuit is

similar to that of a typical single-outputpositive buck regulator. The circuit addsa secondary negative output by attachinga coupling capacitor (C

1), a second in-

VIN

SYNC

SHDN

VC GND

BOOSTVSW

VBIAS

FB

0.1 F

220 pF

3300 pF

2.2k

CDRH4D28-150

LT1956EFEIC1

2.2 F50V CERAMIC

VIN

9 TO 16V36V TRANSIENT

4.99k

15.4k

D1

10 F6.3V

0805 CERAMIC X5R

B0540W

L2CDRH4D28-150

VOUT2

VOUT1

D3B0540W

5V500 mA

10 F6.3V

0805 X5R CERAMIC

10 F6.3V

0805 X5R CERAMIC

L1

D21N4148


5V700 mA

C1

C2

Buck regulator and two inductors make dual-polarity converterKeith Szolusha, Linear Technology Corp, Milpitas, CA

This dual-polarity dc/dc converter uses a single-switch buck regulator.

F igure 1


fOUT(Hz)

VBIAS (V)

200

150

100

50

00 5 10

4.7 µF

10 µF

15

10 µF

1 µF

fOUT(Hz)

VBIAS (V)

2000

1500

1000

500

00 5 10 15

F igure 2

F igure 3

The frequency of the oscillator in Figure 1exhibits almost a 4-to-1 shift for a 4.7-F Z5Umultilayer capacitor.


The value of C1 has little effect on the frequen-cy curves for the circuit in Figure 1.


ideasdesign

ductor (L2), a catch diode (D

3), and an

output capacitor (C2). The negative out-

put voltage maintains regulation basedon the voltage of the coupling capacitor’sremaining constant and equal to the 5Voutput voltage. Current ramps up anddown in the secondary inductor, L

2, with

the same peak-to-peak ripple as that ofthe primary inductor, L

1. The low-im-

pedance path of the coupling capacitorprovides the current to L

2during

the on-time of the switch and in-duces the same voltage across L

2as ap-

pears across L1. The Schottky catch diode,

D3, provides a current path for the in-

ductor during the off-time of the switchand a current path from the coupling ca-pacitor when discharging into the posi-tive output. Current must flow from thecoupling capacitor into L

1during the off-

time of the switch for the capacitor todischarge all the charge gained during theon-time of the switch. This current flow-

ing into the positive inductor during theoff-time takes the place of some of thecurrent that would normally be sourcedfrom the positive catch diode, D

1, reduc-

ing the losses in D1

but increasing thelosses in D

3.

The need for the coupling capacitorto charge and discharge equally creates

0 10077

500

81

82

83

200

78

300

79

400

80(%)

NEGATIVE-OUTPUT (5V) CURRENT (mA)

250-mA POSITIVE-OUTPUT CURRENT




These curves represent efficiency figures for various positive and negative output currents.

F igure 2


ideasdesign

an important limitation of the circuit:To maintain regulation on both outputs,the negative-supply output currentmust always be less than the positive-supply output current (Figure 3). If thenegative-supply output current increas-es enough to equal the positive-supplyoutput current, regardless of how greatthe positive current is, the output volt-age begins to collapse. Also, ifthe negative-supply output cur-rent is too low (below 5 to 25 mA, de-pending on input voltage), the negative-supply voltage can balloon. Withextremely light negative loads, the cou-pling-capacitor discharge current dur-ing switch off-time and the inductorcurrent (L

2) during switch on-time

come only from the negative output ca-pacitor, C

2 (as opposed to both the neg-

ative output capacitor and the negativedc load). Thus, the output capacitorcharges well past its intended voltage

because no negative dc load is availableto discharge the capacitor. If you use thiscircuit in an application in which thenegative output will see light loads, use

a 25-mA preload to maintain regula-tion.Is this the best Design Idea in this issue? Select at www.edn.com.

00

100

100

500

500

200

200

300

300

400

400

600 700

MAXIMUM AVAILABLECURRENT

FROM 5V SUPPLY(mA)

POSITIVE SUPPLY (mA)


This curve gives the maximum available negative-output current as a function of positive-supplycurrent.

F igure 3

www.edn.com April 3, 2003 | edn 65


Many noncontact temperature-measurement systems use infraredsensors, such as thermopiles,

which can detect small amounts of heatradiation. Biomedical ther-mometers that measure thetemperature of an ear or a temple usenoncontact temperature measurement,as do automotive-HVAC systems that ad-just temperature zones based on thebody temperature of passengers. House-hold appliances and industrial processescan also benefit from the use of noncon-tact temperature measurement. Infraredthermometers can measure objects thatmove, rotate, or vibrate, measuring tem-perature levels at which contact probeseither would not work or would have ashortened operating life. Infrared meas-urements do not damage or contaminatethe surface of the item being measured.Thermal conductivity of the object beingmeasured presents no problem, as wouldbe the case with a contact temperature-measurement device. The circuit in Fig-ure 1 provides a design for a high-reso-lution digital thermometer that uses athermopile sensor and a sigma-delta ADC. The design provides high resolu-

tion and response times of approximate-ly 1 msec, and it eliminates the need forhigh-performance, low-noise signal con-ditioning before the ADC.

The high-accuracy, noncontact digitaltemperature measurement system usesthe MLX90247D thermopile fromMelexis (www.melexis.com) and theAD7719 high-resolution, sigma-deltaADC from Analog Devices (www.ana-log.com). The AD7719 provides differ-ential inputs and a programmable-gainamplifier; thus, you can connect it di-rectly to the sensor, allowing the temper-ature-measurement system to providehigh accuracy without the need for pre-

cision signal-conditioning componentspreceding the ADC. The MLX90247Dsensor comprises a thin, micromachinedmembrane embedded with semiconduc-tor thermocouple junctions. The See-beck-coefficient thermocouples generatea dc voltage in response to the tempera-ture differential generated between thehot and the cold junctions. The low ther-mal conductivity of the membrane al-lows absorbed heat to cause a higher tem-perature increase at the center of themembrane than at the edge, thus creat-ing a temperature difference that is con-verted to an electric potential by the ther-moelectric effect in the thermopilejunctions. The MLX90247D also con-

AD7719AIN1

AIN2

REFIN2

REFIN1 ()

REFIN1 ()

AIN5

AIN6

AGND DGND

DIN

DOUT

SCLK

CONTROLLER

DATA OUT

DATA IN

SERIAL CLOCK

REF192/AD780 AVDD DVDD

26k

RSENSE

15k

OUTIR

OUTIR

MLX90247

VSS

EXCITATION VOLTAGE5V

F igure 1

Temperature-measurement schemeuses IR sensor and sigma-delta ADCAlbert O’Grady and Mary McCarthy, Analog Devices, Limerick, Ireland

Using an infrared sensor and a sigma-delta ADC, you can make noncontact temperature measure-ments.

Temperature-measurement schemeuses IR sensor and sigma-delta ADC........65

Automotive link uses single wire ................66

Novel idea implements low-cost keyboard..........................................69

Get more power with a boosted triode ............................................72

Anticipating timer switches before you push the button ........................74


66 edn | April 3, 2003 www.edn.com

ideasdesign

tains a thermistor, allowing you to con-figure a temperature-compensated sys-tem in relative-measurement mode.

The AD7719, a dual-channel, simulta-neously converting ADC with an internalprogrammable-gain amplifier is an idealADC when you use it with theMLX90247D sensor in temperature-measurement applications. The mainchannel is 24 bits wide, and you can con-figure it to accept analog inputs of 20 mVto 2.56V at update rates of 5 to 105 Hz.The auxiliary channel contains a 16-bitADC and accepts full-scale analog inputsof 1.25 or 2.5V with an update rate equalto that of the main channel. The AD7719accepts signals directly from the sensor;the internal programmable-gain ampli-fier eliminates the need for high-accura-

cy, low-noise external-signal condition-ing. The AD7719 simultaneously con-verts both the thermopile and the ther-mistor sensor outputs. The main channelwith its programmable-gain amplifiermonitors the thermopile, and the auxil-iary channel monitors the thermistor.You can use on-chip chopping and cali-bration schemes in optimizing the de-sign. The AD7719 features a flexible se-rial interface for accessing the digital dataand allows direct interface to all con-trollers.

The sensitivity of the thermopile is 42µV/K; thus, it produces an output voltageof 9.78 to 15 mV over the industrial tem-perature range of 40 to 85C, an out-put that the AD7719 can directly meas-ure. The thermistor’s impedance ranges

from 15.207 k at 40C to 38.253 kat 85C with a nominal impedance of26 k at 25C. Again, you can directlymeasure voltages from the thermistor, asFigure 1 indicates. Biomedical ther-mometers generally have a measurementrange of 34 to 42C. In this range, thethermopile’s differential output is 336V. Operating the AD7719 in its 20-mV input range with a 5-Hz update rateallows temperature measurement with aresolution of 0.05C.


In the automotive industry, inwhich the goal is to produce cars withsimpler, lighter wiring looms, any in-

terface that uses just one wire instead oftwo offers a distinct advantage.The circuit in Figure 1 imple-ments a bidirectional link using a singlewire, with the car’s chassis or ground con-ductor providing a negative return path.The microcontroller communicates withthe driver of the car by illuminatingLED

1. The driver communicates by op-

erating switch S1. Detecting the switch

closure requires no current sensing: Thecircuit simply exploits the fact that theforward voltage drop of a properly biasedLED is usually two or three times the V

BE

of a bipolar transistor. Q1, LED

2, and Q

2

form a semiprecision current source. Q3

in the receiver path detects the switch clo-sure. When the microcontroller’s TX pingoes high, Q

2illuminates LED

2and bias-

es Q1on. Q

1sources a constant current to

LED1

via R2

and D1.

LED2constitutes an inexpensive but ef-

fective voltage reference, which imposesa constant voltage across current-settingresistor R

1. Provided that you choose R

3’s

value to suit Q2’s base drive, you can set

the current in LED2

and the voltage

across it to fairly precise and constant val-ues. For example, with R

3430, the

current in LED2

is approximately 10 mAwith 5V at Q

2’s base (TX high). If you use

a device such as the HLMP-1000 forLED

2, its forward voltage remains con-

stant at approximately 1.6V, putting ap-proximately 0.9V across R

1. The resulting

20 mA or so flowing in Q1

provides ade-quate brightness for LED

1and remains

acceptably constant with changes in VB

ortemperature.

With S1 open, R

6biases Q

3on, pulling

the receiver pin, RX, low. RX remains low,regardless of whether LED

1is on. When

the switch closes, the values for R4

and R6

ensure that Q3’s base pulls down to ap-

proximately 150 mV (with VS5V),

thereby turning off Q3

and allowing RXto go high. As long as the switch remainsclosed, RX stays high, whatever the stateof the TX pin. Powering the currentsource directly from the car’s battery volt-age, V

B, rather than from the microcon-

LED1S1 D2

D1

R2

Q1

Q2

MICROCONTROLLER

TX

RX

0V

Q3

R7330k

R6330k

R410k

R3430

R51k

R143

LED2

VB

12V (NOMINAL)

C210 nF

C110 nF

VS5V

(TYPICAL)

REMOTE SWITCH AND INDICATOR LED

CHASSIS OR GROUND CONDUCTOR

F igure 1

Automotive link uses single wireAnthony Smith, Scitech, Biddenham, Bedfordshire, UK

This circuit implements a bidirectional link using a single wire and a ground return.


ideasdesign

troller’s supply, not only relieves the bur-den on the low-voltage regulator, but alsoensures that LED

1receives proper bias,

even with a very low value for VS. Thus,

provided that R3, R

4, and R

6have appro-

priate values, the circuit functions withV

Sas low as 3V or even lower. A further

advantage is that you can replace LED1

with several LEDs connected in series.With V

B12V, the current source has ad-

equate compliance to drive four or fiveLEDs.

R2

is a nonessential component, but itreduces the power consumption in Q

1. D

1

provides positive overvoltage protectionfor the current source, and voltage-sup-pressor D

2can protect against the harm-

ful transients that systems often en-

counter in the harsh automotive envi-ronment. C

2with R

4provides a degree of

noise filtering and has negligible effect onthe switching of Q

3.You may need C

1and

R5

to roll off Q2’s frequency response to

avoid the possibility of high-frequencyoscillation. The transistor types are notcritical; most devices with respectablecurrent gain and adequate power ratingare satisfactory. LED

2provides a triple

function.As well as acting as a voltage ref-erence for the current source, it also pro-vides local indication of the external LEDstatus by illuminating in synchronismwith LED

1. Additionally, it provides

open-circuit (broken-wire) indication byturning off completely (even when TX ishigh) if the connection between D

1and

the external LED breaks—a feature thatmay be useful for troubleshooting pur-poses. In the event of a broken wire, lit-tle collector current flows in Q

1, and its

base-emitter junction shunts LED2; pro-

vided that R1is much smaller than R

3, the

shunt steals LED2’s bias current, thereby

turning it off. Although the circuit wasdeveloped for an automotive product,you could easily adapt it for use in otherapplications in which a simple user in-terface must operate on a single line.


Many applications that use a mi-crocontroller also use a keyboard.If your application uses a

relatively powerful microcon-troller, you can use several free I/O pinsor an unused input with an ADC to ef-fect an easy keyboard connection. But, ifthe microcontroller in your system hastoo few free I/O pins and no on-chipADC, you can be in trouble. However, ifyour system doesn’t require a high-per-formance keyboard, you can solve theproblem by using the circuit in Figure 1.How does it work? At system initializa-tion, the I/O connection is an output, setto logic 0; hence, C is discharged. In read-ing the keyboard, the following steps takeplace:

1. I/O (output) assumes the state log-ic 1, V

OUT.

2. VC

charges to logic 1 (VOUT

) or to avoltage that R

Sand the other resistors de-

termines. (You can set the output I/O tologic 1 by default. In this case, you canomit steps 1 and 2, and the routine be-comes faster. This design uses 0 instead of1 to have an inactive signal on the linewhen the keyboard is not checked.)

3. I/O becomes an input.4. For a duration T

MAX, the microcon-

troller checks the input I/O to see

whether it resets to logic 0.5. If, after T

MAX, the input I/O is still at

logic 1, no button has been activated.6. If within T

MAX, the input I/O resets

to logic 0, the measured time indicatesthe activated buttons.

7. I/O becomes output again and resetsto logic 0 to discharge C.

Several equations describe the opera-tion of the scheme. First, assume someconditions: V

OUTis the voltage of the out-

put I/O at logic 1; VTH

is the threshold forlogic 0 input to the microcontroller; andR

Xis the value of the parallel combina-

tion of RA, R

B, and the other resistors.

Figure 2 shows the timing diagram forthe circuit of Figure 1. You can evaluate

the duration of TX

with the following ex-pression: T

XR

XClog

e(V

C/V

TH). If R

Xis

not negligible with respect to RXMIN

(butthe R

INPUTof the microcontroller greatly

exceeds RX), then

where VOUT

is the voltage at logic 1 on theI/O output. From the last equation, acondition for R

Xis:

Note that, if RA, R

B, and the other re-

I/O

MICROCONTROLLER

KEYBOARD BUTTONS

C

RA

BA BB BC BD

RB RC RD

RS

...

...F igure 1

Novel idea implements low-cost keyboardJean-Jacques Thevenin, Thomson Plasma, Moirans, France

This circuit provides an inexpensive and easy way to read a small keyboard using only one I/O lineof a microcontroller.

T R CV

V

R

RX X eOUT

TH

X

X

≈ • • •log( ++

RS)

,

> •R RV

V VXMIN STH

OUT TH

.


ideasdesign

sistors form an R-2R string, RXMIN

is approximately equal to R

A/2. R

Slimits

the current from the microcontroller and must have a minimum value ofV

OUTMIN/V

OUTMAX. This resistor creates a

delay for charging and discharging C ofapproximately 5R

SC. The following is an

example of a small keyboard with fourbuttons: To choose R

S, I

OUTMAXof the mi-

crocontroller is 25 mA at VOUT

5V, soR

SMIN200. So this design uses

RS220. R

A, R

B, R

C, and R

Dare 1, 2.2,

3.9, and 8.2 k, respectively. You can se-lect values that greatly exceed R

S. In this

case, the effect of RS

is negligible, but youshould then consider the effects of the in-put resistance of the microcontroller.

The duration between two measure-ments is approximately 2 sec (Listing1). With one byte, the maximum dura-tion, T

MAX, is 512 sec (when no button

is pushed). So, time TX

with RXMAX

(inother words, R

D) must be inferior to

TMAX

. Assuming that VTH

is 1.5V (mini-mum), the equation for T

Xbecomes

So, at the beginning of each measure-ment, you must append a delay of522047 nF52 sec to charge C.Figure 3 shows the waveforms at the I/Opin and the returned values with differ-ent button combinations. The powerconsumption of the circuit, with C47nF, V

CC5V, and a keyboard reading

every 30 msec, is approximately 0.04 mW(practically negligible). You can use thisscheme in all applications that don’t re-quire great accuracy or high speed. Youcan download Listing 1 from the Webversion of this Design Idea at www.edn.com.


VTH

VC = VOUT*

TIME

I/O INPUT WITH PUSHED BUTTONS

*IN FACT, IF SOME BUTTONS ARE PUSHED, VC = RX/(RX = RS) . VOUT.

C IN DISCHARGE WITH PUSHED BUTTONS

DURATION TX IF BUTTONS ARE PUSHED

DURATION TMAX IF NO BUTTON IS PUSHED

I/O OUTPUT

C INCHARGE

I/O OUTPUT

The duration, TX, indicates which buttons or combinations thereof youpushed.

F igure 2

These waveforms at the I/O pin and table show the returnedvalue (duration) with different combinations.

F igure 3

LISTING 1—THE DURATION BETWEEN TWO MEASUREMENTS

• CM8200 AAX e

MAXSEC C nF

• •+

< → <

log. ( )

.

5

1 5

8200

8200 220512 53µ


ideasdesign

Even though 6L6 beam-power tubes have beenaround for 66 years, they

are still quite popular for usein electric-guitar amplifiers,and its cousin, the 6CA7(EL34) power pentode, is a fa-vorite among audiophiles.The developers of these tubesdesigned them forpentode-mode op-eration, and they deliver max-imum audio power in thismode. On the other hand,many audiophiles prefer tri-ode-mode operation and, un-til now, had to be content witha 50% reduction in outputpower. This reduction meansthat they require larger pow-er supplies and twice as manyexpensive tubes to obtainpentode power from a triodeamplifier. Figures 1a, 1b, and1c show the 6L6connected as apentode, a true triode, and a“boosted triode,” respectively.The boosted-triode configu-ration allows pentodes to pro-duce pentodelike power while operatingin a true-triode mode. To understand theoperation of the boosted triode, it’s use-ful to review some vacuum-tube theory.

The 6L6 is a beam-power tube and hascathode, control-grid, screen-grid, sup-pressor-grid, and plate electrodes. Thesuppressor grid is actually a virtual sup-

pressor grid provided by twobeam-forming plates, but youcan treat the 6L6 beam-pow-er tube as a pentode. You canthink of a pentode as an n-channel JFET with the fol-lowing electrode functions:

Thermionic cathode:source of electrons (corre-sponds to the JFET source);

Control grid: controls thecathode current; operated ata negative potential relative tothe cathode (corresponds tothe JFET gate);

Screen grid: electrostati-cally screens the control gridfrom the plate, thereby re-ducing the effect that theplate voltage has on the cath-ode current; operates at apositive potential relative tothe cathode;

Suppressor grid: preventssecondary electrons fromleaving the plate and travelingto the screen grid; operates atthe cathode potential; and

Plate: collects the elec-trons (corresponds to the

JFET drain).Figure 2 shows the pentode’s charac-

teristic curves for control-grid voltages of0 to 25V and a screen-grid voltage of

_

+

–32V

47k

6L61 µF

400V 8

_

+

–44V

47k

6L61 µF

400V 8

_

+

–14V

47k

(a) (b) (c)

6L61 µF

400V

250V

100V

8

F igure 1

0

–2.5

–5

–7.5

–10

–12.5

–15

–17.5

–20

–22.5

–25

PLATECURRENT

(mA)

PLATE VOLTAGE (V)

100 200 300 400 500 600 700 800

250

200

150

100

50

00

300

250

200

150

100

50

0

-50

0

10

20

30

40

50

60

70

80

90

PLATECURRENT

(mA)

PLATE VOLTAGE (V)

0 100 200 300 400 500 600 700 800

A pentode (a) can deliver much more power than a triode (b), unless you use a boosted-triode configuration (c).

F igure 2

F igure 3

The load lines for a pentode show that the plate can draw 150 mA at aplate voltage of only 50V.

A pure triode needs 200V plate voltage to draw 150 mA.

Get more power with a boosted triodeDave Cuthbert, Boise, ID


ideasdesign

250V. Note the idealized load line andthat the tube can draw a plate current of150 mA at a plate voltage of only 50V.High voltage gain, high plate impedance,and high output power characterize pen-tode-mode amplification. By connectingthe screen grid directly to the plate, youcan operate the tube in triode mode. Lowvoltage gain and low output impedancecharacterize this mode. Figure 3 showshow the triode curves differ from thepentode curves. The curves representcontrol grid voltages of 0 to 90V. Notethe load line and that, in triode mode, the

plate cannot draw 150 mA at a plate volt-age lower than 200V. This fact greatlylimits amplifier efficiency and power out-put. However, in spite of the limited out-put power, some people still prefer triodemode because they claim it produces asuperior-sounding amplifier.

For the boosted-triode circuit in Fig-ure 1c, you simply add a 100V screen-to-plate power supply (Figure 4) to the stan-dard triode-amplifier circuit. This ad-dition shifts the triode characteristiccurves 100V to the left (Figure 5). Notethe load line and that the plate can nowdraw 150 mA at a plate voltage of only100V, rather than 200V as with the pure-triode-mode circuit. You can obtain sig-nificantly higher power with boosted-tri-ode amplification and still maintain thecharacteristics of triode amplification. InSpice simulations of three single-endedClass A audio amplifiers using Micro-Cap-7 evaluation software (www.spectrum-soft.com), the control-grid bias fora quiescent plate current is 75 mA, andthe ac grid signal is just short of amplifi-er clipping. The transformer ratios pro-vide a plate-load impedance of 5 k forthe pentode and 3 k for both the triodeand the boosted triode. Table 1 details theparameters.

(Editor’s note: This Twilight Zone-wor-thy circuit will be the subject of an up-coming network sitcom, My Big Fat An-ticipating Timer.)

It happens to almost everyone thatan apparatus or system should havebeen turned off a moment ago. The

device in question could be the car heater,the air conditioner, the lights...

This Design Idea offers a solution tothe challenge of turning devices on or off

in the past. In Figure 1, IC2

is a 555-typetimer (preferably CMOS) connected as amonostable one-shot multivibrator. Thepushbutton switch, S

1, triggers IC

2. You

can replace S1

with a transistor or an op-tocoupler, for example. You can connectV

OUTto a relay or a transistor, if needed.

You might need to adjust the values of R4

and R5, depending on the output load

and the characteristics of S1. The inter-

val during which VOUT

remains high is

T1.1RC2. In Figure 1, you replace the

resistor, R, that normally connects to C2

with the circuit inside the dashed line.This circuit comprises a 741 op amp, IC

1,

and three resistors: R1, R

2, and R

3. You

could replace the war-horse 741 with aTL081 if your design needs longer timedelays.

Taking into account the usual op-ampassumptions—equal voltage on both inputs and zero input current—you de-

Anticipating timer switchesbefore you push the buttonJean-Bernard Guiot, DCS AG, Allschwil, Switzerland


TRIAD N-48X 1N40071.5k25W

100V DC120V AC 120V AC 330 F160V

1N5378B

2SC4953+


100V DC40 mA

120V AC 120V AC 22O F250V

(PD=3W)

1N5378B

2SC4953 WITH HEAT SINKOR SIMILAR

+

TABLE 1—PENTODE, TRIODE, AND BOOSTED-TRIODE PARAMETERSDC plate Grid bias Grid swing Output power

Amplifier current (mA) (V) (V) (W)Pentode 75 14 22 11Triode 75 32 64 6Boosted triode 75 44 88 10

F igure 4

F igure 5

A 100V screen-grid power supply transforms a normal triode into a boosted triode.

With a boosted triode, the plate can draw 150 mA with a plate voltage of 100V, versus 200V for a pure triode.


ideasdesign

rive the following expressions:V

OV(R

2R

1)/R

1, and V

O

VR3I

C, where V

Ois the op

amp’s output voltage, V is thevoltage at the noninverting in-put, and I

Cis the current

through R3. I

Cis also the current

that charges C2.

Combining the citedexpressions, you can computethe value of resistor R that theop-amp circuit replaces: RV/I

CR

3R

1/R

2. The timing

interval of this timer is thusT1.1C

2R

3R

1/R

2. Using ap-

propriate values, you can ob-tain long time delays that youcan’t attain with the basic 555circuit. But the real innovationinherent in this circuit is that its outputturns on at a defined time, T, before youpress S

1. To adjust interval T, use a po-

tentiometer for R1. Because the wiper of

the potentiometer connects to the pow-

er supply, adjusting R1

contributes min-imal EMI and other insidious effects tothe op amp’s input. C

1is a power-sup-

ply bypass capacitor, and C3

stabilizes the555’s control voltage. With the values

shown in Figure 1, the interval T is ap-proximately 18 minutes.

IC2555

GND

TRIG

OUT

RESET

VCC

DISCH

THRESH

CTRL

VCC

VOUT

0V

R52.2k

R42.2k

S1 C310 nF

C21 F

C10.1 F/100 F

_

+

IC1741

R2100

R1100k

R31M

V0

V

IC

F igure 1

This innovative timer turns on approximately 18 minutes before you press switch S1.


www.edn.com


The power-up cycle of the supplyvoltage in embedded-system applica-tions is sometimes not a clean event.

This fact holds especially true in battery-operated systems, because the insertionof a battery often causes significant ring-ing or glitching on the supply line (Fig-ure 1). In products with on-off switches,the contact bounce of the switch cancause an unclean power-up. A power-upcycle such as the one in Figure 1 can of-ten cause a processor to enter a brownoutcondition. This condition consti-tutes an errant condition of theprocessor, which requires a reset to takeplace before the processor behaves as ex-pected. The processor is often “lost” or“in the weeds” during a brownout con-dition. Usually, a reset supervisor con-trols the reset line to the processor andthus avoids the brownout condition. Tra-ditional supply-voltage-supervisor cir-cuits hold the processor in reset until thesupply voltage reaches a predeterminedvalue. They also reset the processor if thevoltage dips below the predeterminedvalue. However, the level at which the SVSoperates often does not suit the system.For example, the level may be lower thanthe minimum operating voltage of theprocessor, or it may be higher than thedesired operating voltage of the system.The reset circuit in Figure 2 provides a re-set to the processor based on stabilization

of the supply voltage and not ona predetermined value.

The circuit uses a TLV3491from Texas Instruments(www.ti.com). The com-parator draws approximately 1A and operates from 1.8 to 5.5V,making it well-adapted to battery-operated applications. The inputto the minus terminal is a simpleresistor divider. The resistor val-ues should be relatively high to re-duce the power consumption ofthe circuit. The input to the plusterminal is basically an RC circuit.The RC time constant provides atunable power-up delay. Whenyou apply power or insert a bat-tery, the output of the comparator is low,holding the processor in the reset condi-tion. The plus input of the comparatorbecomes higher than the minus inputonly after the supply voltage stabilizes, re-sulting in a high output state and thus re-leasing the processor for operation. Thestabilization time for the supply voltagedepends on the RC-network componentvalues. Here, the use of low-value resis-tors carries no penalty, because no cur-rent flows through the RC network after

supply stabilization. By selecting R1, C

1,

R2, and R

3, you can guarantee a reliable

reset signal to the processor for a givendV/dt for V

CC. The equations for the volt-

ages at the comparator’s inputs are:

To hold the processor in reset, you

F igure 1

Reset supervisor waits for stable supplyMike Mitchell, Texas Instruments, Dallas, TX

Insertion of a battery supply often results in glitchingand ringing.

+

–

R4

1kR1

150k

R2 46k

TLV3491

RESET

MSP430MICROCONTROLLER

1MR3

C1

0.1 F

1

24

3

F igure 2

This circuit resets a processor based on the stabilization time of the supply voltage.

Reset supervisor waits for stable supply ............................................91

Small circuit forms programmable 4- to 20-mA transmitter ................................92

High-side current sensor monitors negative rail ....................................................96

Transconductance amp gives oscillator reciprocal response......................98


April 17, 2003 | edn 91

V V V eCC CC

t

R C1 1+ =

;

V VC=CC

R

R R3

2 3+.


ideasdesign

need the condition VV. That condi-tion yields:

Solving for t, you obtain

From the last equation, you can calcu-late the amount of time the processor staysin reset. Therefore, as long as the supplyramps to a steady state in a shorter time,you’re guaranteed a reliable reset. The re-verse-biased diode and resistor R

4provide

a faster discharge path for the capacitor.This fast discharge allows the circuit toquickly react to negative glitches in thesupply voltage during normal operation,in which it may be desirable to reset theprocessor. R

4allows you to tune the re-

sponse time of the circuit for any expect-ed supply-voltage glitches. Removal of theresistor yields the fastest response time tosupply-voltage glitches but may result inundesired resets for the processor. The

pullup resistor at the output of thecomparator is necessary becauseof the comparator’s open-drainoutput. The capacitor at the com-parator’s output smoothes any fastswitching the comparatormay encounter.

The current consumption ofthe circuit in Figure 2 is approx-imately 1 A (the current con-sumption of the comparator)plus the current through R

2 and

R3. The circuit costs less than

many dedicated supply-voltagesupervisors. Figure 3 illustratesthe performance of the circuit.Figure 3 is a scope capture of thesame battery insertion of Figure1. The top trace is the supply volt-age; the next trace is the positive input tothe comparator. The negative input to thecomparator is the next trace, and the bot-tom trace is the comparator’s output(connected to the microcontroller’s re-set pin). You can clearly see that the cir-cuit holds the processor in reset until the

supply stabilizes. Thus, the perfomancedepends not on any predefined supply-voltage level, but rather on stabilizationtime.


F igure 3

The circuit in Figure 2 enables the processor wellafter the stabilization of the power-supply voltage.

One of the key challenges in the de-sign of 4- to 20-mA current trans-mitters is the voltage-to-current

conversion stage. Conventional trans-mitters use multiple op amps and tran-sistors to perform the conversion func-tion. These approaches have been aroundfor a long time, but they are usually in-flexible, have poor power efficiency, andhave limited current compliance. An im-proved Howland current pump, on theother hand, can be cost-effective, becauseit addresses the cited problems. In addi-tion, it closely models an ideal currentsource with the potential for nearly infi-nite output impedance. Figure 1 showsthe improved Howland-current-pumptopology, implemented with a high-res-olution DAC, a precision reference, and ahigh-current op amp. Analyzing the cir-cuit in Figure 1 (neglecting the loadingeffects at the output of IC

3), the voltage

at VX

is VX(V

REFD)/2N, where D is the

decimal equivalent of the DAC’s digitalcode and N is the number of bits.

Analyzing nodes VL

and VN, you obtain

Because VN

and VP

are virtually shorted,you obtain

Substituting VN

and VOUT

, IL

becomes

Making R1R

1, R

2R

2, and R

3R

3

simplifies Equation 4 to

According to Equation 5, you can useR

3 to set the circuit’s sensitivity. You can

make R3 as small as necessary to achieve

the desired current and improve the loadrange.As an alternative, you can make theother resistors large to keep the quiescentcurrent low for high power efficiency.The improved Howland current pump isflexible. It offers both current-sink and -source capability. The input voltage atV

Xis polarity-insensitive; you can apply

it to either R1

or R1. You can connect the

load to the supply rail as a high-side load,or you can refer it to a low-side supply orground (Figure 1). Further, one of theprimary advantages of this topology isthat the current pump provides poten-

Small circuit forms programmable4- to 20-mA transmitterAlan Li and Jeritt Kent, Analog Devices, Bellevue, WA

t R< 11 12

2 3

CR

R Rln .

+

CC CC CC

t

R CVR

R RV V e3

2 3

1 1

+> .

IV V

R

V

R RLOUT L L

3 1 2= ′ ′ + ′

.

V V

R

V V

RN X OUT N

1 3

=+R2

.

VR

R RVN L

1

1 2

= ′′ + ′

.

IR R R

RV

R R R R R R R R

R R

L X2 3 1

3

1 2 1 2 1 3 1 3

1 3

= +′

+

′ ′ + ′ ′′

( )/

( ) ( )

(( ).

′ + ′R RVL

1 2

( )/.= +

′• •

IR R R

R

V DL

REFN

2 3 1

3 2(1)

(2)

(3)

(4)

(5)


ideasdesign

tially infinite output impedance, like thatof an ideal current source. However, youmust pay strict attention to resistormatching. You can see the importance ofmatching by examining the circuit’s out-put impedance. If you ground all inputsand apply a test voltage at V

L, you can see

that

Equation 6 shows that, if the resistorsare perfectly matched, Z

OUTis infinite. In-

finite output impedance is a desirablecharacteristic of a current source becausethe resistance of the load does not affectthe current flowing in the load. On theother hand, if the resistors are notmatched, Z

OUTcan be either positive or

negative. Negative ZOUT

causes instabili-ty because of the existence ofa right-half-plane pole in thes-plane domain. Any amountof parasitic capacitance—from poor pc-board layout,op-amp differential capaci-tance, or both—at the invert-ing node of IC

4could cause

instability or worse. Theseparasitics, along withR

1, introduce a zero

into the noise-gain transferfunction, resulting in a slopeof 20 dB per decade. If thenoise-gain transfer functionof the amplifier intersects with

the open-loop response at a slope (rate ofclosure) equal to or greater than 40 dBper decade and the open-loop gain at theintersection exceeds unity, then the cir-cuit is likely to be unstable. The circuitmay ring, show gain peaking, or condi-tionally oscillate after a step function inthe DAC adjustment.

An effective approach to the stabilityproblem is to insert a pole into the noise-gain transfer function by adding a com-pensation capacitor, C

1. This capacitor

creates a pole to keep the rate of closureat 20 dB per decade. Optimum compen-sation occurs when R

1C

PARASITIC R

2C

1.

Because CPARASITIC

is unknown, youshould determine C

1empirically to ob-

tain optimum results. In general, C1

inthe range of some tenths of a picofarad toa few picofarads satisfies compensation

requirements. Note that optimum com-pensation attempts to balance the factthat a small C

1cannot compensate for all

possible causes of oscillation, whereaslarge values of C

1could adversely affect

the settling time of any DAC. Considerthe following design objectives: 16-bitprogrammability, four channels, smallform factor, a maximum ground-referredload of 500 with 10V compliance, 90%minimum efficiency, and 50-mW maxi-mum dissipation from each resistor.

Given the requirements of small formfactor and high precision, the design inFigure 1 uses IC

2, the a 16-bit current-

output AD5544 DAC, with an external opamp instead of a voltage-output DAC.You face some important trade-offs indeciding whether to use a current-outputor a voltage-output DAC. Current-out-

put devices typically cost lessthan voltage-output DACs.The design must convert thecurrent to a voltage to run thecurrent pump, and the exter-nal op amp determines the ac-curacy of this conversion.Thus, you have control of theamount of accuracy as yourapplication requires. Voltage-output DACs generally costmore than current-output de-vices because the current-to-voltage conversion takes placein the package, entailing theinclusion of an op amp. Al-

_

+

IC3AD8512

R1150k

R1150k

R215k

R350

R3´50

C110 pF

RL500

4 TO 20 mA

_

+

IC4AD8512

VOUT

VIN

VREFVREF

VOUT

VL

ILVP

VDD

VXVN

15V15V

_15V

5V

10V

GNDGND

IC2

AD5544

RF

IO V+

V_IO

DIGITAL INPUT

CODE 20 TO 100% FULL SCALE

IC1ADR01

R2´15k

F igure 1

An improved Howland current pump forms the heart of this precision 4- to 20-mA transmitter.

5

4

3

2

1

0

–1

INTEGRALNONLINEARITY

(LSBs)

0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

RL=500Ω.IL=0 TO 20 mA.

CODE (DECIMAL)

25˚C

70˚CF igure 2

Integral-nonlinearity errors from the circuit in Figure 1 don’t exceed 4LSBs at 16-bit resolution.

ZOOUTV t

I t

R R R R

R R R R R R= = ′ ′ + ′

′ + ′ + ′( )

( )

( )

( ) ( ).1 3 1 2

1 2 3 1 2 3

(6)

96 edn | April 17, 2003

ideasdesign

though a voltage-output DAC reducescomponent count in this design, you haveto accept a particular accuracy figurebased on the specifications of the op-ampbuffer inside the DAC. Both approachestypically require an external reference. Inthe end, a current-output approachyields the highest accuracy at compara-ble cost and board space.

Although IC3, which performs the cur-

rent-to-voltage conversion, can be almostany precision op amp using 15V sup-plies, IC

4requires adequate current-driv-

ing capability to handle the maximum20-mA load. The improved Howlandcurrent pump is insensitive to load-re-sistance perturbations. Only IC

4’s supply

voltages limit the compliance voltage. A500 load, for example, can place V

Las

high as 10V at 20-mA load current. Thisscenario sets V

OUTat 11V, requiring the

op amp to swing within 4V of the posi-tive rail. The AD8512 dual op amp candrive 20 mA into a 500 load using15V supplies. However, IC

4’s output-

voltage swing is likely to limit resistiveloads to 500 in this application. Thisdesign uses the 10V ADR01 reference be-cause it is precise and compact.

To minimize the power in the resistors,you start with R

350. R

3 is in the di-

rect load-current path, and it carries justslightly more current than the load, as-suming R

2R

1R

L. At the 20-mA

peak current, the power dissipation is justabove 20 mW. With the limited head-room between the supply and the com-pliance voltages, you should scale the ra-tio between R

2and R

3such that the

additional gain does not saturate IC4. As

a result, you should choose R2

to be 10times smaller than R

1. Using Equation 5

and the resistance-matching criteria, youobtain the following values: R

1R

1150

k; R2R

215 k, and R

3R

350.

It’s desirable to add a 1- to 10-pF capac-itor, C

1, to the negative-feedback path to

avoid possible oscillation arising fromeventual resistor mismatch.

A 16-bit, programmable, 4- to 20-mAcurrent transmitter theoretically has 0.3-A resolution. The actual measured per-formance of the circuit in Figure 1 showsthat the worst-case integral-nonlinearityerror is approximately 4 LSBs. This erroris equivalent to 1.2 A, or 0.006% totalsystem error, well within most systems’requirements. Figure 2 shows the meas-ured results at 25 and 70C.


All dedicated current-sense ampli-fiers provide high-side sensing on apositive supply, but you can adapt

such circuits for monitoring a negativesupply (Figure 1). The positive-supplypin,V, connects to the system’s positivesupply, and the ground pin, GND, con-nects to the negative supply, V

EE. That

arrangement monitors the negative sup-ply and provides a positive output volt-age for the external interface—typically,an A/D converter. The RS pin of the

current-sense amplifier, IC1, connects to

the load, and the RS pin connects to thenegative supply. IC

1’s current-source out-

put drives a current that is proportionalto load current flowing to ground, not tothe GND pin. Output resistor R

OUTcon-

verts the current to a voltage, which anoptional ADC then digitizes.

Saturation in the internal transistors,which occurs at approximately ((V)1.2V), limits the maximum output volt-age. Thus, V must exceed the full-scale

output by at least 1.2V. If, for instance,the full-scale output is 1V, thenV2.2V. To meet the device’s maxi-mum and minimum operating voltages,0V

EE(32V), and ((V)

VEE

))3V. Figure 2 shows the variationof current measurement accuracy withload current.

_

+

_

+

LOAD

A/D CONVERTER

VEE

–(32V–V+) TO –1V

V+

2.2 TO 5V

2

5

1

6

8

ROUT

RS0.2

GND

RS– RS+

V+

OUT

IC1MAX4172

0

–1

–2

–3

–4

–5

SENSINGERROR(%)

0 0.2 0.4

RS=0.2Ω, ROUT=500Ω,V+=3.3V, VEE= –5V.

LOAD CURRENT (A)0.6 0.8 1

F igure 1 F igure 2

High-side current sensor monitors negative railKen Yang, Maxim Integrated Products, Sunnyvale, CA

Connecting this positive-supply monitor allows it to monitor a negative currentand generate a positive output voltage for the ADC.


The current-sensing error of the circuit in Figure 1 varies withload current.

www.edn.com

www.edn.com

ideasdesign

The circuit in Figure 1 is a variationon the familiar integrator/compara-tor triangle-wave oscillator, which

you typically implement with two opamps. An integrator and a comparatorconnect in a positive-feedback loop; thecomparator drives the integratorand vice versa. A fixed amount ofhysteresis exists in the comparator, pro-ducing a triangle wave at the integrator’soutput. The wave oscillates between thefixed threshold voltages.You can vary theoscillation rate using a potentiometer toset the integrator’s gain and thus obtaina constant-amplitude, variable-frequen-cy, triangle-wave output. In the circuit ofFigure 2, the integrator’s gain is fixed,whereas the comparator’s hysteresis is

variable. An OTA (operational transcon-ductance amplifier), IC

2, sets the hystere-

sis, producing an oscillator in which theperiod is a linear function of an externallyapplied voltage. The oscillation rate is in-versely proportional to the control volt-

age; in other words, the oscillator has a1/x response. Such an oscillator is usefulin A/D-converter applications and forclocking time-delay systems, such as au-dio-delay lines.

In Figure 2, R3

and the 15V outputof comparator IC

3Afix the

integrator current at 20A. The integrator pro-duces a triangle of fixed200V/sec slope, and thepeak amplitude is a func-tion of the hysteresis. OTAIC

2provides voltage con-

trol of the hysteresis. Withincreasing V

IN, the hystere-

sis and triangle-wave peak-to-peak amplitude in-crease, consequently in-creasing the oscillator peri-od, T. The triangle wave’samplitude changes fromapproximately 1 mV p-p toa maximum of 20V p-p asV

INvaries from 0 to 10V.

With the same VIN

span, theperiod increases from 20sec to 200 msec. IC

1and

Q1

form a linear voltage-controlled current sourcethat supplies bias current,I

ABC, to the OTA. The cur-

rent IABC

VIN

/RIN

. You cansee that I

ABCincreases from

0 to 0.5 mA as VIN

variesfrom 0 to 10V. The OTA is aswitched-current genera-tor, producing a bidirec-

_

+

26

3

3

2

5

750kR3

20kR2

R11 R10

CA3280 16

15

15V

R5

1k 1.2MR6

R12

R7

45.3kR4

1k R13

4.7k

IC3A

IC3B

R8

220R9

220

2.2k

6

LM393

LM393

7

BUFFEREDOUTPUT

OFFSETTRIMP2

1OOk–15V 15V

1.5M4.7k

IABC

Q1

R1

IC4

AD843CA3140

P1

RIN=P1+R1=20 k, NOMINAL.

CONTROLVOLTAGE

VIN

0 TO 10V

C1

0.1 F

IC2

IC1

3

2N5087

OP07

6

17.4k5k

FULL-SCALETRIM

15V–15V

15V–15V

15V

13

2

3

1

+

_

+

–

_

+_

+

RATE

INTEGRATOR

HYSTERETICCOMPARATOR

_

+_

+F igure 1

Transconductance amp givesoscillator reciprocal responseMike Irwin, Shawville, PQ, Canada

This circuit is a classic triangle-wave generator, using an integrator and a comparator withhysteresis.

F igure 2

This VCO uses an OTA and a hysteretic comparator to deliver a reciprocal (1/x) response to the control voltage.

98 edn | April 17, 2003


ideasdesign

tional output current approximatelyequal in amplitude to I

ABC, when it re-

ceives drive from the comparator’s open-collector output.

The OTA sources current when thecomparator’s output is 15V and sinks anidentical current when the output is15V. Pullup resistors R

4and R

5, along

with resistors R6

through R9, provide a

symmetrical 70-mV drive to the OTA’snoninverting input. The high-compli-ance output of the OTA provides hys-teresis by translating the voltage at thecomparator’s noninverting input up anddown by the amount R

2I

ABCR

2V

IN/R

IN.

The resulting threshold voltages are sym-metrical around the comparator’s inputoffset voltage. This symmetry reduces theeffect of offset voltage on the oscillator’speriod. This design uses an LM393 com-parator for its relatively low maximumbias current of 25 nA. The comparator’soutput changes state when the integra-tor’s output begins to exceed the thresh-

old voltage set by hysteresis, reversing thedirection of the OTA’s output currentand the threshold polarity. This actionmakes the integrator’s slope reverse andinitiates the next half-cycle.

You can calculate the oscillator’s peri-od as follows:

For the given component values,

Potentiometer P1

sets the full-scale pe-riod for V

IN10V, and P

2nulls the OTA’s

input offset voltage to optimize the per-formance at small values of V

IN. With the

component values shown, the circuit

covers a three-decade range from 200sec to 200 msec with lower than 1%linearity error. The error increases to 2%for T100 sec. With a 10-nF integra-tor capacitor, the circuit oscillates at fre-quencies as high as approximately 150kHz (T6.7 sec). The CA3280 OTAprovides the best performance in thiscircuit, thanks to its excellent offset spec-ifications. Using the CA3080 andLM13600 in the circuit reduces per-formance. The integrator op amp shouldhave low input-bias current and high-speed response to minimize ringing ontriangle peaks. The AD843 and CA3140both work well. You could add temper-ature compensation by including a ther-mistor in the OTA’s input-attenuator cir-cuit. Finally, note that you should usepolystyrene or polypropylene capacitorsin the integrator.


I R C

I

V RABC

INT

IN IN4 42Τ = = ( / )RR C

V RSUPPLY

2

3/.

V k k

V kIN

74 20 20 10

15 7500

( / )( )

/Τ Ω Ω

Ω= =

.. ( ).

( ).

0250

V SEC

RATEV

Hz

IN

IN

=



White-light LEDs are findingtheir way into many markets thatincandescent bulbs once served.

Flashlights are among the newer applica-tions in which reliability, ruggedness, andability to control the power draw of theLEDs make these devices attractive. Withincandescent bulbs, the power manage-ment for the device is a simple on-offswitch. However, the LEDs cannot oper-ate directly from the two cells you typi-

cally find in most flash-lights, because their re-quired voltage is 2.8 to4V, compared with abattery voltage of 1.8 to3V. The power manage-ment has a further com-plication because thelight output of the LEDrelates to cur-rent, and theLED’s characteristics areextremely nonlinearwith voltage. One ap-proach to this problemis to boost the power supply with a cur-rent limit. A number of devices for LEDapplications are available; however, theircurrent ratings are typically too low forthe 1 to 5W that flashlight applicationsneed.

Figure 1 presents an alternative to thetypical boost power regulator. A buck-converter IC, IC

1, generates the higher

voltage that the white-light LED needs.An internal buck power stage connectsbetween VIN and PGND, sourcing cur-rent to output Pin L. This circuit operates

by turning on the high switch, therebyconnecting the battery voltage across in-ductor L

1. Once inductor L

1stores suffi-

cient energy, the high-side switch turnsoff. The inductor current drives theswitching node negative, and energytransfers through the low side into out-put capacitor C

1, creating an essentially

lossless switching event. Also, because thehigh- and low-side switches are MOS-FETs, voltage drop is lower than that of adiode implementation; therefore, effi-ciency can be high. The converter IC

Buck IC boosts battery voltage for white LEDRobert Kollman, Texas Instruments, Dallas, TX

VIN

FC

GND

PG

PGND

L

EN

SYNC

ILIM

IC1TPS6200X

FB

10

9

8

7

6

1

2

3

4

5

0.1 F

1 F

+

C110 F16V

100

2.7 2.7

OPEN175 mA.

SHORT350 mA.

12

BP1BH2AAPCL1

10 H

1 2

10 F16V

Edn030220di31771Heather

10k

F igure 1

A buck-converter IC is a good choice for boosting voltages for white-LED drive.

100

95

90

85

80

75

70

65

60

EFFICIENCYAT 350 mA

(%)

1.5 2 2.5

NO CURRENT SENSE

CURRENT SENSE

INPUT VOLTAGE (V)

3 3.5

Resistive current sensing has an adverse effect on the efficien-cy of the circuit in Figure 1.

F igure 2

Buck IC boosts battery voltage for white LED ..................................................63

Switched-capacitor IC and reference form elegant 48 to10V converter ....64

Buck converter handles battery-backup system..................................66

Circuit disconnects load from low-voltage supply ..............................68

Circuit forms gamma-photon detector ....70

Circuit ensures safety in power-on operation ..................................72



ideasdesign

monitors the current through the LEDvia a current-sense resistor and comparesthe current-sense voltage with an inter-nal 0.45V reference within the converterIC to achieve regulation. Current and,therefore, illumination are functions ofthe current-sense resistor voltage. Al-though the internal reference voltage ofthe IC is lower than that of most otherICs, it does cause an appreciable powerloss. With the LED voltage of 2.8 to 4V, itdegrades efficiency by 10 to 14%. Reduc-ing the resistor’s value and using an am-plifier to sense the current at a lower volt-age could reduce this loss.

Figure 2 shows load-current regula-tion and boost voltage at a 350-mA cur-

rent setpoint. Efficiency is 80% or bet-ter over the normal battery-voltage rangebut falls as battery voltage drops to end-of-life values. Also, the figure shows theimpact of the resistive-current sensing.At high input voltages, the efficiency ap-proaches 95%, and, at low input voltages,it falls to 80%. The trend for the curvesstems from two interrelated effects: Athigh input voltage, input current and,hence, switch current are low. Therefore,conduction and switching losses are low.Second, much like an autotransformer,the boost power stage does not handle thetotal output power. The amount of pow-er that the power stage handles relates tothe boost voltage, or the difference be-

tween the input voltage and the LED volt-age. In this design, the LED voltage is ap-proximately 3.7V, so that at high line of3.2V, the power stage handles only 13%((3.73.2)/3.7) of the power. At low line,in which the currents are much higher,the power stage handles almost fourtimes as much, or 50%, of the power. Al-though a buck controller is not an obvi-ous choice for this application, it provideslow-cost, low-input-voltage operationand good efficiency over a wide input-voltage variation.



Asystem designer must almost al-ways face a trade-off in choosing theright part for an applica-

tion. The trade-off usually in-volves performance, price, and function.An example is the issue of powering cir-cuits from a telecom-voltage source. Tele-com systems almost exclusively use high-potential negative rails, such as 48V.Digital circuits typically in use in such ap-plications usually operate from a “brick”-type power supply. However, analog cir-cuits rarely require enough power tojustify using a costly brick. At the heart ofthese bricks is nothing more than a spe-cialized switching converter in tandemwith an isolated flyback-transformer coil.But some applications neither require norcan tolerate the use of a coil-based ap-proach. Figure 1 depicts a way to addressthe problem. The circuit provides a smallamount of power to analog/digital cir-cuits, such as the LMH6672 DSL op amp.

The LMV431 voltage reference, alongwith the voltage-setting resistors sets theoutput voltage to approximately (11k/280)1.24V5.7V. This outputvoltage then goes to the base of Q

1, the

2N2222 transistor. The configuration ofthe transistor causes a V

BEdrop of ap-

proximately 0.7V, resulting in a net volt-

age of 5V for the next stage.The purposeof the transistor is to provide additionalcurrent to the LM2682 switched-capaci-tor converter. Note that the converter hasa 5V reference (GND pin). Small ca-pacitors C

1and C

2enable the pumping

and inverting action required to convertthe 5V to 10V. Furthermore, the MSO-8 package of the LM2682 and the SOT-23-

3 package of the LMV431 allow the circuitto consume little board space. In roughlythe size of a small transformer, the pro-posed circuit does an elegant job of pow-ering low-power circuits from a negativehigh-voltage source.

R2

1k

R3

10k

R1

280

LMV431 3.3 F

FUSE

INPUT –48V OUTPUT 10V

LM2682

VOUT

GND C1–

C1+

C2–

C2+

C13.3 uF

Q1N2222

C23.3 uF

VIN

F igure 1

Switched-capacitor IC and reference form elegant 48 to 10V converterWallace Ly, National Semiconductor, Santa Clara, CA

This simple circuit provides a 10V power source from 48V telecom power rails.


ideasdesign

Asynchronous buck converter is in-herently bidirectional. That is, ittransfers energy from input to out-

put as a buck regulator when the outputvoltage is low, but, when the output volt-age is high, the converter acts as a boostregulator, transferring power from out-put to input. This Design Idea shows howto use this bidirectional energy transferto automatically recharge a battery whenthe main 5V supply is available in a bat-tery-backed 5V system. The circuit inFigure 1 provides as much as 7A current

at 5V output set at 4.8V and recharges a12V sealed lead-acid battery with a cur-rent as high as 2A. The basic concept isthat the ITH-pin voltage of the LTC3778controls the L

1inductor current, or the

valley level. Above approximately 0.7V atthe ITH pin, the net inductor current ispositive from input to output. Below thatlevel, the inductor current becomes in-creasingly negative, resulting in a boostfunction that transfers energy from out-put to input. When the FCB pin of theLTC3778 is high, the IC inhibits negative

inductor current and the boost functionby turning off the bottom MOSFET.

Figure 2 shows a 5V power supplybacked up by a battery-powered, LTC-3778-controlled power supply. The syn-chronous, bidirectional LTC3778 buckcircuit acts as a battery-to-5V converterif the main 5V supply is off and as a bat-tery charger when the 5V supply is alive.As Figure 1 shows, in the charging mode,the circuit regulates the battery currentby sensing the charge current through R

1

by means of an LT1787 current-sense

0.1 F 0.1 F

0.1 F

1 F

1 F

4.7 F

VIN

IC4

VOUT

LT1460GCZ

LTC1639

13.7k

12

13+–

+

–

+

–

1M

100k 100k

100k

100100k

100k0.068 F

24.9k

14 6

5

IC3D

IC3BIC3C

+

–IC3A

LTC16397

LTC16398

9

LTC1639110

75 pF

1N4148

24.9k

22 pF

383

1.1k

2

3

23.2k

ICI

LTC3778EFRUN/SS

VON

PGOOD

VRNG

ITH

FCB

SGND

ION

VFB

EXTVCC

BOOST

TG

SW

SENSE+

SENSE–

PGND

BG

DRVCC

INTVCC

VIN

330k

1 nF

0.01 F

0.01 F

12.1k

200

4.75k

1k

38.3k

Vin

5VOUT

INTVCC

5VOUT

SHDWN– CMDSH1

0.22 F

10.005

GND

Q2

Q1

B340

+

+

10 F25V

7.2 F 8A

470 F 6.3V

(4.8V)5VOUT

1

10k

VBATT

10 F25V

12V

PWR__GOOD

OR1SYSSVP/S

FIL–VS–DNCVEE

FIL+VS+

VBIASVOUT

IC2LT1787 0.01 F

0.01 F +180 F20V

0.02 2W

VIN

CIN1,2

R1

VBATT

51k

100k8.2V

51k

20k

PWR__GOOD

2N3904 Q52N7002

Q62N7002

Q42N7002

Q3

SHDWN–NOTES:Q1 AND Q2: SI488DY.L1 SUMIDA CDEP1304 (H) - 7R2.CIN1 AND CIN2: SANYO 20SP180M.

1 2

3

1M

L1

F igure 1

Buck converter handles battery-backup systemHaresh Patel, Linear Technology Corp, Milpitas, CA

This bidirectional converter automatically recharges a battery when the 5V main supply is active.


ideasdesign

amplifier, IC2. An error ampli-

fier, IC3B

and IC3C

, comparesthe current-sense signal witha reference voltage from theLT1460GCZ, IC

4, and drives

the ITH pin of IC1. When the

ITH-pin voltage falls lowerthan approximately 0.7V, thecircuit forces the average in-ductor current to a neg-ative value, causing re-verse power flow from theoutput to the input of theLTC3778, thereby chargingthe battery. The lower the voltage at theITH pin, the higher the charge current.

At the beginning of the charge cycle,a constant current charges the battery.When the battery voltage reaches 13.8V,IC

3Dpulls the FCB pin of IC

1high, there-

by not allowing Q2

to turn on. So, thecircuit inhibits boost mode regardless ofthe level at the ITH pin. The interrup-tion in charging current causes the bat-tery voltage to drop below 13.2V torestart charging. This action results inpulse charging with the pulse frequen-cy gradually decreasing until the batteryfully charges. In the backup mode, IC

3A

senses the output-voltage drop to 4.8Vand drives the ITH pin to maintain theoutput voltage at 4.8V. The rechargingresumes when the system’s 5V power re-turns and the 5V bus goes higher than4.8V. In this scheme, the main supplyvoltage must be slightly higher than thebackup-supply voltage for properswitchover. Approximately 100 to 200mV should be adequate to prevent un-necessary mode switching attributableto ripple.

If the lower voltage in the backupmode is objectionable, then you can usea power-good signal from the main sup-

ply to change the reference volt-age to the desired value whenthe power-good signal is low.Q

3through Q

6prevent low-bat-

tery discharge by shuttingdown IC

1when the battery

voltage is low and the power-good signal from the main sup-ply is inactive. You could im-plement more sophisticatedcharging algorithms using asystem microcontroller or ana-log circuitry that sets the chargecurrent as a function of battery

voltage. You can implement float charg-ing by reducing the charge current to ap-proximately 100 mA when the battery isnearly fully charged. A gradually taperingcharge current can mimic constant-volt-age charging as a alternative to pulsecharging. The circuit can use a three-cell(in series) lithium-ion battery if you setthe maximum voltage to 12.6V.

LTC3778

5V

LOAD LOAD

AC

POWER GOOD

5V BUS

F igure 2

The battery charges when the 5V main supply is alive and provides5V power when the main supply goes down.


Power supplies often in-clude a circuit that discon-nects the load when the sup-

ply voltage drops too low, such aswhen a battery is nearlydischarged. A p-chan-nel MOSFET connected betweensupply and load is the typical ap-proach. However, a 1.5V single-cell battery or other low-voltagesupply is insufficient to fully turnon the MOSFET. For such low-voltage systems, consider the cir-cuit of Figure 1. A small invert-ing charge pump, IC

1, generates a

negative voltage approximatelyequal to the input supply, V

CC.

That voltage connects to the ground ter-minal of a microprocessor supervisor,IC

2, which monitors the voltage differ-

ence between its own VCC

and ground

pins. As long as this difference is greaterthan the supervisor’s internal trip-volt-age threshold, the reset output voltage as-sumes the charge-pump output voltage

of approximately 2VCC

,which provides a gate-sourcevoltage adequate to keep theMOSFET on. When themonitored voltage drops be-low the threshold of the su-pervisor, its reset output goesup to V

CCand turns off the

MOSFET. The supervisor hasa threshold of 2.6V. Becausethe voltage it detects is twicethe supply voltage, this cir-cuit disconnects the loadwhen the supply voltagedrops below 1.3V, making itsuitable for use with a typi-cal 1.5V battery. Other in-

ternal threshold voltages are available.

100k

RESET

2

3

11

OUT

GND

GND43

2 IN

VCC

RL

VGS = 2.7V OR LESS.

5 SHDN6

1 µF

1 µF

1.5V

IC1MAX1697

IC2MAX6327XR26-T

F igure 1

Circuit disconnects load from low-voltage supplySteve Caldwell, Maxim Integrated Products, Chandler, AZ

This low-voltage circuit disconnects the load when the supply voltagedrops below a predetermined threshold of 1.3V in this case.



ideasdesign

The circuit of Fig-ure 1 includes aPIN photodiode

that detects individualphotons of gamma ra-diation. The reversebias on the photodiodesometimes creates a de-pletion region. Whensuch a photon strikesthis depletion region, asmall amount of chargedevelops. This charge isproportional to thephoton’s ener-gy. Four ampli-fiers following the PINphotodiode amplifyand filter the resultingsignal.A final compara-tor distinguishes be-tween the signal andthe noise. Thus, thecomparator’s outputpulses high each time agamma photon withsufficient energy strikesthe photodiode. Small signal levels makethis design an interesting challenge. Thedesign requires very-low-noise circuitrybecause the individual gamma photonsgenerate a small amount of charge andbecause lowering the overall noise levelallows the circuit to detect lower energygamma photons.You must pay special at-tention to the first stage, which is themost noise-critical.

The most critical component is thePIN photodiode, whose selection ofteninvolves conflicting considerations. De-tector sensitivity (the number of photonsdetected for a given radiation field), forexample, depends on the size of the de-pletion region, which in turn depends onthe area of the diode and the reverse biasapplied to the diode. To maximize sensi-tivity, therefore, you should choose alarge-area detector with high reverse bias.Large-area detectors tend to have high ca-pacitance, which increases the noise gainof the circuit. Similarly, a high bias volt-age means high leakage current. Leakagecurrent also generates noise. The circuit

in Figure 1 includes the QSE773 PINphotodiode from Fairchild (www.fairchildsemi.com). Though readily availableand inexpensive, it is probably not theoptimal choice. Certain PIN diodes fromHamamatsu (www.hamamatsu.com) canwork nicely in this application. Choosinga detector with 25- to 50-pF capacitancewith reverse bias applied provides a faircompromise between sensitivity andnoise.

Important considerations for the first-stage op amp include input-voltage noise,input-current noise, and input capaci-tance. Input-current noise is directly inthe signal path, so the op amp shouldkeep that parameter to a minimum.JFET- or CMOS-input op amps are amust. Also, if possible, the op amp’s inputcapacitance should be smaller than thatof the PIN photodiode. If you use a high-quality PIN photodiode and an op ampwith low current noise and pay careful at-tention to design, the limiting factor fornoise should be the first-stage op amp’sinput-voltage noise multiplied by the to-

tal capacitance at the op amp’s invertingnode. That capacitance includes the PIN-photodiode capacitance; the op-amp in-put capacitance; and the feedback capac-itance, C

1. Thus, to minimize circuit

noise, minimize the op amp’s input-volt-age noise. The op amp in this circuit,IC

1A, a MAX4477, well suits this design.

It has negligible input-current noise andlow input-voltage noise of 3.5 to 4.5nV/Hz at the critical frequencies of 10to 200 kHz. Its input capacitance is 10 pF.

R1

and R2

contribute equally to noisebecause they are directly in the signalpath. Resistor-current noise is inverselyproportional to the square root of the re-sistance, so use as large a resistance valueas the circuit can tolerate. Keep in mind,though, that leakage current from thePIN diode and first-stage op amp place apractical limit on how large the resistancecan be. The MAX4477’s maximum leak-age current is only 150 pA, so R

2could

be much larger than the 10 M shown.R

1can also be substantially larger when

the circuit operates with a high-quality

12V

1k

10k

10k

1k

1M

5V

100k

R210M

R110M

IC1AMAX4477 IC1B

MAX4477

C14.7 pF

0.1 F1000 pF

100 pF0.1 F

0.1 F

0.1 F

0.01 F

PINDIODE

–

+–

+

GAMMARADIATION

5V

IC2AMAX4477

100 pF

0.1 F0.01 F–

+

5V

28

36

52

1

4

4

1

18

3

IC3MAX987

0.1 F

–

+

5V

4

5

2

3

7

1k

10k

150k

10k

IC2BMAX4477

0.01 F

100 pF

–

+

6

57

VOUT

TEST POINT 1

F igure 1

Circuit forms gamma-photon detectorBruce Denmark, Maxim Integrated Products, Sunnyvale, CA

When a single gamma photon with sufficient energy strikes the PIN photodiode in this circuit, the output of the com-parator pulses high.


ideasdesign

PIN photodiode. C1

affects thecircuit gain, and smaller valuesbenefit both noise and gain. Usea capacitor with low temperaturecoefficient to avoidgain changes withtemperature. This capacitancevalue also affects the require-ment for gain-bandwidth prod-uct in the op amp. Smaller ca-pacitance values require a highergain-bandwidth product.

To ensure that the circuitmeasures gamma radiation andnot light, cover the PIN photodi-ode with an opaque material. Toblock radiated emission frompower lines, computer monitors,and other extraneous sources, be sure toshield the circuit with a grounded enclo-sure. You can test the circuit by using aninexpensive smoke detector. The ionizingtypes of smoke detectors use americium241, which emits a 60-keV gamma pho-

ton. (The more expensive photoelectricsmoke detectors do not contain americi-um.) A 60-keV gamma is close to the cir-cuit’s noise floor but should be detectable.A graph shows the result of a typical gam-ma strike (Figure 2). The top waveform is

from Test Point 1, and the bot-tom waveform represents thecomparator’s output.A possibleimprovement would be to re-place C

1with a digitally trim-

mable capacitor, such as theMAX1474, which provides thecircuit with digitally program-mable gain. Similarly, replacingthe mechanical potentiometerwith a digital potentiometer,such as the MAX5403 allowsdigital adjustment of the com-parator threshold. Finally, driv-ing the comparator’s nonin-verting input with a referenceinstead of the 5V supply im-proves the comparator’s thresh-

old stability.

F igure 2

These waveforms from the Figure 1 circuit show the signal at TestPoint 1 (top trace) when a gamma photon strikes the PIN photodi-ode, and the resulting comparator output (bottom trace).


STOP M POS: 15.20 SEC CURSOR

CH1 100 mV CH2 5V M 5 SEC CH2 / 1.36V

TYPEVOLTAGE

SOURCECH1

DELTA216 mV

CURSOR 1216 mV

CURSOR 20V

Computers find universaluse in industrial-control sys-tems. During power- and

start-up sequences (booting), theoutputs of such con-trol systems may yielduncontrolled pulses before thesoftware defines the correct sta-tus. If these outputs control thepower-on state of a system, theseuncontrolled pulses could havedramatic consequences. Safetyregulations forbid such erratic be-havior. The circuit in Figure 1 isa cost-effective approach to thespurious-pulse problem. The cir-cuit costs approximately 10 timesless than other available timers. Theopen-collector output of the controllingdevice connects to the reset input of theCD4060 counter, IC

1. You can easily

adapt this circuit to other controller-out-put configurations, such as an optocou-pler. As long as R

1pulls the reset input

high (controller-output off), thecounter’s clock stays disabled and all out-

puts are low. C, R2, and R

3are the timing

components for IC1.With R

2R

310 k

and C0.1 F, the measured clock fre-quency is approximately 360 Hz.

The output of the circuit is Q12. Thereset input must stay low longer thanT(2n1)/f(2048)/3605 sec for theoutput to turn on (n is the output num-ber, 12). Any spurious pulse from the

controller’s output that is short-er than 5 sec has no effect on theoutput of the circuit. Output Q13of the counter turns on after 11sec, Q14 after 23 sec, and so on.The LED, connected to Q7through R

4, flashes during the

timing period. With VCC

12Vand an LED current of 10 mA,R

4(V

CC2)/101 k. For safe-

ty reasons, you can add the opto-coupler, IC

2. If output Q12 of the

counter fails (shorted to VCC

), theoutput turns on only if the con-troller’s output is on. Choose thevalue of R

1depending on the con-

troller’s output and the noise lev-el; in this design, R

110 k. Note that

VCC

should have a maximum value of15V for the CD4060 and 6V for the74HC4060.

IC1CD4060

CONTROLOUTPUT

RESET

LED

Q7

Q12

C2C1C0VCC

0V

R4

R1

R2 R3

R5

IC2

VCC

8

612

1

16 9 10 11

0V

OUTPUTF igure 1

Circuit ensures safety in power-on operationJean-Bernard Guiot, DCS AG, Allschwil, Switzerland

This simple timing circuit ensures that a controller’s spuriouspulses do not affect a system’s start-up operation.


www.edn.com May 1, 2003 | edn 87


In the circuit of Fig-ure 1, the REF01, IC

1, is

a buried-zener-diode-based, precision 10V ref-erence that features mini-mal noise and drift overtemperature. The circuitprovides notonly the 10Voutput of the REF01, butalso a 5V output that aREF02 reference woulddeliver. In addition, thecircuit provides 5V,10V, and an unbalanceddual reference, the sum ofwhose voltages is precisely10V. In addition to theREF01, the circuit uses ahighly precise, unity-gaininverting amplifier, IC

2.

Tables 1 and 2 define theoutput voltages as a func-tion of the jumper con-nections and as a functionof the optional use of aREF02 reference in placeof the REF01. In Figure 1, assume the useof a REF01 reference, and that Point 1

connects to Point 2. (Pin 4 of IC1

con-nects to ground.) IC

2inverts the 10V

output of IC1

to deliver 10V at VOUT2

.Now assume that Point 1 connects to

Point 3. (Pin 4 of IC1

connects to the outputof IC

2). If V

OUT1is at X

volts, VOUT2

assumes alevel of X volts. TheREF01 forces exactly10V between its outputand Pin 4. Therefore,X(X)10, 2X10,and X5V. In thisarrangement, 5V and5V are simultaneous-ly available at V

OUT1and

VOUT2

, respectively. To

obtain precisely 5V atV

OUT2, you must ratio-

match R1

and R2

and alsomatch their temperaturecoefficients. Now assumeR

2/R

1A and Point 1 con-

nects to Point 3. In thiscase, the gain of the in-verting amplifier is A.Therefore, V

OUT1and

VOUT2

deliver unbalancedoutputs, the sum of whichis 10V. You can easily de-rive that V

OUT110/(1A)

and VOUT2

10A/(1A).The flexibility of this

circuit eliminates the needto design and inventoryseveral voltage sources.Moreover, the circuit canserve as a dual reference.The circuit finds applica-tion in D/A convertersneeding external refer-ences, portable instru-ments, digital multime-ters, and A/D converters. It

is advisable to use the ultralow-offset-voltage OP07 or ultralow-noise OP27 forthe inverting amplifier.

_

+

VIN VOUT

GND

IC1

REF01

15V

0.1 F

C20.1 F

7

2

3

R215k

IC26

4

41

15V

R37.5k

3

JUMPERS2

2

0.1 F

15V

C1

VOUT1

VOUT2

C3

R1

15k


6

F igure 1

Supply delivers pin-programmablemultiple referencesV Manoharan, Kochi, India

This pin-configurable voltage reference delivers a variety of positive and nega-tive output voltages.

TABLE 1—AVAILABLE OUTPUT VOLTAGESDevice Jumper VOUT1 VOUT2IC1 connection (V) (V)REF01 1 to 2 10 10REF01 1 to 3 5 5REF02 1 to 2 5 5REF02 1 to 3 2.5 2.5

TABLE 2—UNBALANCED OUTPUT VOLTAGESDeviceIC1 R2/R1 VOUT1 VOUT2

REF01 A 10/(1+A) 10A/(1+A)REF02 A 5/(1+A) 5A/(1+A)

Supply delivers pin-programmable multiple references ........................................87

Design an efficient reset circuit ..................88

One-shot provides frequency discrimination ................................................90

Circuit forms novel floating current source ................................................92

Circuit provides Class D motor control ..................................................96


88 edn | May 1, 2003 www.edn.com

ideasdesign

When you work with micro-processors, you must ensure thatwhen the power-supply voltage

fluctuates to the minimum per-missible level,V

L, that the proces-

sor’s ALU continues to operate normal-ly. Also, when you switch on the powersupply, the ALU must operate normallywhen the supply voltage equals or exceeds

a certain high level,VH. The min-

imum and high levels constitutea hysteresis band (V

HYSTV

HV

L), and

fluctuations in supply voltage within thisband should not perturb the logic oper-ations of the processor (Figure 1). Aproperly designed reset circuit can ensureproper operation of a microprocessor.One requirement of an efficient reset cir-cuit is that it operates properly over theintended temperature range—for exam-

ple, 40 to 85C. Several reset circuitsare available that meet the voltage con-ditions, but the temperature constraintsrender them unsatisfactory. This DesignIdea proposes a small, inexpensive re-set-circuit structure.

The supervisor circuit includes acomparator with hysteresis (Figure 2).The circuit represents a noninvert-ing comparator; the voltage to su-pervise is V

CC. The comparator takes a

sample of VCC

via the R1-R

2voltage di-

vider and compares it with the referencevoltage, V

REF. You obtain V

REF by using a

battery voltage,VBAT

, but VCC

would workas well. The pullup resistor, R

OUT, is nec-

essary to obtain a positive voltage at theoutput, because the comparator’s outputhas an open-collector or open-drainstructure. The following approximateand exact equations are based on selec-tion of V

Hand V

L. (Remember that

VHYST

VHV

L.)

In the approximate equations, you dis-regard R

OUT, because its value is negligi-

V

VH

VL

NOTES:IF t < tA, THEN RESET.IF tB–tA,>tMIN , THEN THE RESET DISAPPEARS.tC: RESET INSTANT APPEARS.

tA tB tC t

F igure 1

Design an efficient reset circuitGuillermo Bosque, Asesoría e Integracion de Tecnologías, Urduliz, Spain

A proper reset signal plays an important role inmicroprocessor operation.

VCC

R1

R2

R3

ROUT

VOUTVBAT

RREF

VREF

_

+

F igure 2

This comparator has built-in hysteresis to pro-vide a reset signal when the supply voltagefalls outside the limit band.

+CRST

RRST

VOUT2

VCC

IC2

VCC

ROUTVOUT1

R3

IC1R2

R1

V

V

VCC

VREF

RREF

VBAT


_

+

_

+F igure 3

This circuit introduces a time constant in the reset function.

ttRST

VRSTEND

VOUT2

VOUT1

t

F igure 4

The reset signal ends after one time constant inthe circuit of Figure 3.

+

IC1

IC2IC3

R4

VOUT3CRST

RRST

VCCVCC

VCCVCC

VOUT2

ROUT

VOUT1

R3

R1

R2

VBAT

RREF

VREF

_

+_

+_

+F igure 5

The additional comparator in Figure 5 switches when the exponential signal reaches VREF.

APPROXIMATEEQUATIONS

EXACTEQUATIONS

R1 =

=

RV

V

R RV V

V

L

REF

L REF

HYST

2

3 2

1

.

.

+R R2 33

2 3 1

1 3

1 32

11

1

R R R

V

V

R R R

R R RR

V

V

H

REF

OUT

OUT

L

REF

=

++ +

=

.

( )

.


ideasdesign

ble compared with that of R3. But

the value of ROUT

affects VL, because

ROUT

and R3

are additive when the com-parator is in the high-impedance (off)state. Choosing values for V

HYSTand V

L

and knowing VREF

, you obtain the following approximations: R

1R

2

(VL/V

REF1), and R

3R

1(V

REF/V

HYST).

Now, you add a timing circuit to the hys-teretic comparator (Figure 3). WhenV

OUT1assumes a low level, V

OUT2switch-

es to a low level and discharges CRST

.When V

OUT1switches high, comparator

IC2switches to its high-impedance state,

and CRST

begins to charge through RRST

.V

OUT2follows an exponential curve and

arrives at a value, VRSTEND

, which signalsthe end of the reset signal (Figure 4).Youcan modify the t

RSTby adjusting the val-

ues of CRST

and RRST

. Now, if you add an-

other comparator, IC3(Figure 5), you ob-

tain the waveforms of Figure 6.The final reset circuit appears in Fig-

ure 7. The circuit has four comparators,one voltage reference, seven resistors, andthree capacitors. To determine the resis-tor values, you can use the followingequations: R

1R

2(V

L/V

REF1), and

R3R

1(V

REF/V

HYST). An appropriate

comparator IC is the quad LM239 (25to 85C) or the LM139 (55 to125C). The voltage reference is the1.2V ICL8069CMSQ (55 to 125C).C

1and C

2stabilize high-frequency fluc-

tuations and have values of 100 nF and 10F, respectively. R

REFhas a value of 50 k,

and R4

and R5

have values of 5 to 100 k,depending on the circuit you wish to con-trol. If you chose V

L4.75V,V

HYST0.1V,

and R210 k, you obtain R

129.6 k

and R3355 k. For timing the reset, you

use the capacitor-charging equation,VV

CC(1et/RRST/CRST).

The final instant of reset occurs whenVV

REF1.2V. Choose 5V for V

CC. The

equation then becomes tRRST-

CRST

ln(1V/VCC

). If you choose t1 secand C

RST10 F, then

You obtain RRST

36.4 k. If CRST

1F, then R

RST364 k. It’s preferable to

have a low value for CRST

because of thelow current in the comparator’s outputtransistor. Solving for R

2, you obtain

R210 k.

+

+

+

R4

R5

R3

RESETMICROPROCESSOR

VCC

VCC

VCC

VCC

5k TO 100k

5k TO 100k

RESET GENERAL

IC3

IC4IC2

IC1

CRST

RRST

VBAT

C2100 F

C1100 F

VREF

RREF

VBAT

R2

R1

_

+

_

+

_

+

_

+

F igure 7

The complete reset circuit can handle microprocessors and other circuitry.

You use a frequency discriminatorto compare one signal frequencywith another one. A functional fea-

ture, retriggering, of a monostable, one-shot 74xx123 multivibrator canyield frequency discrimination.Figure 1 shows a frequency discrimina-tor that determines the relation of input-pulse frequency to a reference frequency.The external components, R

1and C

1, set

the reference frequency. These values de-termine the 74xx123’s reference frequen-

DD

D C IC274LS74

R,S

Q QQ

Q

Q

R310k

5V

1,4

5

6R

C

R/C

13

4

15

14

2

R110k

5V

5V

fIN 2

1

3

IC1

74LS123

3

C15100 pF

R1

10k

F igure 1

One-shot provides frequency discriminationVictor Aksenenka, CSRI Elektropribor, St Petersburg, Russia

This simple circuit can reveal whether an input frequency is above or below a reference frequency.

t

t

VOUT3

VOUT2

VREF

VOUT1

t

tRSTF igure 6

One additional comparator produces a positivesignal at the processor’s reset port.

=

.Rt

CV

V

RST

RSTCC

1

cy as follows: fR1/t

W, and t

WkR

1C

1.

The multiplication factor k depends onC

1’s value and the power-supply voltage.

The rising edge of the input pulse startsthe one-shot, whose output switcheshigh for the interval t

W. The same pulse

edge sets the 74xx174 flip-flop to thesame state as the output ofthe one-shot. If the intervalbetween pulses is longer than t

W, the next

pulse arrives after the one-shot returnsto its initial state. The one-shot’s outputis low, and the rising edge of the inputpulse sets the flip-flop low. The low flip-flop output indicates that the input-pulsefrequency, f

IN, is lower than f

R.

If the interval between input pulses is

shorter than tW

, the next pulse arrives be-fore the one-shot completes its cycle andreturns to its initial state. The one-shot’soutput is high, and the rising edge of theinput pulse sets the flip-flop high. A highflip-flop output indicates that the input-pulse frequency, f

IN, is higher than f

R.

Doubling the circuit in Figure 1 imple-ments frequency discrimination with a“window” characteristic (Figure 2). Twopairs of R and C values determine thelower and upper reference frequencies.

An exclusive-OR circuit takes the outputsof the upper and lower flip-flops. The ex-clusive OR’s output is high when f

INis be-

tween fRL

and fRH

. When fIN

is outside thefrequency band f

RLto f

RHthe exclusive

OR’s output is low. Figure 3 shows the fre-quency-discrimination characteristic.With R and C values as in Figure 2, andthe use of a 74LS123 one-shot, f

RL16

kHz, and fRH

46 kHz. Other types ofone-shots could produce different re-sults.

www.edn.com

ideasdesign

2

1

3

D

D

R

D

C

IC2A74LS74

IC374LS86

Q1

Q3

R,S

fIN 13 2

1

23

5

61,4

34

15

5V

5V 5V

14

R310k

C15100 pF

R110k

R510k

Q

Q

CICIA74LS123

R/C Q

Q

D

C

IC2B74LS74

Q2

R,S

12 9

810,13

11

5V

R610k

Q

Q10

9

11

D

D

R

5

12

7

5V

5V

6

R430k

C25100 pF

R210k

Q

Q

CICIB74LS123

R/C

F igure 2

Doubling the circuit in Figure 1 and using an exclusive-OR circuit results in a window discriminator.

Q3

Q2

Q1

VOUT

fRL fRH fIN

F igure 3

The output of the exclusive-OR circuit in Figure2 is high only when the input frequency isbetween defined limits.

Figure 1 shows a polar-ization circuit applicableto ISFET (ion-sensitive

field-effect-transistor) sensors.ISFETs are solid-state chemicalsensors that measure the pHvalue of a solution in biomed-ical and environmental applica-tions, for example. The circuitin Figure 1 is extremely simple;it sets fixed-bias conditions forISFET sensors (V

DSI

0R

X;

IDS

I0). When a sen-

sor needs characteri-zation, you must modify thebias conditions, thus increasing

the cost and the complexity ofthe bias circuit. The low-costauxiliary module in Figure 2implements a novel, voltage-controlled floating currentsource. The current range cov-ers the interval 0 to 100 A.You implement this module tocontrol the ISFET sensor’s biasvoltage, but you can apply it toany sensor that needs bias of100 A or lower. The floatingcurrent source uses three op-erational amplifiers, all por-tions of a Texas Instruments(www.ti.com) TL084. The cur-

+

–TL082A

+

–TL082B

VCC

RX

VSG

–VCC

2I0

I0

D

S

ISFETSENSOR

REFERENCEELECTRODE

F igure 1

Circuit forms novel floating current sourceS Casans, AE Navarro, and D Ramirez, University of Valencia, Burjassot, Spain

This circuit is a classic configuration for biasing ISFET sensors.

92 edn | May 1, 2003


ideasdesign

_

+

_

+

_

+

_

+

_

+TL084C

TL084B

R

R R

VR1

VR2

VC

R0

R0

RXTL084A

TL082AD

S

TL082B

ISFETSENSOR

REFERENCEELECTRODE

E1

E2

I2VSG

I1

I0

I0

VCC

_ VCC

This novel floating current source represents an improved way to bias ISFET sensors.

F igure 2

rent sources (I0) and the current mirrors

(E1

and E2)use the Burr-Brown

(www.ti.com) REF200. The REF200 hastwo 100-A floating current sources (I

0)

and one current mirror Ei(i1, 2). The

VR1

and VR2

voltages compensate the de-viations arising from the operationalamplifiers’ offset voltages and the resis-tor tolerances. The V

Cvoltage controls

the currents I1

and I2; therefore, in the

circuit in Figure 2, VC

controls the sen-sor bias voltage V

DS.

Figures 3 and 4 show the measured ab-solute errors occurring in the bias currentand voltage, respectively. The main ad-vantages of this current source are that itfloats and that you can connect it to anycircuit without changing its operating

mode, because the currents I1

and I2

arecomplementary. Therefore, if I

1dimin-

ishes, the I2

current increases in the sameproportion, and this action does not af-fect the other currents in the circuit. Inthe ISFET-sensor case, changing I

2via V

C

allows you to vary the bias voltage appliedto the sensor without changing the biascurrent, I

DS.

ERROR(µA)

IDS (µA)

0.1

0

_ 0.1

_ 0.2

_ 0.3

_ 0.40 10 20 30 40 50 60 70 80 90 100

F igure 3

Very small measured errors appear in the ISFET’s bias current.

ERROR(mV)

VDS (V)

1.5

0.5

_ 0.5

_ 1.5

_ 2.5

_ 3.50 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Only a few millivolts of error appear over the full range of VDS.

F igure 4


ideasdesign

Class D audio amplifiers providea dual benefit for battery-poweredportable devices. They enhance bat-

tery life, and they produce much lesspower dissipation than do their linearcousins. Those features make Class D am-plifiers ideal candidates for controllingspeed and direction in small electric mo-tors. The standard applicationcircuit for a Class D audio am-plifier, IC

1, requires only slight modifica-

tions. In place of the usual audio-signalinput is a variable dc voltage that poten-tiometer R

2generates. Resistor R

1biases

the potentiometer to match the inputrange of IC

1. Full-counterclockwise ro-

tation of the potentiometer correspondsto maximum-speed reverse rotation ofthe motor. Midscale on the potentiome-ter corresponds to motor off, and full-clockwise rotation of the potentiometer

produces maximum-speed forward rota-tion in the motor. The characteristics ofa given motor may allow you to eliminatethe amplifier’s output filter, which com-

prises L1, L

2, C

1, and C

2. But, unless the

control circuitry is near the motor,you should include the filter to reduceEMI.

16151413121110 9

12345678

IC1MAX4295

GNDPVCCOUT+PGNDVCCVCMINAOUT

SSPVCCOUT–PGND

GNDFS2FS1

SHDN

R4100k

R3100k

R116.5k

R225k

C31 F

C5100 pF

VCC

GND

15 H

L1

C11 F

15 H

L2

C21 F

C4 1 F

1

3F igure 1

Circuit provides Class D motor controlJohn Guy, Maxim Integrated Products, Sunnyvale, CA

A Class D audio amplifier, IC1, helps implement this simple motor-speed controller.



A915-MHz data-acqui-sition project re-quired a small anten-

na, but the availableantennas lacked the nec-essary characteristics: ef-ficiency, compactness—that is, smaller than astandard 3-in. mono-pole—with adequatebandwidth, and withamenability to modelingby inexpensive NEC-2 an-tenna software. (To learnmore about NEC antennasoftware, go to www.nittany-scientific.com/nec.)The result of this designeffort, called the “Tab”an-tenna for its square shapehas the following characteristics:

a square shape, 1.25 in. per side (0.1wavelengths);

the ability to be constructed in FR-4pc board;

linear polarization; a 2-to-1 VSWR (voltage-standing-

wave-ratio) bandwidth of 46 MHz(5% bandwidth);

the ability to be mounted parallel or

perpendicular to a pc board; enhanced suppression of second-

and third-harmonic radiation; and the ability to be mechanically trim-

mable to resonance.The Tab antenna is a folded monopole

that you miniaturize by forming it intoan inverted L with a downward bend atthe end (Figure 1). You can solder it per-pendicular to a pc board or build it as

part of a pc board and place it at acorner. The folded section trans-forms the 12.5 radiation resist-ance to 50 and provides second-harmonic suppression. Third-har-monic suppression comes from anopen stub near the base of the an-tenna. Detailed NEC-2 modelingexplores the sensitivity to changesin the dimensions and optimizedharmonic suppression. BecauseNEC models wire antennas in a vac-uum and the Tab antenna is built onFR-4, you must incorporate the di-electric properties of the dielectricbetween the antenna elements intothe model.

To incorporate the dielectric

properties, you add pe-riodic RC loads be-tween the transmis-sion-line elements. Theloads are the smallboxes in Figure 2, andeach load comprises a30 resistor in serieswith a 78-fF capacitor.The capacitance ofeach RC load is equalto the difference be-tween the transmis-sion-line capacitancescalculated with FR-4 asthe dielectric and withvacuum as the dielec-tric. You calculate theresistance of each RCload using the pub-

lished FR-4 loss tangent of 0.02. The fol-lowing formulas determine the approxi-mate RC values for the transmission-lineloads:

where D is the conductor spacing and dis the conductor diameter.

0.250.25 IN.

L = 0.570 IN.

L = 0.500 IN.

VIA=0.5 IN.

L = 1.25 IN.

L = 1.25 IN.

GNDGND GND

GND

GND

SIGNALINPUT

F igure 1

Small, 915-MHz antenna beats monopoleDave Cuthbert and Bob Casiano, Micron Technology, Boise, ID

This 915-MHz antenna measures only 1.25 in. sq yet outperforms a standard 3-in.monopole.

The square grids represent loads of 30 in serieswith 78-fF capacitors.

F igure 2Small, 915-MHz antennabeats monopole ............................................73

Digital signal controls sine generator ................................................74

Transmitter accurately transfers voltage input ..................................................76

Absolute-value circuit delivers high bandwidth ..............................................80


Z0 ==

276 210

Er

D

dlog ,

=0

Ct Er

ZPROP VACUUM ._

2R

LOSS TANGENT

fC=

π.


ideasdesign

You calculate the RC load pa-rameters for 915 MHz and placethem every 0.1 in. (approximate-ly 5) along the line. You use thefollowing parameters in the cal-culations:

D62 mils, d20 mils, effective Er (dielectric con-

stant) of FR-43, loss tangent0.02, and t

PROP_VACUUM85 psec/in.

Table 1 shows the effectiveparameters in air and in the FR-4medium. You use iterative model-ing to determine the antenna di-mensions with the following design pa-rameters: The first vertical section and thehorizontal section must be of equallengths, the feedpoint impedance target is50, and the resonant frequency is 915MHz. You meet these design criteria witha simulated antenna height of 1.3 in. anda total element length of 3.3 in. The actu-al element length of 3 in. stems from di-electric loading. You also shorten the ac-tual antenna height to 1.25 in. tocompensate for the impedance increasethat the dielectric loss causes. Note thatthe modified NEC model accounts onlyfor the dielectric between the antenna el-ements.

The folded section, functioning as ashorted 180 transmission line at 1830MHz, provides second-harmonic sup-pression. And, although the optimumpoint for the short circuit is 1.75 in. fromthe feedpoint, you can achieve second-harmonic suppres-sion of 25 dB by plac-ing the short within10% of this point. Thelocation of the shorthas little effect at 915MHz. An open trans-mission line at the feedpoint that is 90 at2745 MHz provides third-harmonic sup-pression. This line creates a near-short cir-

cuit at 2745 MHz and providesharmonic suppression of 15 dBwhen you trim it to within 5% ofthe optimum length. Table 2 com-pares the simulated harmonicsuppression of the Tab antennawith that of a quarter-wavelength

monopole with a 50 sourcedriving both antennas.

The Tab antenna has 20-mil-wide traces on oppositesides of 62-mil FR-4 andmounting pads at three loca-tions to allow soldering theantenna securely to a largerboard. You tune the antennaby trimming the open trans-mission line to provide animpedance minimum at2745 MHz and then trim-ming the antenna elementsto resonance at 915 MHz.Figure 3 shows that the sim-

ulated 2-to-1 VSWR bandwidth is 41MHz, whereas the measured bandwidthis 46 MHz. Note that the required oper-ating band is only 902 to 928 MHz. Theincreased measured bandwidth arisesfrom dielectric losses and indicates that

the radiation efficiency is approximately90%. The large bandwidth of the Tab an-tenna results in low sensitivity to envi-ronmental detuning. This design effortyields an antenna only 40% as tall as astandard quarter-wavelength monopole,yet having excellent radiation efficiency,extended bandwidth, and superior har-monic suppression.

860 880

3.5

3

2.5

2

1.5

1

0.5

0900

FREQUENCY (MHz)

920 940 960

SIMULATED VSWR

MEASURED VSWR

The simulated VSWR figures of the Tab antenna agree closely withthe measured results.

TABLE 2—HARMONIC SUPPRESSION OF QUARTER-WAVELENGTH MONOPOLE AND TAB ANTENNA

Frequency Quarter-wavelength Tab antenna(MHz) monopole (dB) (dB)1830 7 252745 1 15

F igure 3

TABLE 1—ANTENNA PARAMETERS INAIR AND IN FR-4 PC-BOARD MATERIALDielectric Er Z0 () C (fF) RAir 1 219 39/0.1 in. InfiniteFR-4 3 126 117/0.1 in. 30RC load 78 30

The circuit of Figure 1 produces anaccurate, variable-frequency sinewave for use as a general-purpose

reference signal. It includes an eighth-or-der elliptic, switched-capacitor lowpassfilter, IC

3, which uses a 100-

kHz square-wave clock signalthat microcontroller IC

2 generates. (Any

other convenient square-wave source isalso acceptable.) The microcontroller re-ceives its clock signal from a 10-MHz os-cillator module. A voltage supervisor,

IC1MAX809 IC2

AT90S2323

IC3MAX740010-MHz

CRYSTAL

10k1 F

0.1 F0.1 F

10k

10k

IN OUT

SHDN

COM

OSGND

CLK

VOD

VOUT

5V

1

2

4 5

6

8

F igure 1

Digital signal controls sine generatorSimon Bramble, Maxim Integrated Products, UK

By removing harmonics from a square wave, this circuit generates an accurate and adjustable sine-wave output.


ideasdesign

LISTING 1—ASSEMBLY CODE FOR SINE GENERATOR

IC1, ensures correct operation in the

event of a power failure. IC3

sets the fil-ter’s cutoff frequency at one-hundredththe clock frequency.

The eighth-order elliptic filter’s sharproll-off sharply reduces the harmonicamplitudes in a 1-kHz square-wave in-put, thereby producing a nearly perfect

1-kHz sine wave at its output. Using di-vider-chain logic or a processor, you canthen create a digitally adjustable sine-wave source by adjusting the clock andinput frequencies and maintain a ratio of100-to-1 between them. To prevent clip-ping at the positive and negative peaks,attenuate the input signal and superim-

pose it on a dc level of VCC

/2. The resultfor a 5V input is a 2.25V peak-to-peakoutput. Listing 1 shows the assemblycode for the microcontroller this appli-cation uses. You can download the codefrom the Web version of this Design Ideaat www.edn.com.

When you connect remote sen-sors to a central process con-troller, a simple, robust, and com-

monly used interface is the 4- to 20-mAloop. The advantages of this current loopinclude the simplicity of just two twist-ed wires that share both power and sig-nal, the loop’s high noise immuni-ty in harsh environments, and thede facto loop standard within theprocess-control industry. Within this in-terface scheme, a typical 24V battery

TWISTED-PAIRWIRE

LOOP SUPPLY

RLOAD

VLOOP

VLOOP

ROUTVERY

LARGE

FIXED4 mA

0 TO16 mA

RIN

VIN

VIN

VOLTAGEINPUT

VOLTAGE-CONTROLLEDCURRENT SOURCE

F igure 1

Transmitter accurately transfers voltage inputClayton Grantham, National Semiconductor, Tucson, AZ

This ideal 4- to 20-mA current transmitter has one voltage-controlled current source and one fixedcurrent source.


ideasdesign

(loop power source) connects through atwisted-wire pair to a transconductanceamplifier (voltage-to-current converter)that converts a sensor’s—for example, apressure transducer’s—output voltageinto a current that then gets transmittedback through the twisted-wire pair to areceiver (load resistor) at the process-control computer. An important criteri-on in this interface is that the currenttransfer of sensor information must beaccurate. Figure 1 shows the transmitterwith one voltage-controlled currentsource and one fixed-current source.

The fixed-current source is 4 mA, acurrent that constitutes the power sourcefor the transmitter and the sensor elec-tronics. This fixed current source musthave an output impedance greater than20 M to keep the loop current inde-pendent of loop-supply variations. Sim-ilarly, current needs to be independent oftemperature—that is, greater than 100ppm/C—because the transmitter andthe sensor can be in harsh environments.The voltage-controlled current sourcehas the same requirements as the fixed-current source and needs to convert theinput voltage signal linearly into a 0- to16-mA current. Thus, it produces an ide-al transconductance as the two-port net-work representation of a voltage-con-trolled current source. The totalloop-current equation is: Loop cur-rent4 mA(gm)V

IN(for V

IN1.2V,

gm13.3 mmho).The transconductance circuit in Fig-

ure 2 allows you to transmit current (4-to 20-mA loop) with less than 1% totalerror from 40 to 85C and over a 3.2to 40V loop-voltage range. Many IC re-alizations of a current transmitter haveexisted for years, but none operates at theloop voltage of 3.2V. Also, these ICs arebecoming sensor-specific, whereas youcan modify and optimize the circuit inFigure 2 for any sensor electronics orloop-current variation (for example, a 1to 5A loop) at low loop voltage. The to-tal loop current is as follows: Loop cur-rent1.225V(R

11/R

10)/R

3V

IN/R

2. The

circuit discussion starts with the realiza-tion of the fixed current source, I

S. The

fixed 4-mA current all flows through R3.

The servo circuitry, including IC2and IC

3,

senses the 44-mV voltage drop across R3

and keeps it fixed. Note that the groundcurrent of all ICs also flows through R

3;

thus, the 4-mA fixed-current setting in-cludes ground-current errors. The dualop amp, IC

2 , is both an inverting gain

stage and an integrator stage. R10

and R11

set the inverting gain to 27.8V/V. Thenoninverting-integrator components C

1,

C2, R

5, and R

6provide a comparison of the

44 mV across R3

(gained up to 1.225V)to the shunt-reference voltage of IC

3. The

output of IC2A

adjusts the sum of the current though R

4and any ground cur-

rent from IC2, IC

3, and IC

4to a value of

4 mA. IC4

acts as an analog power-on-re-set circuit that holds off the start-up ofservo action until all the ICs have suffi-cient supply voltage. With the divider

ratio of R8

and R9

and the 2.32V option of IC

4, the start-up voltage equates to:

VSTART-UP

2.32V(R8R

9)/R

92.7V.

This start-up value is higher than therated supplies of IC

1and IC

2and lower

than IC5’s regulated output of 3V. R

4lev-

el-shifts the output of IC2A

up from zero.R

7biases IC

3into its specification range

to guarantee 0.1% tolerance and 50-ppm/C temperature coefficient over the40 to 85C range. The circuit discus-sion continues with the realization of thevoltage-controlled current-source. IC

1,

Q1, and R

2 are configured as a voltage-to-

current converter. Thus, for a full-scalerange of 20 mA, 16 mA comes from thevoltage-to-current converter. With themaximum V

INat 1.2V, R

2must be 75 to

produce 16 mA. IC1

must have a com-mon- mode input range that goes beyondits negative supply (less than 44 mV).R

1is optional and prevents an open cir-

cuit on IC1’s input. You can remove R

1,

depending on the output impedance ofany input-sensor electronics. Note that R

1

directly introduces an error in the full-scale loop-current.

At the heart of the circuit discussion isthe realization of an output impedance,R

OUT, greater than 20 M in Figure 1. The

low-dropout regulator, IC5, accomplish-

es this task by subregulating the supply toIC

1and IC

2. The good line regulation of

IC5

keeps the 3V output within 30 mVover the input range of 3.2 to 40V. Addi-tionally, IC

5requires as little as 200 mV

of overhead to properly regulate, and it

_

+

_

+

_

+

VIN VCC

GND

GND

RESET

VLOOP VREG +V

–VLOOP

R11M

Q12SD601A

R275

R311

R5100k

R6100k

R4200

IC2ALMV358

IC4LM3724-

2.32V

IC2BLMV358

IC5LM2936-3V

IC3LM4051-1.225V

R123.6k

4- TO 20-mACURRENT LOOP

R717.8k

R926.7k R10

100kR113.6k

R83.01k

C10.01 µF

C322 µF

C20.01 µF

C40.01 µF

VOLTAGEINPUT

0 TO 1.2V

4

1

1

2

115

2

82

3 3

5

3 1

76

5

1,22

3

–VIN

0 TO16 mA

4 mA

MR

IC1LM7301

F igure 2

This circuit transforms a 0 to 1.2V input voltage to a 4- to 20-mA output range.


ideasdesign

can withstand more than 40V. This cur-rent-transmitter circuit is useful for bothlow-loop-voltage designs, and it’s back-ward-compatible with higher loop-volt-age implementations. Furthermore, IC

5

has reverse-supply and surge protection.Therefore, this circuit does not require anadditional diode within the loop, a com-mon need with other ICs to prevent accidental reverse-wiring damage. TheTO-252-package option simplifies thethermal-design considerations. With a 1-in.-sq-area pad for heat sinking, theworst-case power dissipation calculationwould keep the junction temperaturewithin its rated 150C: T

J85ºC(20

mA)(40V)50ºC/W125ºC.You could increase the V

INrange of the

current-transmitter by scaling R2, as long

as you don’t violate the common-modeinput range of IC

1. IC

1’s V

CMincludes its

positive rail. So, to obtain a higher VCM

,you can increase the voltage option ofIC

5. For example, use the LM2936-5V

and R2 equal to 312.5 for a 0 to 5V in-

put range. This configurationwould also require that the loopsupply be at least 5.2V. Note thatany sensor and other electronicscan and should use the 3V subrailsthat IC

5creates as long as the cur-

rent they demand does not exceed3 mA. The 4-mA fixed-current cir-cuitry adjusts for thecurrent demand. Figure3 shows the total error on proto-type units over temperature.

The total error includes the off-set (4-mA) and full-scale (20-mA)effects on the ideal loop current.The tolerances of R

2, R

3, R

7, and R

8

should be within 0.1% with 50-ppm/ºCtemperature coefficients. With IC

5sub-

regulating the rails of IC1, IC

2, and IC

3,

the power-supply-rejection-ratio errorof these ICs does not generate a signifi-cant error. In like manner, IC

2’s CMRR

(common-mode-rejection-ratio) errordoes not generate a significant error.IC

3’s CMRR error and Q

1’s base-current

error both influence the best nonlinear-ity attainable: less than 0.01%. IC

2’s off-

set error is in series with the 44-mV volt-age across R

3, producing an offset error

of 4 mA. Adjust R3

if you need to nullthis error. Adjust R

2to fine-tune the full-

scale range of 20 mA. The op amp’s off-set-temperature-coefficient error issmall compared with the 1% temper-ature-range budget.

–40 –20 0 20 40 60 80TEMPERATURE (˚C)

0.50

0.25

0.00

–0.25

–0.50

ERROR(% OF 16mA)

F igure 3

On three prototype circuits of Figure 2, the totalerror is well below 1% over temperature at 3.2Vloop voltage.

Most absolute-value circuits havelimited bandwidth and high com-ponent count, and they require

several matched resistors. The circuit inFigure 1 uses three fewer componentsthan most absolute-value circuits re-quire, and only two of the resistors musthave 1% tolerance to obtain 1% accura-cy. This circuit’s output voltage is an ac-curate representation of the absolute val-ue of the input signal, and it is accuratefor input signals containing frequenciesas high as 10 MHz. Another advantage ofthis circuit is that it has a positive-volt-age output, thus saving an analog in-verter in most applications. When the in-put voltage is positive, the negativeoutput voltage of IC

1cuts off the diode,

thereby preventing signal propagationthrough IC

1. Virtually no signal propa-

gates through R2, because the resistor

connects to ac ground through the out-

put of IC2. The only signal path is

through R3

to buffer IC2, and the output

of the buffer is a positive voltage. Whenthe input voltage is negative, the positiveoutput voltage of IC

1forward-biases the

diode, thus providing an ac short circuitfor R

3to ground. IC

2is within IC

1’s feed-

back loop, so the output voltage is posi-tive because of IC

1’s configuration as an

inverting op amp.This design uses a dual op amp to min-

imize parts count. Two op amps ina feedback loop tend to be unsta-ble. Select an op amp that has sufficientphase margin to prevent oscillation whenthe input voltage is negative. The circuit’sdynamic range is from the op amp’s in-put offset voltage to the maximum out-put voltage. This dynamic range is from1 mV to 4.1V for the TLC072 with 5Vpower supplies. The excellent bandwidthperformance results from combining the

high-frequency TLC072 op amp with afast Schottky-barrier diode. You can usehigher frequency op amps to obtain bet-ter bandwidth results, but you must takecare in the op-amp selection to avoid os-cillation or reduced dynamic range.

_

+

_

+

IC1TLC072

IC2TLC072

VOUT

D1

5V

5V

VIN

R110k1%

R210k1%

R35%

SD103CCT-NO

F igure 1

Absolute-value circuit delivers high bandwidthRon Mancini, Texas Instruments, Bushnell, FL

This inexpensive absolute-value circuit has highbandwidth.



With the proliferation ofdual-voltage architec-tures and multiproces-

sor boards, even simple appli-cations can require severalprocessor voltage rails.With each processorhaving its own power-up and -down requirements, power-rail sequencing and control canbecome a complex task. Thechallenge for power-supply de-signers is to consider eachprocessor’s timing and voltagerequirements and assimilatethese into a total system, ensur-ing that the final design meetsthe requirements of all proces-sors.

Failure to properly powerprocessors can lead to problemsthat range from the fairly be-nign, such as a reduction inMTBF, to the catastrophic, suchas latch-up. Given the variety ofavailable processors and the ap-plication challenges you expect when de-veloping a power-sequencing and -con-trol scheme, use of a microcontroller isdesirable because of its programmabili-

ty. The MSP430 is a good fit for such anapplication (Figure 1). The high-per-formance, low-cost 16-bit RISC proces-sor has several high-quality analog pe-ripherals and a JTAG interface.

Controlling power supplies that haveenable pins, such as those on most “brick”dc/dc converters and low-dropout regula-tors, is simply a matter of using a GPIO(general-purpose I/O) line. If the powersupply has no enable function, an inlineswitch, normally a MOSFET, can controlthe power supply, either with a GPIO orPWM signal. The circuit in Figure 1 usesthe TPS725xx family of low-dropout reg-ulators to provide 3.3, 2.5, and 1.8V froman input dc source. These regulators havean enable pin and a reset function.You caneasily expand this circuit to any number of

voltage rails.The MSP430 monitors a con-trol variable to determine when to activateeach rail. For power-sequencing applica-tions, the two most commonly controlledvariables are time and voltage.When timeis the control variable, the controller en-ables the first rail. At a specific time there-after, it enables the next rail. Some time af-ter that, it enables the next rail, and so onuntil it has enabled all rails.

The MSP430 provides the timing-se-quence and the -control signals to turnon the power supplies. If voltage is thecontrol variable, then the controller acti-vates the first voltage rail and monitorsits rise via an ADC. When the first volt-age rail reaches a specific voltage level,the controller enables the next voltagerail and monitors its rise until it reaches

13 PI.1

MSP430FI49

2 4

1 3 5 100k

100k

TO PIN 14MSP450

TO PIN 17

TO PIN 59

1.8V

1 µF

TPS72518

14 PI.2

THREE D CELLS

4.5V

15 PI.3

17 PI.5

18 PI.6

19 PI.7

59 PG.0

60 PG.1

61 PG.2V

100k

SHUTDOWNFOR EXTERNAL

HOST

SYSTEM RESET

12

10

PI.0

PI.4

VIN VOUT

EN GND RESET

100k

2 4

1 3 5 100k

100k

TOPIN 15

TO PIN 18

TO PIN 60

AS CLOSE ASPOSSIBLE TOOUTPUT PIN 4

2.5V

1 µF

TPS72525

VIN VOUT

EN GND RESET

1

10k

2 4

3 5TOPIN 13

TO PIN 19

TO PIN 61

3.3V

1 µF

VIN VOUT

EN GND FB

F igure 1

Microcontroller directs supply sequencing and controlJoe DiBartolomeo, Texas Instruments, Dallas, TX

An ultra-low-power microcontroller controls a system’s power-supply sequencing.

Microcontroller directs supply sequencing and control................................73

Circuit provides leading-edge blanking............................................................74

MOSFETs reduce crosstalk effects on analog switches........................................78

Grounded resistor tunes oscillator ............78

Obtain higher voltagefrom a buck regulator ..................................80



ideasdesign

a specified voltage level. At this point, thecontroller enables the next voltage railand monitors it. This process continuesuntil the controller has enabled all volt-age rails. When using voltage as the con-trol variable, the controller can use eithera GPIO or a PWM signal as the enablesignal, depending on whether the designrequires rail tracking. You can also use a combination of voltage and timing control.

In Figure 1, each low-dropout regula-tor connects to two MSP430 lines—onefor enabling and the other for monitor-ing.When time is the control variable, themonitoring takes place via Port 1 (GPIO);when voltage is the control variable themonitoring occurs via Port 6 (ADC). TheMSP430 also provides a system reset andhas an input for power-down. The codeis fairly simple and does not require muchprogramming experience. When time isthe control variable, the first thing to dois initialize the MSP430 and setup theport and timer; this operation takes fivelines of code (see Listing 1, which is avail-able with the Web version of this DesignIdea at www.edn.com). The next opera-tion is to load the capture-and-compareregister zero (CCR0) with the first timinginterval and start the timer.When CCR0’svalue is equal to the timer’s value, the firstvoltage rail becomes enabled. CCR0 is

then loaded with the next time interval,and the timer resets and restarts. WhenCCR0 is equal to the timer value, the sec-ond voltage rail becomes enabled. Thisoperation repeats until all rails become enabled.

Once all rails are enabled, a delay loopenters the picture to ensure that the resetpins on the low-dropout regulators havetime to come up. The TPS725xx familyhas an open-drain, 100-msec reset func-tion. Once the delay is complete, theMSP430 checks each regulator’s reset lineto ensure that all rails are up. If all rails areup, the MSP430 issues a system reset.When voltage is the control variable, onlyfive lines of code are necessary to initial-ize the MSP430 (Listing 2, which is avail-able with the Web version of this DesignIdea at www.edn.com). The next opera-tion is to load registers R9, R10, and R11with values that represent 3.3, 2.5, and1.8V, based on a 3V ADC reference. Thefirst rail becomes enabled, and its outputvoltage undergoes monitoring until it iswithin specification, at which point thenext rail is enabled and monitored. Thisoperation repeats until all three rails be-come enabled. Once all the rails are en-abled, the delay loop for regulator resetactivates, and the system reset occurs.

Once the MSP430 turns on all the volt-age rails and applies the system reset, it

enters the monitor mode. It continuallychecks the low-dropout regulator’s out-put voltage, via the reset or output pins,depending on whether time or voltage isthe control variable. If a fault occurs, theMSP430 enters an error routine. Themost obvious fault would be the loss ofa voltage rail, but other faults, such asovervoltage and undervoltage, are alsoamenable to monitoring. The actionsthat the error routine takes depend on theapplication. The simplest actions wouldbe to power down all rails, but program-mability gives you complete control. Onefinal function is the powering down ofthe voltage rails. An external signal, like-ly from the main processor, signals theMSP430 to power down the processorrails. In this example the power-down se-quencing is just the opposite of the pow-er-up sequence, but you can define anysequence. One addition to the power-down sequence could be to turn on dum-my loads to discharge the output filtercapacitors. This design uses the TPS-725xx low-dropout regulators becausethey offer fast transient response and sta-bility with any output capacitor. Howev-er, some applications may require largeoutput capacitors to maintain stabilityand transient response. In these cases, theability to discharge these filter capacitorsimproves MTBF.

In isolated switch-mode power sup-plies using peak-current-mode con-trol, generally the current-sense resis-

tor senses the current on the primary sideof the power converter. Figure 1 shows atypical circuit, in which R

2is the current-

sense resistor that monitors the current.The current-sense signal goes to the in-put of the PWM comparator—in thiscase, the PWM comparator’s input(I

SENSE) of the controller IC. R

3and C

1

provide an RC delay in an attempt to re-move some of the leading-edge spikes onthe current-sense signal. Sometimes, theRC delay circuit is insufficient for re-moving the false noise signals at the in-put of the PWM comparator. This DesignIdea shows how to suppress the false trig-gering signals caused by parasitic LC (in-

ductance and capacitance),causing LC tanking andfalse-peak current triggeringto the peak-current-limitcomparator.

The RC delay circuit inFigure 1 works for most ap-plications in suppressingvoltage spikes that may false-ly trip the peak-limit-cur-rent comparator. However,some applications require aleading-edge blanking cir-cuit to suppress falsetriggering. Figure 2shows the typical cur-rent-sense signal that ap-pears across R

2. The leading-

edge spike at time T1

occurs

UCC38517

GATE DRIVE

ISENSE

T1

R1

R3

Q1

R2C1

F igure 1

Circuit provides leading-edge blankingMichael O’Loughlin, Texas Instruments, Dallas, TX

In this classic PWM-controller configuration, R2 is the sendingresistor for the output current.

when the gate drive switches from low tohigh and the parasitic capacitance fromthe gate to the source of Q

1is charging.

Depending on the values of R1

and R2, a

large-enough leading-edge voltage spikecould falsely trigger the PWM compara-tor at the I

SENSEpin. This problem is com-

mon in isolated dc/dc power converters.To remove false triggering from the PWMcomparator, it is desirable to blank out theleading-edge spikes that appear on thecurrent-sense signal. You can suppressthese leading-edge spikes by adding fouradditional components to the circuit inFigure 1. Figure 3 shows the extra cir-

cuitry necessary to provide leading-edgeblanking. The gate drive from the PWMcircuit activates the leading-edge blank-ing circuit. Transistor Q

2suppresses the

leading-edge current-signal spike. Com-ponents R

4, C

2, and R

5set up the amount

of time the leading edge of the current-sense signal is suppressed from the PWMcomparator.

Selecting the components for the lead-ing-edge blanking circuit is simple. Youselect Q

2 with sufficiently low saturation

voltage,VSAT

, to suppress the leading edgeof the current-sense signal. You select R

4

and R5

to drive transistor Q2

into satura-tion. You then select C

2to set up the tim-

ing for the circuit. To select transistor Q2,

the maximum collector-to-emitter volt-age, V

CE, must be less than the gate-drive

voltage. The transistor saturation voltage,V

SAT, must be low enough to suppress the

voltage spike at the PWM comparator’sinput. For most applications, you can getaway with using a 2N2222 transistor.You

must select R3

to providesome current-limitingprotection for transistorQ

2. R

4must supply suffi-

cient base drive, IB, current

to Q2. You select R

5such

that its current is 10% ofthe base-drive cur-rent. You choose thevalue of C

2to keep tran-

sistor Q2

saturated for two RC time con-stants. You can use the following equa-tions to calculate the resistor andcapacitor sizes:

and

where VGATE

is the maximum gate-drivevoltage of the PWM comparator, andT

BLANKis the amount of leading-edge

blanking time required.Another power-supply de-

sign has current-sense spikesso large that the modulewill not regulate. This de-sign requires the implementa-tion of the leading-edgeblanking circuit in Figure 2.The design,a 200-kHz flybackconverter, requires a leading-edge blanking time, T

BLANK,

time of 200 nsec.The leading-edge blanking circuit requiresa maximum base current, I

B,

of 42 mA. The IB

specifica-tions require R

4to be 275

and R5

to be 200. To attainthe 200-nsec delay,C

2needs to

be approximately 390 pF.Q

2, a 2N2222 current-sup-

pression transistor, requires acurrent-limiting resistor, R

3,

of roughly 1 k. The PWMcomparator’s input, I

SENSE, has

a peak threshold of 1.5V. Fig-ure 4 shows the current-sensesignal of the flyback convert-er before the addition of thesuppression circuit.The wave-form shows that leading-edgespikes turn off switch Q

1.

After you add the leading-edge blank-ing circuit to the power module, it clampsthe leading-edge voltage spikes and allowsthe converter to operate correctly. Figure5 shows the current-sense waveform.Leading-edge noise spikes on the current-sense signal can cause instabilities in peak-current-mode-control power-supply de-signs. Usually, you can resolve these issueswith an RC filter at the input of the peak-current-limit comparator. In some in-stances, the noise disturbance caused byparasitic capacitance and gate-drive cur-rent can cause the PWM comparator totrip falsely. In these instances, the supplyrequires a leading-edge blanking circuitsimilar to this one.


ideasdesign

T1

The leading-edge spike in this waveform couldfalsely trigger the PWM comparator in Figure 1.

C2

GATE DRIVE

R4

R5

Q2

ISENSE

F igure 3

Transistor Q2 suppresses (blanks) leading-edgespikes that could falsely trigger a PWM com-parator.

F igure 4

Without leading-edge suppression, the spikes turn off Q1

in Figure 1.

F igure 5

After adding the blanking circuit of Figure 3, the converterworks normally.

RV V

IGATE BE

B4 =

,

RV V

IGATE BE

B 105 =

/

CT

R RBLANK

224 5

=+( )

,

F igure 2


ideasdesign

To vary the frequency of any sine-wave oscillator, you should use a pairof ganged variable resistors, and you

should thoroughly match their charac-teristics over the entire variation range tosatisfy the oscillator’s balancing condi-tions. This restriction leads to problemsin the tuning range and high cost, there-by limiting the range of applications. Thesine-wave oscillator in Figure 1 is free ofthe cited disadvantage. You can tune itover a wide frequency range using onlyvariable resistor R

1. The oscillator

requires no balancing, so nomatching problems arise. The variableresistor connects to ground, an advanta-geous fact in many applications. Like

most classic sine-wave RC oscillators, theimplementation comprises an opera-tional amplifier, IC

2, with two feedback

loops. One loop is a frequency-inde-pendent, positive-feedback loop usingtwo fixed resistors, R

2and R

3, in this ex-

ample. The other loop is frequency-de-pendent. This loop uses capacitors C

1and

C2; variable resistor R

1; and a single-pole,

double-throw analog switch, IC1, driven

by a periodic sequence of square-wavepulses applied to the SW input.

Assuming a switching frequency,F

S1/T, much higher than the oscillation

frequency and assuming that the pulsewidth, , is half the switching period(0.5T), the approximate voltage trans-

SW

IC1

C1

R1R2

R3

C2

10 nF

1 nF

OUTPUT

4.9k

1k

LT1361

IC2

F igure 1

Grounded resistor tunes oscillatorVladimir Tepin, Taganrog, Russia

In this sine-wave oscillator, the output frequen-cy is dependent only on the value of thegrounded resistor R1.

Some cost-effective analogmultiplexer/demultiplexer ICs,such as the CD4053 and

CD4066, find frequent use as signaldistributors. These digitally con-trolled analog switches have low on-resistance. However, withall channels in the samepackage, crosstalk can be annoyingand unavoidable.

Figure 1 provides a cost-effectiveand viable method of solving thisproblem. By simply adding some n-channel MOSFETs, such as the2N7002 or 2N7000, the crosstalk ef-fect becomes negligible. When theChannel Select signal is high, theCD4053’s input pins A, B, and C as-sume a level of nearly 0V. This oper-ation selects Channel 1. Therefore, theY output connects to Y0 and Z to Z0.Meanwhile, the Channel Select signalturns on Q

4and Q

5, thereby drastically at-

tenuating the Channel 2 signal at Y1 andZ1. The crosstalk effect simultaneouslydecreases. When the Channel Select sig-

nal is set low, YY1 and ZZ1, and Q2

and Q3

turn on to attenuate the crosstalkeffect. For the 2N7002, the R

DS(ON)resist-

ance is several ohms; therefore, the

crosstalk decreases by more than 40 dB.Add to that the analog switch’s internalrejection ratio, and the total crosstalk re-jection could be as high as 80 dB.

AUDIO R OUTAUDIO L OUTAUDIO OUT

CH1L INCH1R IN

CH2L INAUDIO CH2

AUDIO CH1

CH2R IN

CH SELECT

CH2

CH1

1k

1213

21

53

61110

97 8

4

15

14

16

–5V

Q2

Q22N3904

C11 µF

Q3 Q4 Q5

1k

1k

1k

10k

10k

2N7002 2N7002 2N7002 2N7002

VEE GNDCBAINH

Z1Z0

Y1Y0X1 VCC

CD4053IC1 X

Y

Z

X0

F igure 1

MOSFETs reduce crosstalk effectson analog switchesStanley Chen, Global Mixed-Mode Technology, Taipei, Taiwan

By using a few low-cost MOSFETs, you can drastically reduce crosstalk effects in an analog multiplexer.


ideasdesign

SSPWM

COMP

SGNDSYNC

EN/UVLOFB

CSH

HSDVSW

BST

LSDPGND

VDDVIN

VOUT

IC2AMIC6211

12

3

45

6

78 9

1011

1213

14

1516

Q3

MMBT3906

R4100

C10100 pF

C94.7 F

R510k

C51 nF

C40.1 F

C122 F

C222 F

R1100k

VIN 27V

C60.1 F

D1SD103BWS

C30.1 F

Q2SI4800DY

Q1SI4800DY

D2B140

L1

10 H

R2

40m

R316.2k

R61.05k

C747 F

C847 F

VOUT20V AT 2.5A

R91k

R8100

R791

1

5

2

3

4

IC1MIC2182

_

+

F igure 1

Obtain higher voltage from a buck regulatorAjmal Godil, Micrel Semiconductor, San Diego, CA

You can generate 20V output using a standard, current-mode buck regulator.

Several semiconductor vendors’current-mode buck controllers haveinput-voltage ranges of 30 to 36V

but have output-voltage ranges from thereference voltage to approximately 6V.

This output-voltage constraint arisesfrom the common-mode-voltage limi-tation of the current-sense amplifier. Inreal-world applications, the power-sup-ply designer must be able to generate

high output voltage for printers, servers,routers, networking, and test equip-ment. Using a conventional buck regu-lator to generate higher voltages is achallenge. The circuit in Figure 1 meets

fer function of the frequency-dependentfeedback loop is:

where 01/2RC

1C

2is the oscillation

frequency, d0C

1/C

22C

2/C

1, and

d12C

2/C

1. Using this function and

assuming the transfer coefficient of thepositive-feedback circuit to be R

2/(R

2R

3), you obtain the oscillation

condition in the form d1/d

2

2C2/C

1/(2C

2/C

1C

1/C

2). The os-

cillation condition does not depend onR

1. It thus becomes obvious that con-

trolling grounded resistor R1

results onlyin the variation of the oscillation fre-quency and does not affect the conditionfor oscillation. This situation means thatyou can tune this oscillator over a widerange of frequencies, preserving the out-put waveform.

PSpice simulations prove the possibil-ity of tuning the oscillation frequencyover three decades (20 Hz to 20 kHz) byvarying R

1from 1.2 M to 1.2 k. This

design uses an LT1361 (www.linear.com)for IC

2, R

21 k, R

34.9 k, C

110 nF,

C21 nF, and F

S500 kHz. The output-

voltage amplitude is 3.2 to 3.3V. The to-tal harmonic distortion in the 0- to 100-kHz band does not exceed 3%. It’s usefulto note that, because the oscillation fre-quency is proportional to the conduc-tance of the variable resistor (G

11/R

1),

you can use the oscillator as a linear, wide-band conductance-to-frequency or re-sistance-to-period converter.

H ss s d

s s d

20 1 0

2

20 0 0

2( ) ,= + +

+ +ω ωω ω


ideasdesign

the challenge by using an external opamp, a small-signal pnp transistor,and a low-output-voltage buck regu-lator to deliver 20V output voltagefrom a 27V input supply for load cur-rents as high as 2.5A. You can easilyprogram the circuit to provide high-er load currents by merely loweringthe sense resistor, R

2. IC

1, the con-

troller in Figure 1 is the MIC2182,and IC

2, the operational amplifier, is

the MIC6211. Resistors R3

and R6

program the output voltage asfollows: V

OUT20VV

FB(1R

3/R

6).

CSH (Pin 8) and VOUT (Pin 9) ofthe buck controller normally connectacross the sense resistor, R

2, for output

voltages as high as 6V. The controller as-serts current limit when it senses ap-proximately 100 mV across these twopins. In the case of V

OUT20V, the oper-

ational amplifier and Q3

level-shift the

voltage drop across R2from 20V down to

5V, which is within the input common-mode range of the internal current-senseamplifier of the buck regulator. You canreadily understand the circuit operationby assuming a voltage drop of 40 mVacross R

2for a load current of 1A. The

current through R8

is 400 A((20.0420)/100), which is alsothe current through R

9and R

4

(via Q3). This current generates

a voltage drop of 40 mV acrossR

4(400 A100). The con-

troller’s VOUT pin connects tothe internal 5V regulator(VDD) and R

4; the other side of

R4connects to the CSH pin. The

voltage on the VOUT pin is 5V,and the voltage on the CSH pinis 5.04V. The voltage differencebetween these two pins is exact-ly the voltage drop across R

2.

The simple circuit in Figure 1 allows youto achieve greater than 95% efficiency forload currents as high as 2.5A withV

OUT20V, using a conventional low-

output-voltage, current-mode buck reg-ulator. Figure 2 shows the efficiency ofthe regulator.

0 0.5 1.5 2.51 2 3

98

96

94

92

90

88

86

EFFICIENCY(%)

ILOAD (A)

F igure 2

This curve shows the efficiency of the regulator in Figure 1.

www.edn.com June 12, 2003 | edn 87


Whether you use them as indica-tors or to provide illumination,LEDs are hard to beat in efficien-

cy, reliability, and cost. White LEDs arerapidly gaining popularity as sources of il-lumination, as in LCD backlights, butwith forward voltages typically rangingfrom 3 to 5V, operating them from a sin-gle cell presents obvious difficulties. Thisdesign exploits the ultralow operatingvoltage of a single-gate Schmitt inverter,such as the Texas Instruments (www.ti.com) SN74AUC1G14 or the Fairchild(www.fairchildsemi.com) NC7SP14 (Fig-ure 1).When you first apply battery pow-er, Schottky diode D

1conducts, and the

familiar Schmitt-trigger astable multivi-brator starts to oscillate at a frequency de-termined by timing components C

2and

R1. When IC

1’s output goes high, transis-

tor Q1

turns on, and current begins toramp up in inductor L

1. The maximum,

or peak, level of inductor current isI

L(PEAK)(V

BATTV

CE(SAT))t

ON/L

1, where

VBATT

is the applied battery voltage,VCE(SAT)

is Q1’s saturation voltage, and t

ONis the

duration of the high-level pulse at theSchmitt trigger’s output. If Q

1’s saturation

voltage is, for example, less than 50 mV,you can ignore V

CE(SAT)and simplify the

expression to IL(PEAK)

VBATT

tON

/L1.

At the end of tON

, when the inverteroutput goes low, Q

1turns off, and the

voltage across L1

reverses polarity. Theresulting “flyback” voltage immediatelyraises Q

1’s collector voltage above V

BATT

and forward-biases the LED and D2,

which appear in series. This action illu-minates the LED with a maximum for-ward current equal to I

L(PEAK)and raises

IC1’s supply voltage, V

BOOT, to a diode

drop above VBATT

. D1

is now reverse-bi-ased and remains so for as long as thecircuit continues to oscillate. The re-sulting “bootstrapped” supply voltagefor IC

1ensures that the astable multivi-

brator continues to operate even whenV

BATTfalls to very low levels. You should

choose values for C2

and R1

to producea time constant of microseconds, there-by allowing a small inductance value forL

1. For example, a test circuit using val-

ues of C268 pF, R

139 k, and L

147

H produces an operating frequency ofapproximately 150 kHz at V

BATT1V.

The resulting value of tON

3 sec leads

to a peak inductor current of approxi-mately 65 mA and produces excellentbrightness in the white LED. Even withV

BATT as low as 500 mV, the correspon-

ding peak current of 33 mA producesreasonable LED intensity.

The inductance value should be as lowas possible to maintain a high peak cur-rent and, hence, adequate LED bright-ness at the lowest supply voltage. How-ever, L

1should not be too small, or the

peak current could exceed the LED’smaximum current rating when V

BATTis

at a maximum. Remember that the in-ductor should be adequately rated to en-

C110 µF

C31 nF

R22.2k

IC1SN74AUC1G14OR NC7SP14

NOTES: D1, AND D3 ARE BAT42s OR SIMILAR.

C4

D3

Q2 D2

VAUX

L1

ILLED

C2

Q1

R1

D1 D2

VBOOT VBOOT

VBATT VBATT

SINGLECELL1.5V

NOMINAL

2 4

GND

10k

TO PIN 5,IC1

GND

5

3

+C1

10 µF

+

+

+

D2 IS A 1N4148 OR SIMILAR.

F igure 1

Light a white LED from half a cellAnthony Smith, Scitech, Biddenham, Bedfordshire, UK

This circuit produces dazzling intensity in a white LED from very low battery voltages (a). A modification allows even lower battery voltages (b).

Light a white LED from half a cell ............87

LED driver delivers constant luminosity ......................................88

Get more power with a boosted triode ....................................90

White-LED driver touts high efficiency ................................................92


(a) (b)

88 edn | June 12, 2003 www.edn.com

ideasdesign

sure it does not saturate at the highestvalue of peak current. Switching tran-sistor Q

1should have very low satura-

tion voltage to minimize losses and pro-duce the highest possible peak current.The addition of D

3and C

4 enables the

circuit to generate an auxiliary supplyvoltage, V

AUX, which you can use to drive

low-power circuitry without adverselyaffecting the LED’s intensity. With a bat-tery voltage of 1V, the test circuit pro-duces good light intensity in the whiteLED and delivers almost 1.5 mA at 4.7Vto the auxiliary load. Even at V

BATT500

mV, the circuit delivers 340 A into a

10-k load and maintains reasonableLED brightness. Note that IC

1cannot

take power from the auxiliary rail, be-cause V

AUXcan easily exceed the maxi-

mum voltage rating of the two suggest-ed device types.

The minimum start-up voltage de-pends largely on the device you use forD

1. Tests using a high-quality Schottky

diode produce a minimum power-upvoltage of just 800 mV. You can furtherreduce this level by replacing D

1with pnp

transistor Q2(Figure 1b). This modifica-

tion allows the test circuit to start up atjust 650 mV at room temperature. Note,

however, that Q2’s collector-base junction

becomes forward-biased under quiescentconditions, which results in wasted pow-er in its base-bias resistor. Despite its sim-plicity, the circuit can produce spectacu-lar results with high-brightness LEDs.The Luxeon range of LEDs from Lu-mileds (www.lumileds.com) allows thecircuit to demonstrate its prowess. WithL

1reduced to 10 H and V

BATT1V, the

circuit generates a peak current of 220mA in a Luxeon LXHL-PW01 white LED,resulting in dazzling light intensity.

The circuit in Figure 1 issimilar in principle tothat of a previous Design

Idea (Reference 1) but offersimproved, more reproducibleperformance. The outputcurrent is almost constantover an input-voltage range of1.2 to 1.5V and is insensitiveto variations of transistorgain. Transistors Q

1and Q

2

form an astableflip-flop. R

1and C

define the on-time of Q2.

During that time, Q1

is off,and the voltage at the base ofQ

1and the current in induc-

tor L ramp up. When the volt-age at the base of Q

1reaches approxi-

mately 0.6V, Q1

turns on, and Q2

turnsoff. This switching causes “flyback”actionin inductor L. The voltage across the in-ductor reverses, and the energy stored inthe inductor transfers to the LED in theform of a down-ramping pulse of cur-rent. During flyback time, voltage acrossthe LED is approximately constant.

The voltage for yellow and white LEDsis approximately 1.9 and 3.5V, respec-

tively.When the current through the LEDfalls to zero, the voltage at the collector ofQ

2falls sharply, and this circuit condition

triggers the next cycle. Assuming the jus-tifiable approximation that the saturationvoltage of Q

2is close to 0V and that the

LED’s forward voltage, VD, is constant,

you can easily derive the expression forthe average dc current through the LED:

At first glance, IAVE

de-pends strongly on V

IN. But

close examination of thelogarithmic term revealsthat, with a proper selectionof V

B, the logarithmic term

can become a sharply de-clining function of V

IN. The

logarithmic term thus fullycompensates for the termV

IN2 in the expression. That

compensation is preciselythe purpose of the diode,D

1, in series with the base of

Q1. The circuit drives a

high-brightness yellow orwhite LED. Table 1 showsthe proper component se-

lection for both colors. Table 1 also showssome measured results at V

IN1.35V. Be-

cause the voltage across the white LEDfalls from 3.9 to 3.1V during flyback, ca-pacitor C subtracts current from theamount available to the base of Q

1. This

subtraction might retrigger the circuitbefore the current in L falls to zero. Theaddition of R

3and D

2solves this problem.

During flyback, the current that flowsthrough R

3compensates for the current

withdrawn through C.

Reference1.Nell, Susanne, “Voltage-to-current

converter drives white LEDs,” EDN, June27, 2002, pg 84.

L

LED

VD

D1

1N4148

1N4148

Q12N2222

Q22N2222

D2R3

4.7k

C

R110kR2

2.2k

VIN

NOTE:WHITE LED REQUIRES R3 AND D2.

VB

F igure 1

LED driver delivers constant luminosityIsrael Schleicher, Bakersfield, CA

This circuit delivers virtually constant luminosity for a white or a yel-low LED.

TABLE 1—COMPONENT SELECTION FOR YELLOW OR WHITE LEDLED L (mH) C (pF) D1 Current drain LED current Frequency Power-conversion

(mA) (mA) (kHz) efficiency (%)Yellow 1 470 1N4003 5.6 3.30.1 40 83White 2 1800 1N752 12.4 3.70.2 15 78

IV R C

V L

V V V

VAVEIN

De

IN D B

I2

21= +

log

NN BV

.


ideasdesign

This Design Idea is a reprint of anearlier one that contained errors ingraphics (Reference 1). Even though

6L6 beam-power tubes have been aroundfor 66 years, they are still quite popularfor use in electric-guitar amplifiers, andits cousin, the 6CA7 (EL34) power pen-tode, is a favorite among audiophiles. Thedevelopers of these tubes designed themfor pentode-mode operation, and theydeliver maximum audio power in thismode. On the other hand, many audio-philes prefer triode-mode operation and,until now, had to be content with a 50%reduction in output power. This reduc-tion means that they require larger pow-er supplies and twice as many expensivetubes to obtain pentode power from a tri-ode amplifier. Figures 1a, 1b, and 1cshow the 6L6 connected as a pentode, a

true triode, and a “boosted triode,” re-spectively. The boosted-triode configu-ration allows pentodes to produce pen-todelike power while operating in atrue-triode mode. To understand the op-eration of the boosted triode, it’s usefulto review some vacuum-tube theory. The6L6 is a beam-power tube and has cath-ode, control-grid, screen-grid, suppres-sor-grid, and plate electrodes. The sup-pressor grid is actually a virtualsuppressor grid provided by two beam-forming plates, but you can treat the 6L6

beam-power tube as a pentode. You canthink of a pentode as an n-channel JFETwith the following electrode functions:

Thermionic cathode: source of elec-trons (corresponds to the JFET source);

Control grid: controls the cathodecurrent; operated at a negative potentialrelative to the cathode (corresponds tothe JFET gate);

Screen grid: electrostatically screensthe control grid from the plate, therebyreducing the effect that the plate voltagehas on the cathode current; operates at a

_

+

–32V

47k

6L61 µF

400V 8

_

+

–44V

47k

6L61 µF

400V 8

_

+

–14V

47k

(a) (b) (c)

6L61 µF

400V

250V

100V

8

F igure 1

0–2.5–5–7.5–10–12.5–15–17.5–20–22.5–25

PLATECURRENT

(mA)

PLATE VOLTAGE (V)

100 200 300 400 500 600 700 800

250

200

150

100

50

00

LOAD LINE

300

250

200

150

100

50

0

50

0

10

20

30

40

50

60

70

80

90

PLATECURRENT

(mA)

PLATE VOLTAGE (V)

0 100 200 300 400 500 600 700 800

LOAD LINE

A pentode (a) can deliver much more power than a triode (b), unless you use a boosted-triode configuration (c).

F igure 2 F igure 3The load lines for a pentode show that the platecan draw 150 mA at a plate voltage of only 50V.

A pure triode needs 200V plate voltage todraw 150 mA.

Get more power with a boosted triodeDave Cuthbert, Boise, ID

TABLE 1—PENTODE, TRIODE, AND BOOSTED-TRIODE PARAMETERSDC plate Grid bias Grid swing Output power

Amplifier current (mA) (V) (V) (W)Pentode 75 14 22 11Triode 75 32 64 6Boosted triode 75 44 88 10


ideasdesign

positive potential relative to the cathode; Suppressor grid: prevents secondary

electrons from leaving the plate and trav-eling to the screen grid; operates at thecathode potential; and

Plate: collects the electrons (corre-sponds to the JFET drain).

Figure 2 shows the pentode’s charac-teristic curves for control-grid volt-ages of 0 to 25V and a screen-gridvoltage of 250V. Note the idealized loadline and that the tube can draw a platecurrent of 150 mA at a plate voltage ofonly 50V. High voltage gain, high plateimpedance, and high output power char-acterize pentode-mode amplification. Byconnecting the screen grid directly to theplate, you can operate the tube in triodemode. Low voltage gain and low outputimpedance characterize this mode. Figure

3 shows how the triode curves differ fromthe pentode curves. The curves representcontrol-grid voltages of 0 to 90V. Notethe load line and that, in triode mode, theplate cannot draw 150 mA at a plate volt-age lower than 200V. This fact greatly lim-its amplifier efficiency and power output.However, in spite of the limited outputpower, some people still prefer triodemode because they claim that it produces

a superior-soundingamplifier.

For the boosted-tri-ode circuit in Figure 1c,you simply add a 100Vscreen-to-plate powersupply (Figure 4) to thestandard triode-ampli-fier circuit. This ad-dition shifts the triodecharacteristic curves100V to the left (Figure5). Note the load lineand that the plate cannow draw 150 mA at aplate voltage of only

100V, rather than 200V as with the pure-triode-mode circuit. You can obtain sig-nificantly higher power with boosted-tri-ode amplification and still maintain thecharacteristics of triode amplification. InSpice simulations of three single-endedClass A audio amplifiers using MicroCap-7 evaluation software (www.spectrum-soft.com), the control-grid bias for a qui-escent plate current is 75 mA, and the acgrid signal is just short of amplifier clip-ping. The transformer ratios provide aplate-load impedance of 5 k for the pen-tode and 3 k for both the triode and theboosted triode. Table 1 details the param-eters.

Reference1. Cuthbert, Dave, “Get more power

with a boosted triode,” EDN, April 3,2003, pg 72.

300

250

200

150

100

50

0

50

0

10

20

30

40

50

60

70

80

90

PLATECURRENT

(mA)

PLATE VOLTAGE (V)

0 100 200 300 400 500 600 700 800

LOAD LINE

With a boosted triode, the plate can draw 150 mAwith a plate voltage of 100V versus 200V for apure triode.


100V DC40 mA

120V AC 120V AC 22O F250V

(PD=3W)

1N5378B

2SC4953 WITH HEAT SINKOR SIMILAR

+

A 100V screen-grid power supply transforms a normal triode into a boosted triode.

White LEDs, the most recent addi-tion to the LCD backlight, findcommon use in providing back-

light for color LCDs. Thanks to their sizeand white-light output, they appear insmall,portable devices with color displays,such as PDAs and cellular phones. Likeother LEDs,a white LED needs a constant-current source—typically, on the order of15 to 20 mA. The forward voltage of awhite LED is approximately 3.5V. Mostproducts use multiple LEDs to provide ad-equate backlight for a display. Because theLED’s brightness depends on its forwardcurrent, these multiple diodes commonly

connect in series to ensure that the samecurrent flows through each of them. Youneed approximately 14V to forward-biasfour series-connected LEDs, starting fromthe nominal operating voltage, 2.7 to 4.2V,of a single-cell lithium-ion battery. Boostregulators usually provide this operatingvoltage. A current-sense resistor, whichyou insert in series with the LEDs, closesthe feedback loop. However, it is impor-tant to minimize the voltage drop acrossthis resistor to increase efficiency. Cur-rently available integrated boost regulatorscommonly use a 1.24V bandgap voltage asthe feedback reference, which results in

1.24V loss across the current-sense resis-tor, a loss that represents approximately7% loss in efficiency. Figure 1 shows an in-teresting LED-drive circuit.

You use the SP6682, a standard, regu-lated charge-pump circuit, in an unusu-al manner to control the external switch,Q

1. This IC incorporates an internal 500-

kHz oscillator, which would normallydrive charge-pump capacitors to doublethe input voltage. The circuit in Figure 1uses no charge-pump capacitors. Instead,the oscillator output appears on Pin 7and drives Q

1on and off. Q

1, L

1, D

1, and

C1

function as a conventional boost reg-

White-LED driver touts high efficiencyDimitry Goder, Sipex Corp, San Jose, CA

F igure 5

F igure 4


ideasdesign

ulator, which builds up voltage across C1.

When this voltage exceeds the sum of thediodes’ forward drop, current starts toflow. The circuit senses current across R

1

and compares it with a 0.3V referencevoltage inside the chip. This circuit pro-

vides efficiencies as high as 87%, a figurethat exceeds that of any integrated boostregulator. Several factors are responsiblefor the increased efficiency. First, the chipintegrates the 0.3V reference voltage,which is significantly lower than the typ-

ical 1.24V. This reference voltage appearsin series with the LEDs and thereforeconstitutes an efficiency loss propor-tional to the value of the reference. Sec-ond, a discrete MOSFET provides lowon-resistance and high switching speed,parameters superior to those of any in-tegrated switch.

Q1

is a low-cost device that comes in atiny SOT-23 package. Also, the excellentdrive capability of the charge-pump ICensures low switching losses. By chang-ing the type of the MOSFET you use, youcan make a trade-off between desired ef-ficiency and cost. The breakdown voltageof the MOSFET limits the maximumoutput voltage; you can adjust the volt-age to drive a system with as many LEDsas you need. (Larger displays use eight to12 LEDs.) For dimming purposes, ap-plying a PWM signal to the Enable pincauses the regulator to shut down andrestart. This function allows you to pre-cisely control LED brightness.

SP6682

10

2

4

3

1

9

6

8

PWM IN

NO CONNECT

NO CONNECT

NO CONNECT

NO CONNECT

ENABLE VFB

Q1Si1304

7

5

C2N

VIN C11 F

R115

L14.7 H

VIN 2.7 TO 4.2V

D1

F igure 1

This circuit uses a charge-pump IC to provide power to a series string of LEDs.

www.edn.com June 26, 2003 | edn 99

ideasdesign


Industrial and telecom applica-tions often require a nonisolated, low-voltage supply from a high-voltage in-

put. IC manufacturers have responded tothat need with the application of high-voltage processes and offer control ICsthat work to 50V and higher. That volt-age is sometimes insufficient, and youneed further design techniques to extendthe input voltage. The buck converter inFigure 1 represents one such technique.In addition to allowing circuit operationover a wide input-voltage range, thetechnique reduces power dissipation, be-cause the control circuit does not operatedirectly from V

IN. The circuit uses a lin-

ear regulator and a source-switched driv-er to buffer a control IC from a line whose

voltage is as high as 110V. When you ap-ply the input voltage, current flowsthrough resistor R

2and zener diode D

2,

clamping the gate voltage of FET Q1

to9.1V. C

2reaches a voltage of approxi-

mately 6V, which is equal to Q1’s gate

voltage minus its typical turn-on thresh-old of 3V. FET Q

1now acts as a crude lin-

ear regulator and allows the control cir-cuit to become active.

The source-switched driver of Q2, Q

4,

and Q5

then comes into play to allow thesupply to come into regulation. TheTL5001’s open-collector output switchesto a low state to turn on the main powerswitch, Q

3. With the gate of FET Q

5also

held at 9.1V and the output pin of theTL5001 low, current flows through Q

5’s

VCC

DTC

COMP

FB

RT

GND

OUT

SCP

IC1TL5001AID

R82.74k

R74.99k

R630.1k

R37.15k

C40.047 F

C3470 pF

R544.2k

C80.01 F

C20.1 F

C71 F

C50.01 F D2

9.1VBZX84C9V1LT1

1

J1

VIN20 TO 110V DC

GND

1

2

Q5SI2320DS

Q1SI2320DS

Q4MMBT5401

Q3IRFR6215

Q2MMBT3904

R240.2k0.5W

R11k

C10.1 F200V

D3MURS120T3

C6100 F

16V

1

1

2

2

3

J212V, 0.2A

GND

L11 mH

5

2

3

4

6

7

8

FREQUENCY200 kHz

R4402

D1BAS16

F igure 1

Gate-drive method extends supply’s input rangeJohn Betten and Robert Kollman, Texas Instruments, Dallas, TX

A buck converter uses switched-source gate drive to generate high output voltages.

Gate-driven method extends supply’s input range......................................99

Active-clamp/reset-PWM IC becomes more versatile ............................100

Circuit provides hiccup-current limiting................................102

Microcontroller provides SRAM battery backup ................................104

Positive regulator makes dual negative-output converter................106

Analog switch frees stuck I2C bus ............108



ideasdesign

drain-to-source pins. The amount ofdrain current that flows is equal to:(9.1VQ

5’s turn-on thresholdIC

1’s Pin

1 saturation voltage)/R4. In this example,

this current is nominally approximately12 mA. Because most of this currentflows through R

1, the value of R

1sets the

voltage amplitude used for the gate driveof Q

3. With a value of 1 k for R

1, the

voltage across it is 12V. Transistors Q2and

Q4

form an npn/pnp pair to quicklyswitch gate-drive current into and out ofQ

3. The base-emitter junction of Q

4con-

ducts when a voltage drop exists acrossR

1. This conduction quickly pulls down

the gate of Q3

from VIN

to approximately11.2V (12VV

BE). Because Q

3is a p-

channel FET, pulling the gate to 11.2Vlower than the source turns it on. Whencurrent is not flowing in R

1, the base of

Q2pulls up to V

IN, a voltage that forward-

biases its base-emitter junction.The gate of Q

3quickly charges to near-

VIN

potential, thereby turning off Q3. This

drive circuit is fast, because none of thetransistors operates in a saturated mode;therefore, Q

3can attain 0.5-sec turn-on

time. This speed means that the circuitcan achieve reasonably high operatingfrequencies with the low duty cycles youencounter in a high-voltage input. Youcan scale this gate-drive circuit for high-er or lower input voltages by the properselection of the drain-source (or collec-

tor-emitter) ratings of Q1, Q

3, Q

4, and Q

5.

All must have voltage ratings greater thanthe input voltage, and all, except for Q

1,

should also be able to switch at highspeeds. The addition of diode D

1offers

two advantages. It allows the control cir-cuit to operate after start-up from theoutput voltage, rather than the inputvoltage. This method is more efficient,inasmuch as the input voltage is relative-ly high. A bias-power savings of approx-imately sevenfold is the result. Also,adding D

1pulls the source pin of Q

1to

approximately 11.2V, thus Q1

turns off.All bias power to the controller nowcomes from the output voltage, and Q

1

no longer dissipates power.

The UCC3580 (www.ti.com), IC1

inFigure 1, is an active-clamp/reset-PWM IC that has all the requisites of

a power-supply IC except for current limit. You can use the shutdown pin (16)for this purpose (see the UCC3580 data

sheet). But when the shutdown pin acti-vates, the soft-start capacitor normallyconnected to Pin 15 discharges, and theconverter starts again, resulting in hiccupmode. Poor dynamic response ensues be-cause of this circuit behavior. The prob-

lem becomes especially serious when youhot-plug a load card, with typically 100-F decoupling across the converter’s out-put, into the motherboard.You can avoidthis problem by not using the shutdownpin for current limiting. Instead, use the

UCC3580IC1

14

12

3

8

SYNCHRONOUSRECTIFIER

D1C2

C3VOUT5V

T2

C1

VIN

L1T1

R20.1

Q1

R310k

R7510k

C60.1 F

C50.1F

V

V

R6100

R42.7k

R510k

D5

D6

D7

Q2

V

D3D2

C410 F

R1

D412V

ZENER

LM358

+

_

+

F igure 1

Active-clamp/reset-PWM IC becomes more versatileGowripathi and M Sindhu, ITI Ltd, Bangalore, India

This circuit does not use the shutdown pin of the PWM IC; instead, it relies on the error amplifier’s output to provide current limit.


ideasdesign

error amplifier’s output pin, Pin 12. Q1

isthe main switch, T

1is the main trans-

former, and C1

is the bulk capacitor. Q2,

D3, and D

4provide power (V) for IC

1

during start-up and current limit. D1

andC

2rectify and filter the voltage from the

auxiliary winding of T2to power the con-

trol circuit during normal operation. R2

senses the current in the main switch, Q1.

The LM358 op amp provides currentlimit. Diode D

6isolates the op amp and

Pin 12 of IC1

during normal operation.According to the data sheet of UCC3580,the error amplifier’s output should pulldown to 0.3V or lower for 0% duty cycle.This condition forces you to use a nega-tive supply (V) for the op amp to obtainrated performance.As Figure 1 shows, thesame supply voltage (V) serves for the

PWM IC and the op amp.You can obtainthe negative supply voltage (V) for theop amp from another winding on T

2.

Even though the voltages that T2

gener-ates decrease in foldback condition, the opamp continues to obtain V from Q

2. A

negative voltage (V) from T2is adequate

for proper operation of the op amp. TheSchottky diode, D

7, from Pin 12 to ground

protects the error amplifier’s output fromlarge negative voltages.

The inverting input of the op ampsenses the peak pulse voltage across R

2.

Diode D5

helps C5

to charge to peak volt-age (peak detection), and R

3helps to dis-

charge C5when the peak voltage across R

2

decreases. Use a slow diode for D5. The

reference voltage at the noninverting in-put has two components—first, from the

fixed 5V reference (Pin 14) of IC1; sec-

ond, from the voltage generated by the T2

winding. This voltage decreases with out-put voltage, and voltage foldback occursat the noninverting input. The 50-mVcomponent from the fixed 5V referenceis necessary for start-up. As the currentlimit starts, the output voltage starts todecrease, and the noninverting-inputvoltage also decreases, causing foldback.With this circuit, if the current limit startsat an output current of 10A, the outputshort-circuit current is 2A. The outputrecovers even with minimal current hys-teresis. The positive voltage that the T

2

winding generates decreases from 13Vjust before current limit to 3V at shortcircuit. This circuit does not influence thetransient response of the converter.

Current-limit protection is anessential feature for power-supplysystems. The three major types of

current-limit-protection mechanismsare constant, foldback, and hiccup. Hic-cup current limit performs the best ofthe three types; however, the implemen-tation is rather complex. In this scheme,upon detection of an overcurrent event,the whole power supply shuts down foran interval before it tries to power itself

up again. The cycle repeats until theovercurrent fault disappears. With suchoperation, the dissipation in the powersupply itself is minimal. You can incor-porate the circuit in Figure 1a into thePWM circuit of a switch-mode powersupply to implement the hiccup feature.Figure 1b represents a typical shunt-voltage regulator to regulate the V

CCthat

powers the PWM controller.Most PWM controllers have an un-

dervoltage-protection feature, in whichthe internal circuitry shuts down when-ever its V

CCdrops below a certain thresh-

old. For example, assume that the circuitin Figure 1a works with a UCC3570PWM controller. In this chip, an excessivecurrent that causes the Count pin to ex-ceed 4V or the ILIM pin to exceed 0.6Vsets the shutdown latch. This action thenforces the PWM controller’s output to golow and discharge the soft-start capaci-

CLAMP

CLAMP

VAUX

510

DZ12VC3

0.1 F1 F

VCC

BD677AQ4

(b)(a)D3

1N4148

D11N4148

D21N4148

SS600 600

1 FC2

Q22N2907A

Q32N2222A

100

12k

VCC

R2

C1100 F

200k

110kTL431

Q12N2222A

R1

11k

TO SOFT-START PIN OF THE PWM IC

IC1

10

F igure 1

Circuit provides hiccup-current limitingCH How and KP Basu, Multimedia University, Cyberjaya, Malaysia

You can incorporate hiccup circuitry (a) into your PWM-control scheme, using a typical shunt regulator (b) to regulate the supply voltage to the PWM chip.


ideasdesign

tor, C2. The discharge current of C

2caus-

es Q3and, hence, Q

2to turn on for a short

interval to charge the timing capacitor,C

1. The moment the voltage across C

1

builds up, Q1

turns on and activates IC1

to overwrite the VCC

voltage, which DZ

initially set to a voltage—in this case,7.02V—low enough to turn off the PWMcontroller (Figure 1b). With this action,the controller becomes temporary dis-abled, and the shutdown latch resets.

After C2completely discharges, Q

3and

Q2

switch off, and the charge stored in C1

continuously supplies the base driveneeded to hold Q

1on through R

1. The

PWM controller then stays in sleep modefor the fixed interval, t

SLEEP, until the dis-

charge current of C1

can no longer keepQ

1on. You can estimate this sleep-time

interval (Figure 2) by using the followingequation:

where IIC1

is the forward current of IC1

(10.7 mA with VAUX

12.5V), VC1

(0) isthe initial voltage stored in C

1(5.05V),

R1C

1(1.1 sec), h

FEQ1is the dc current

gain of Q1

(170 from test results), and

tSLEEP

is the sleep timefor the PWM IC (2sec).

Note that, accordingto the 2N2222A datasheet, dc current gaincan be 75 to 300.Therefore, to obtain abetter prediction fromthe above equation, it isadvisable to determinethe dc gain throughsimple testing. To solvethe equation, youmust first deter-mine V

C1(0). This

quantity depends onseveral factors. First, itdepends on the PWMIC. The IC can discharge the soft-start ca-pacitor either linearly (constant-currentsink) or exponentially (RC discharge).Knowing this fact, you can work out theturn-on time, t

ON, of Q

3and Q

2by plug-

ging tON

and VCC

into the standard RC-charging equation with the time constantof

1R

2C

1. In Figure 1a, because

2.31t

ON5

1, you can approximate

VC1

(0) by using VC1

(0)VIC1

VBEQ4

V

CEQ2V

D1.

After time period tSLEEP

elapses, C1

should have discharged to a low enoughvoltage to turn off Q

1, thereby allowing

VCC

to climb back to its normal value,thus enabling the PWM controller. Thesoft-start capacitor then charges upagain. The output pulse gradually startsto generate after the soft-start voltagereaches the internal threshold. This“sleep-reboot-detect” cycle repeats untilthe fault disappears.

A scope display shows the relevant waveforms duringhiccup operation. Trace 1 is the VCC output voltage of

the shunt regulator, Trace 2 is the soft-start voltage of the PWM con-troller, Trace C is the collector-emitter voltage of Q3, and Trace B isthe voltage across timing capacitor C1.

To maintain content inthe event of power loss,many designs that include

SRAM require a dedicated de-vice that can automaticallyswitch from a standard powersupply to battery operation.Microcontrollers seldom finduse in power-switch-ing applications. Be-cause microcontrollers typi-cally operate from the primarypower supply, they stop exe-cution if that supply drops,thereby making it impossibleto perform the switching op-eration. However, by using acharacteristic of many microcontrollers,you can perform this switching functionwithout interruption to the SRAM (Fig-

ure 1). Many microcontrollers have in-ternal protection diodes on their I/Opins. Therefore, if the V

CCpin is left float-

ing, the CPU in many in-stances powers up and runsif you apply power only toan I/O pin. With this fact inmind, you can create an“automatic voltage switch”by connecting the mainpower-supply rail and a sec-ondary battery backup totwo separate I/O pins of themicrocontroller. The mi-crocontroller can then havefirmware that drives a thirdI/O to a logic-high (source)mode or otherwise sourcecurrent to an output pin.This output then provides

the uninterrupted power to the externallow- power SRAM device.

When the VCC

rail is present, the mi-

LOW-POWER SRAM

GND

VCC

CHIP ENABLE

GNDVCC

BATTERY OK

POWER SUPPLY OK

OPTIONAL STATUS SIGNALS

MICROCONTROLLER

POWER-SUPPLY INPUT

BATTERY INPUT

MICROCONTROLLER-I/O-PORT INPUTS

F igure 1

Microcontroller provides SRAM battery backupDave Bordui, Cypress Semiconductor, Orlando, FL

A microcontroller can power up and run even if its VCC pin is floating.

I

hR V V eIC

FEQC BEQ

tSLEE

01

11 1 1× = ( ) ×( )

PP

τ ,

F igure 2


ideasdesign

crocontroller draws current from the VCC

pin and operates normally. If the VCC

raildrops below the battery-input voltage,the microcontroller automatically drawscurrent from the battery instead. Al-though this scenario requires nofirmware whatsoever, many microcon-trollers can run firmware and continueexecution throughout this power-supplytransition. Continuing the microcon-troller’s firmware execution allows other

firmware-based functions, such as de-assertion of SRAM chip enable, battery-and rail-health indication, and analog-to-digital conversion. When you use thistechnique, you must take care to ensurethat the entire design draws less currentthan the forward-bias-current rating ofthe protection diode. Also, the externalSRAM circuit must draw no more cur-rent than the microcontroller’s outputcan source. This stipulation remains true

whether the VCC

rail or the battery pro-vides power. It is also important to real-ize that, because the protection diodes aresourcing the power, a slight voltage dropexists on the microcontroller’s uninter-rupted-power-supply output. This volt-age drop is equivalent to the one that themicrocontroller’s manufacturer specifies.You should consider this drop when youselect the battery, V

CCrail, and external-

SRAM voltage requirements.

Some systems, such as optical net-works, require more than one neg-ative voltage. A common procedure

is to boost the main negative supply of5V to 10V and then reduce it with alinear regulator to 9V. The 5V itselfcomes from a positive supply, typically 5or 12V. Independently creating each ofthe two negative voltages requires the useof two switching-regulator ICs. Howev-er, a simpler approach uses only one step-down switching regulator and createsboth a negative output with low ripplecurrent and a second output with twicethe voltage. The circuit in Figure 1 is apositive-to-dual-negative dc/dc convert-er that converts 5V to both 5V and10V, using a positive buck regulator.This configuration is not a usual appli-cation circuit of a positive buck-regula-tor IC, which you would typically find insingle-output step-down applications.However, by rearranging the connectionsto ground and V

OUT, the dc/dc con-

verter becomes a common posi-tive-to-negative converter.

The circuit features an additional neg-ative-output stage with twice the voltageof the first output by using a second in-ductor, a catch diode, and an output ca-pacitor. The circuit includes a couplingcapacitor, C

COUP, for energy transfer to

the second winding and offers regulationof the secondary output without feed-back. The use of two inductors, as op-posed to one transformer, can provide aflexible circuit layout. This circuit meas-

ures less than 3 mm high and delivershigh load current (Figure 2). You can re-place the two inductors with a single 1-to-1 transformer, but even at the high1.25-MHz switching frequencies, it maybe difficult to find a less-than-5-mm-high transformer that can do the job. TheLT1765 buck regulator provides high cur-rent capabilities even with small induc-

tors and all-ceramic coupling, input, andoutput capacitors, thanks to both its 1.25-MHz switching frequency and its 3A on-board power switch.

Figure 2 shows the output capabilityfor the circuit in Figure 1. The load cur-rent on one output determines the max-imum available load current on the oth-er. At maximum output current, the peak

FB

VCGND

SHDN

SYNC

VIN

BOOSTVSW

LT1765EFE-5

1800 pF

100 pF2.4k

10 F16V

X5R CERAMIC

0.22 F

CMDSH-3

L1CDRH6D28-3R0

B220A

B130A

CCOUP4.7F16VX5R

L2CDRH6D28

33 H

COUT210 F6.3VX5R

CERAMIC

COUT10 F6.3VX5R

CERAMIC

VOUT5V

VOUT210V

CIN

IC1

VIN5V

F igure 1

Positive regulator makes dual negative-output converterKeith Szolusha, Linear Technology Corp, Milpitas, CA

You can use a positive buck regulator to configure adual, negative-output dc/dc converter.


ideasdesign

switch current (the sum of the peak in-ductor currents) is equal to 3A. Forcingthe output current higher than the max-imum value can cause the output voltageon both lines to collapse and lose regula-tion. The single feedback signal directly

monitors VOUT

, but the low-im-pedance ceramic coupling ca-pacitor with an extremely highrms current rating keeps V

OUT2

well-regulated. As loadconditions change onboth V

OUTand V

OUT2,

VOUT2

’s regulation be-comes slightly compro-mised over different loadconditions. V

OUT2can be-

come unregulated if theload current on V

OUT2be-

comes extremely small. Apreload of 5 mA on V

OUT2

is necessary to maintainregulation if the load current fallsbelow 5 mA. Zero load current onV

OUTdoes not cause the con-

verter to lose regulation.Cross-regulation typically stayswithin 1% of the typical output

voltage, an excellent rating for a single-feedback, dual-output converter. Figure3 shows typical efficiency curves for var-ious values of the load current on V

OUT2.

0 200 400 600 800 1000

VOUT LOAD CURRENT (mA)

EFFICIENCY(%)

80

76

72

68

64

60

VOUT2 LOAD CURRENT=400 mA



VOUT2 LOAD CURREN =100 mA

F igure 3

The circuit in Figure 1 has high conversion efficiencyfor various values of load current.

0 200 400 600 800 1200

VOUT LOAD CURRENT (mA)

MAXIMUM VOUT2

LOAD CURRENT

(mA)

1000

600

500

400

300

200

100

0

F igure 2

The circuit delivers high maximum currents available fromthe two outputs in the circuit of Figure 1.

The dual-channel PCA9540 I2Cmultiplexer often breaks up an I2C orSM bus or allows you to use devices

with the same addresses on the same bus.When the PCA9540 initially powers up,it comes up in a state in which both chan-nels are deselected. The I2C- or SM-busmaster can then address the control reg-ister in the PCA9540 to select eitherChannel 0 or Channel 1, connecting themaster to the appropriate channel. TheI2C bus can then address downstream de-vices on the selected channel. If a failureoccurs in one of the downstreamchannels, such that the I2C bus isstuck at high or low, the I2C-bus mastercould become disabled. Because thePCA9540 has a power-on-reset functionthat initializes the multiplexer with allchannels disconnected, this feature canfree the bus. In some applications, how-ever, powering down the entire systemmay be impractical. One way to avoidpowering down the entire system is to in-stall a low-on-resistance analog switch inseries with the power-supply line of themultiplexer (Figure 1).

When the enable pin of the 74LVC1G66goes low, the supply voltage disconnectsfrom the multiplexer, thereby freeing upthe I2C bus. The I2C master or any othersystem controller can generate this hard-ware reset. The 74LVC1G66 is available ina 2-mm2 package,so the circuit takes up lit-tle additional board space. This example

uses the PCA9540, but you can use the74LVC1G66, with a typical on-resistanceof approximately 6, to selectively controlthe power for any device that has a power-on-reset function. Its size and wide oper-ating-voltage range also make it practicalto selectively power down sections of anycircuit in power-sensitive applications.

SC1

SD1

SC02.7 TO 5.5V

2.7 TO 5.5V

2.7 TO 5.5V

3.3V

RESET

CHANNEL 0

CHANNEL 1

SD0

PCA9540

74LVC1G66

Z

Y

E

SCL

SDA

SCL

SDA

VSS

IC2MASTER

VDD

VDD

F igure 1

Analog switch frees stuck I2C busBob Marshall, Philips Semiconductor, Morgan Hill, CA

To free up a stuck I2C bus, this circuit controls the supply voltage to force a hardware reset.

www.edn.com July 10, 2003 | edn 77


Ramp or sawtooth waveforms areuseful for a broad range of applica-tions, including automatic-test

equipment, benchtest equipment, andactuator control. Discrete componentstypically set the waveform frequency. Un-fortunately, drift in these componentvalues over time and temperature limitsthe accuracy of the output frequency.

Also, changing the frequency requiresthat you use a different set of compo-nents. This Design Idea describes a flex-ible implementation of a sawtooth wave-form generator (Figure 1) using twoDDS (direct-digital-synthesis) devices.The frequency of the sawtooth is digital-ly programmable, so the design requiresno external components to set the fre-quency. A DDS device, a programmablewaveform generator, can deliver sine,square, and triangular (up/down ramp)waveforms. You can digitally implementchanges in phase or frequency by loadingonboard registers. Using the phase regis-ters, the DDS chip can generate two lin-ear up/down ramps of the same frequen-cy but with a 90 offset. The up ramp ofone occurs at the same time as the downramp of the other. Selecting a phase reg-ister causes the signal from that registerto go to the output.A sawtooth waveformoccurs when the only the “up ramp” of

each signal is directed to the output. TheAD9833 delivers the MSB of the phaseregister, thus producing a digital signal atthe frequency of the up/down ramp. Thissignal connects to the PSELECT pin onthe AD9834, which controls switchingbetween the phase registers.

Latency in the devices means that yousee the effect of switching between thephase registers on the output only after

INTERFACESIGNALS

IOUT

IOUT

MSBCONSTANTPHASE

AD9833

90˚

0˚

AD9834

PSELECT

F igure 1

DDS device produces sawtooth waveformNiamh Collins, Analog Devices, Limerick, Ireland

Two DDS chips provide a convenient way togenerate sawtooth waveforms.

VDD

IOUT

IOUTBVDD

VDD

DVDD

DVDD

AVDD

VIN

VDD

VDD VDD

VOUT

CAP

DIGITALCONTROLLER

CRYSTALOSCILLATOR

CAP

7

1

10

4

7 18

DGND

DGND

AGND

DGND AGND

9

SCLK6 SDATA

COMP

COMPREFOUT

SLEEP

FS ADJUST

IOUTB

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

10 nF

6.8k

10 µF

8

5

FSYNCFSYNCBFSYNC

MCLK

MCLK_CNTRL

MCLK2_CNTRL

MCLK_CNTRLMCLK_CNTRL

MCLK2_CNTRL

SCLK

SDATASDATA

FSYNC

SCLKCLK_N

MCLK2_CNTRL

MCLK

AD9833 AD9834

2

6 5

14 32

12

1

20

IOUT

SIGN BIT OUT

19

17 200

200

16

13

15FSYNC

SDATA

SCLK

FSYNC

RESET

PSELECT

FSELECT

SDATA

SCLK

11

10

9

8

4

1

F igure 2

This circuit delivers positive- and negative-going sawtooth waveforms.

DDS device produces sawtooth waveform ......................................77

Circuit makes universal VCSEL driver ....................................................78

Circuit level-shifts ac signals ........................80

Interface a serial 12-bit ADC to a PC ........82

Safety device uses GMR sensor..................84


78 edn | July 10, 2003 www.edn.com

ideasdesign

seven MCLK (master clock)cycles. Controlling the MCLKsignals of both devices so thatone MCLK is inactive for anumber of clock cycles canovercome this inher-ent latency. Figure 2 il-lustrates how the two devicesconnect. The connections tothe interfaces of the two de-vices combine so that they canaccept programs from thesame digital controller. TheAD9833 is connected such thatFSYNC is active high; theAD9834 is connected such thatFSYNC is active low. In this way, the con-troller has to control only three signals in-stead of six. The AD9834 is configured sothat the frequency and phase are con-trolled via the pins. This configuration al-lows the digital output from the AD9833to control phase-register selection by sim-ply connecting it to the PSELECT line.Two analog outputs from the AD9834,IOUT and IOUTB, deliver complemen-tary sawtooth waveforms (Figure 3).

A RESET (Pin 11) signal initializes thedevices. This initialization can occur inthe same way for both devices, using thecontrol register. This operation requiresa control word with the RESET bit set to1. The frequency and phase registers ofboth devices are then ready to load withdata. Because of the switching involved increating the sawtooth waveform, its fre-quency is twice that of an equivalent tri-angular waveform:

where FWORD

is the frequency word loadedin both devices.

The AD9834 phase switches between0 and /2. Following instructions in theIC’s data sheet, you should therefore loadPhase Register 0 with 0 and Phase Reg-ister 1 with 0x800 (which corresponds toa 90 phase shift). The AD9833’s phaseis always set to /2, so you should there-fore load Phase Register 0 with 0x800.Once the MCLK of the AD9833 beginsto run and after seven MCLKs of laten-cy, the output of the AD9833 changes be-cause of the /2 phase shift in Phase Reg-ister 0. You can deactivate RESETthrough the control register once the reg-isters are loaded with data. In the samecontrol word to the AD9834, you shouldset the MODE bit to 1, which results in

the selection of the triangularwaveform as the output wave-form, and you should set PIN-SW to 1, so that the pin con-trols phase-register-selectfunction. And, for theAD9833, you should set theOPBITEN bit to 1 to enablethe digital output. You shouldset the DIV2 bit to 1 so thatthe digital output is not di-vided by 2, and set theSLEEP12 bit to 1 because theDAC is not being used. For thesystem to implement the saw-tooth, there must be an offset

between the times when the MCLKs ofboth devices begin to run. You calculatethe offset as follows:

If, for example, Offset10, then theMCLK of the AD9834 should run for 10cycles before the MCLK of the AD9833starts running. From then on, the ICsshould be synchronous. A negative valueof Offset indicates that the MCLK of theAD9833 should start running first.

This Design Idea provides a flexiblemethod for generating a sawtooth wave-form. The frequency is digitally program-mable, and the design requires no externalcomponents to change the frequency. Thefrequency does not change with compo-nent drift over time or temperature.

TIME

600

30

OUTPUT VOLTAGE AT IOUT

(V)

TIME

600

30

OUTPUT VOLTAGE AT IOUTB

(V)

F igure 3

The up ramp of the upper waveforms occurs at the same time as thedown ramp of the bottom waveform.

VCSELs (vertical-cavity surface-emitting lasers) are commerciallyavailable infrared semiconductor

lasers with 850 nm. Short-cavity-length, high-quality Bragg mirrors im-part properties to VCSELs that differfrom those that earlier Fabrey-Perotlasers impart. The emission characteris-tics—optical power, P

, versus diode cur-

rent—shows threshold and operatingcurrents of approximately 3 and 13 mA,respectively, for the Lasermate TSC-M85A416 VCSEL. Such values are typi-

cal for this type of laser (Figure 1). Thecurrent characteristics are nearly inde-pendent of temperature. Thanks to theirlow operating current, effective couplingto multimode fibers, high-speed switch-ing, and low price—about one-thirdthat of a Fabrey-Perot laser—VCSELsmay replace LED light sources in shortfiber-optic links. The MC10EP89ECL coaxial VCSEL driver allowsthe circuit to switch current withless-than-1-nsec rise and fall times (Fig-ure 2). The IC delivers a voltage swing of

P

(60 W/DIV)

I THIVCSEL

(2 mA/DIV)F igure 1

Circuit makes universal VCSEL driverAndrzej Wolczko, Institute of Electronics AGH, Krakow, Poland

A VCSEL has threshold and operating currentsof approximately 3 and 13 mA, respectively.

fF

fSAWTOOTHWORD

MCLK227

= × ,

OFFSET ROUNDFWORD

24 7

28

=

÷

..


ideasdesign

1.6V minimum to a 75 load (Figure 3).The 120 resistor, R

M, limits the am-

plitude of the pulse current, and RP

de-termines the initial polarization currentof the laser. For R

P, the laser practi-

cally switches off during the low state ofthe driver. You must load the MC10EP89

with resistor RL

forproper operation of theIC.You can optimize thevalues of R

Mand R

Pfor

each type and character-istic (individual emis-sion parameters) of theVCSEL you select. Be-cause of the dynamic re-sistance of the laser, thevoltage drop across thejunction varies from ap-proximately 1.9 to 2.2V

within the full current range. Therefore,you should consider this variation whenyou calculate R

Mand R

P. In turning off

the optical power of the VCSEL, you ob-serve some residual emission (tail) in theoptical-pulse response(Figure 4). If the currentfalls to zero (R

P), the

tail is shorter and small-er, but the optical-pow-er amplitude also de-creases.

The oscillogram rep-resents the response of a155-Mbps laser (Figure4). VCSELs for 622 and1250 Mbps arealso availablefrom Lasermate. TheMC10EP89 needs sym-metrical drive; the input

OR/NOR gate works as an asymmetri-cal/symmetrical ECL converter. Thelaser’s good thermal properties elimi-nate the need to provide a complicatedstabilization loop for the optical power.The entire circuit is dc-coupled and op-erates with constant optical power am-plitude for each binary code, and the cir-cuit is insensitive to bit patterns. Aslow-start circuit is unnecessary. Be-cause of the operating speed, you mustcarefully design the pc board accordingto high-frequency rules: Keep connec-tions as short as possible, use surface-mount components, and carefully per-form decoupling, for example. You mustground the metal case of the laser andisolate it from the chip.

MC10EP01

MC10EP89

300

RL150

VDRIVE

RM120

RP300

–5V

VCSEL

ECLINPUT

50

F igure 2

This universal VCSEL driver allows you optimize the circuit forany type of laser diode.

VDRIVE (V)

1 nSEC/DIV

0

–1

–2

–3

–4

F igure 3

The driver in Figure 1 switches 1.6V into 75

with less-than-1-nsec rise and fall times.

P

(ARBITRARYUNITS)

1 nSEC/DIV

100

80

60

40

20

0

RP

1300

F igure 4

These curves show the VCSEL’s response with RP open andRP1300.

AC signals can emanate from manysources, and many of these sourcesare incompatible with the most pop-

ular interface voltages, such as TTL. Atemptation always exists to capacitivelycouple the ac signals because capacitivecoupling strips off the dc level. Capacitivecoupling sometimes doesn’t work, be-cause the coupled signal’s voltage swingsaround ground, so you have to add dcoffset to make the coupled signal com-patible with the interface voltage. Also,the coupled signal contains a dc content,V

DC, which varies with pulse width, and

the dc variation interferes with the inter-

face voltage when the signal swing islarge. This circuit completes the signalinterface by measuring the dc offset,adding appropriate compensation to thecapacitively coupled signal and addingan adjustable-dclevel feature (Figure1). R

1and C

2form a lowpass filter

(f3dB

0.312 Hz) that measures the dccontent of the input signal. The transferequation is the following:

+

–

VOUT

VA

VINR1

5.1k

R310k

R410k

RF10k

RG10k

R25.1k

C2100 F

C12 F

VREF

7.5V

–7.5V

TLCO7X

Circuit level-shifts ac signalsRon Mancini, Texas Instruments, Bushnell, FL

This circuit is a universal level shifter for ac sig-nals; it accommodates any interface standard.

VV R V R R

R R R C sAIN REF

13 1 2

2 3 1 2

= + ++ +

( )

( )( ))

.

+

+

R

R R

RF G

G

1F igure 1


ideasdesign

When R1R

2R

3and R

FR

G, V

DC

transfers to the output signal,VA, because

it is multiplied by 1/2(2)1 or a gain ofone. The output voltage for the same re-sistor values contains V

REF; thus, the out-

put signal is level-shifted by the voltage,V

REF, not V

REFplus the V

DC. When the in-

put signal’s duty cycle changes, ratherthan the output voltage’s changing withduty cycle, the op amp keeps the output-voltage level constant. The gain for the

VDC

must be one, so that it cancels thevoltage shift after ac-coupling. The gainfor the reference voltage can be greaterthan one; for example if R

1R

23R

3and

RF3R

G, the dc content is 1/4(4)1, and

the reference-voltage gain is 3/4(4)3.V

REFcan be positive or negative, so you

can obtain TTL, CMOS, or ECL logic lev-els with this circuit. The time constantformed by C

1and R

4must be large

enough to pass the lowest frequency sig-

nal without distortion. The value of R4

isnot critical, as long as the op amp candrive R

4 without losing too much signal

swing. In some cases, you can size R4

topresent the driving-point impedance youneed to eliminate near-end reflections.The circuit easily couples 400-MHz dataas configured, but the data rate dependson the time constant formed by R

4and

the input impedance of the driven cir-cuit.

Over the years, IC man-ufacturers have devisedvarious ways of effecting

interfaces and paying specialattention to reducing the num-ber of ICs’ interface-I/O pins.The MAX187 is one such de-vice, a 12-bit A/D converter.You can create an interface tothis ADC using serial data-communications techniques.Analog-to-digital conversionand data transfer from MAX-187 require only three digital-I/O lines.You can create a sim-ple interface between theMAX187 and a PC using thecomputer’s Centronics print-er port (Figure 1). You enableor disable the MAX187 by set-ting the SHDN pin (Pin 3) tohigh or low level, respectively.If you leave this pin open, thenthe internal reference(4.096V) becomes dis-abled, and you must apply anexternal voltage reference toREF (Pin 4). Otherwise, thispin connects to a 4.7-F bypass capaci-tor, C

1. The digital data from the

MAX187 transfers to the processing unitone bit at a time by using an externalclock at SCLK (Pin 8).

A complete data transfer requires 13external clock pulses. The first clockpulse’s falling edge latches the first data bit(the MSB) at the DOUT pin (Pin 6). Theoutput data bit changes at the falling edgeof the next external clock, and you canread the serial data bits until the appear-ance of the falling edge of the next clock

cycles. The analog-to-digital conversionstarts when the ADC’s CS pin (Pin 7) goeslow. This pin must remain in the low stateuntil the complete cycle of conversion andsubsequent serial-data transfer has takenplace. A change of state in the DOUT pinfrom low to high level indicates the EOC(end-of-conversion) status. Then, serial12-bit data is available for transfer. Soft-ware controls the MAX187’s operation.The software should be able to generateall the control signals for successful con-version and also should be able to detect

the EOC status. It should alsobe able to generate 13 externalclock pulses to read serial 12-bitdata and convert it into paral-lel data.

The software for the MAX-187’s operation is in TurboC, Version 3.0 (which youcan download from the Webversion of this Design Idea atwww.edn.com). In the code,Port defines the Centronicsport of the PC to which theMAX187 interfaces. Write Portdefines the port for initiatingthe analog-to-digital conver-sion and generating the externalclock pulses. Read Port definesthe port for reading the EOCand serial data from the ADC.After pulling CS and SCLK low,the EOC loop checks for theEOC status. If a valid EOC doesnot appear, this loop remainsoperational. As soon as a validEOC appears, the first of the 13clock cycles appears, whichlatches the first data bit (MSB).

After this action, the routine calls a sub-routine (get_adc()). The subroutine gen-erates the rest of the external clock cyclesto read the 12 bits of serial data. The func-tion also converts the received serial datainto parallel data (adc_val). It converts bymultiplying the previous data by two byshifting adc val to the left by one bit andadding one to the parallel data if the seri-al bit’s value is one. Once the parallel datais available, the function returns the val-ue and displays it on the screen.

132512

11

10

9

8

7

6

5

4

3

2

114

15

16

17

18

19

20

21

22

23

24

SHDN

AIN

REF GND

SCLK

VDD

DOUT

CS

C14.7 F

4 5

2

3

1

MAX187

IC1

5V

C310 F

C20.1 F

8

7

6VIN

P1

F igure 1

Interface a serial 12-bit ADC to a PCDS Oberoi and Harinder Dhingra, GCET, Jammu, India

It’s easy to effect an interface of a 12-bit serial ADC to a PC.


ideasdesign

This Design Idea presents a differen-tial safety device to prevent risks aris-ing from current leakages in house-

hold applications. The proposed circuituses a new method for differential cur-rent sensing (Figure 1). The method en-tails the use of Helmholtz coils and amagnetic sensor based on the GMR (gi-ant-magnetoresistive) effect. The AC004-01 magnetic sensor from NVE (www.nve.com) uses GMR technology (Refer-ence 1). Two Helmholtz coils carry thehousehold’s input current. If no differ-ential current between phase and groundexists at the center of the coils, then themagnetic field is uniform and null. But,in the presence of an unbalanced mag-netic field, corresponding to a leakagecurrent to ground, a differential magnet-ic field appears at the center of the

Helmholtz coils (Reference 2).Thus, the sensor’s output is anonzero voltage that the cir-cuit in Figure 1 amplifiesand compares with a presetreference voltage. The refer-ence voltage corresponds tothe highest allowable leakagecurrent—generally, approxi-mately 30 mA.

The sensor’s output, a dif-ferential voltage, connects viaa highpass filter to an INA118instrumentation amplifier, adevice with high common-mode rejection (Reference 3). This stageconverts the sensor’s differential signalfrom a Wheatstone-bridge arrangementto a unipolar output with an appropri-ate gain figure. This output goes through

a half-wave rectifier and a lowpass filterand becomes a dc signal. If this signal isgreater than V

REF1, then the MOC3041

optotriac turns off, thereby interruptingthe power to the household appliance.

+

–

+

–

+

–

VCC

VCC

J2

VREF1

VCC

VCC

IC1AOPA2234

IC1BOPA2234

IC1INA118

VOUT

J2

J1

2

3

8

31

2

8 4 5

6

7

VREF2

50

220k

1

7

10k

100 nF

3.3k

1M1M

100 nF

100 nF

500k

V–

V+ 58

SEN+ SEN–

4

1

GMRSENSOR

5V

5

IN41486

HALF-WAVE RECTIFIER AND FILTER

100

10 F

12J3

VREF1

VCC

VREF2

3.3k

3k

LM40402.5V

REFERENCEVOLTAGE

1

2

+

–

VREF1

VOUT IC4LM311

VCC

VCC

VCC VOUT2

4 1

5 6 8

7

10M

1.3k

1k

2

3

COMPARATOR

2.5k

10k

Q12N2905

3

2

12

64

IDOD

T1T2

820

MOC3041 RELEASE

RELEASE SWITCH

J4

J5

FILTER

100-kHzFILTER

GND

8.7kS1

1

4

8

4

F igure 1

Safety device uses GMR sensorJ Pelegri-Sebastia and D Ramirez-Munoz, University of Valencia, Spain

This circuit uses a GMR sensor to detect and disable dangerous differential line currents.

F igure 2

The sensor’s output (Channel 4) is zero because the dif-ferential line current is zero.


ideasdesign

Figures 2 and 3 depict two scenarios. TheChannel 1 trace represents the line cur-rent; Channel 2 shows the current circu-lating through the line; and Channel 4represents the sensor’s output, which isproportional to the difference betweenline and ground currents. In Figure 2, thesensor’s output is zero because the cur-

rent difference is null. Figure3 shows a ground current thatgenerates a nonzero magnet-ic field in the sensor. In Figure4, the ground current isgreater than 30 mA. The com-parator changes state, activat-ing the optotriac (Channel 1)

and turning on therelay (Channel 2, 20m A / d i v i s i o n ) .Channel 3 showsthe live current, andChannel 4 shows thesensor’s output (1mV/division).

References1. Daugton, JM,“Giant mag-

netoresistive in narrow stripes,IEEE Transactions on Magnet-ics, 1992.

2.Smith,CH,and RW Schnei-der,“Low magnetic field sensing

with GMR sensors,” Sensors magazine,September 1999.

3. Casas, O, and R Pallas, “Basics ofanalog differential filters,” IEEE Transac-tions on Instrumentation and Measure-ment, 1996.

F igure 3

A ground current generates a nonzero magnetic field inthe sensor (Channel 4).

F igure 4

The ground current exceeds 30 mA. An optotriac and arelay disconnect power to the household appliance.

www.edn.com July 24, 2003 | edn 81


Using a capacitive-cou-pled clip, you can pickup the signal from a

twisted-pair or -wire tele-phone line or from other un-shielded analog lines with-out piercing the insulation.No line test can detect theclip’s presence, and it leavesno evidence of hav-ing been attached. Itneeds no ground return.Youcan fasten the small, insulat-ed pickup plates to the op-posing jaws of an alligator clip for quickand easy attachment. Balanced lines fromthe plates connect to the inputs of a high-impedance differential amplifier (Figure1). For this scheme to have satisfactorysignal-to-noise and frequency-responseparameters, the clip, connecting cable,and amplifier must m be attached paral-lel to the signal wire and must be as long

as is conveniently possible—an inch ormore—and preferably slightly curved tomaximize the coupling capacitance. (Fora twisted-conductor line, the platesshould not be longer than the twist“wavelength” to avoid signal cancella-tion.) You should orient the clip for thecleanest signal output.

The clip, its connecting cable, and theamplifier must be shielded to minimize

interference, typically comprising 60-Hzsignals and their harmonics from power-line fields. The cable should have goodelectrical symmetry and low total capac-itance between conductors and to theshield. Thus, the amplifier must be nearthe clip. The amplifier should have highinput resistance, low current noise, andadequate common-mode rejection.

The clip’s coupling capacitance andstray capacitance and the amplifier’s in-put resistance determine the low-fre-quency cutoff of the detected signal. Straycapacitances in the clip and in its con-necting cable to the shield are generallymuch larger than the coupling capaci-tance. Thus, voltage-divider action re-duces the signal, but the stray componentadds to the capacitance the amplifier’s in-

put sees and reduces the cir-cuit’s noise by the square rootof the signal attenuation. Thenoise reduction accrues fromreducing the needed input re-sistance. Therefore, you gen-erally don’t need the compli-cation of an insulated “boot-strapped” shield. You can fol-low the amplifier with a near-by or remotely located post-amplifier for more gain andbandpass filtering to opti-mize the signal-to-noise per-

formance. A telephone signal has a band-width of approximately 300 Hz to 3 or 4kHz. A sharp highpass cutoff at 300 Hzeffectively rejects power-line noise pick-up. A simple, two-pole, Sallen-Key But-terworth filter works well.You can trim itto provide some high-frequency peakingto obtain the most intelligible signal.

A multiple-pad pickup scheme im-proves noise rejection (Figure 2). The cir-cuit’s arrangement is such that even-numbered pads on one side andodd-numbered pads on the other sidepick up equal noise that produces oppo-site-phase outputs from op amps A andB. Op amp C then sums the signals andrejects the noise. The desired differencesignal, however, appears in-phase at theoutputs of A and B, so both op amps con-

+

–

TO POSTAMPLIFIEROP

AMPR

RVS(CABLESIGNAL)

VCM60 Hz+HARMONICS

C1

CCOUPLING CSTRAYTOTAL

AMPLIFIER RIN

C2

C3

C4

C5

F igure 1

Clip extracts signal from phone lineMaxwell Strange, Fulton, MD

In this equivalent circuit, you should maximize the coupling capacitances, C1

and C2, and minimize the stray capacitances, C3, C4, and C5.

+

–C

+

–B

+

–A

RGAIN

OUTPUT

R

RA

D

B

C

PHONE LINECLIPPADS

F igure 2

A multiple-pad approach produces cancellation of equal noise that the opposed pad pairs pick up. Clip extracts signal from phone line ..........81

Circuit produces variable frequency, duty cycle ........................................................82

Active-feedback IC serves as current-sensing instrumentation amplifier ............86

Create secondary colors from multicolored LEDs................................88



ideasdesign

tribute equally to the output. You canmake a segmented pickup from pieces oftwo-sided pc board with the solid-copperside serving as a shield.You can solder theshield side of the pieces to a suitable alli-gator clip. Alternatively, for longer termuse, you can simply tape them onto thecable. You can use any even number ofpads. the more you use, the better, buteight on each side are sufficient.

The amplifier of Figure 3 uses twoquad J-FET or BiFET op amps. Thanks to

stray capacitance on the input lines of thetest model, a relatively low input resist-ance of 3.3 M is sufficient. Input noiseis mostly the Johnson noise of the 10-Mfeedback resistors. Power-line noise pick-up is usually the bigger problem. Theoutput stages incorporate some highpassfiltering to reject noise below 300 Hz. Theoutput level depends on many factors butis approximately 50 mV. A postamplifier(not shown) can provide more equaliza-tion, filtering, and gain if necessary, as

well as manual or automatic level control.Tests of models of both design ap-proaches use readily available compo-nents and show perfectly clear telephonespeech through a small speaker in thepostamplifier box. The multiple-padpickup system produces noticeably low-er noise, and clip orientation is less crit-ical.

_

+IC1B

_

+IC1A _

+IC2A

_

+IC2C

NOTES:IC1 AND IC2 ARE QUAD JFET OP AMPS.CAPACITORS ARE 20% CERAMIC._

+IC1D

_

+IC1C

_

+IC2B

3.3MD

C

B

A

3.3M

10M

10M

10M

10MINPUT FROMMULTISEGMENT

PICKUP

3.3M

X

X

9V

SHIELD ANDPOWER GROUND

SHIELD

3.3M

3.3M

3.3M

R

150k

R

R150k

0.0015 µF

0.01µF

0.01µF

1 µF

1 µF 1 µF

150k

10k

OP-AMP+POWER

OP-AMPPOWER

220k

R

R

R

150k

OUTPUT

3.3k150 pF

_

+IC2D

R

F igure 3

This amplifier, using the multiple-pad approach effectively reduces power-line-related noise pickup.

This Design Idea shows a simple,low-cost circuit that produces a high-ly accurate variable-frequency and

variable-duty-cycle output (Figure 1).Further, the duty cycle and frequency areindependent of each other (excluding 0and 100% duty cycle). The method de-rives its accuracy and stability from thefact that the output is based on a crystaloscillator and divisions of the oscillator’sfrequency. The design uses only six de-

vices. IC1, a 74HC393 binary ripple

counter, has as its input is the oscillator’soutput frequency. The outputs are the os-cillator frequency divided by two, four,eight, 16, 32, 64, 128, and 256. IC

5Bis cas-

caded with IC1to divide the oscillator fre-

quency further by 512, 1024, 2048, and4096. In this circuit, the divide-by-128 isthe largest division it uses. You could,with a simple wiring change, substitutean unused divider to obtain a different

output-frequency range. The eight inputsof IC

2, a 74HC151 eight-line-to-one-line

multiplexer, connect to the oscillator’sfrequency divided by one, two, four,eight, 16, 32, 64, and 128. Note that theoscillator’s output connects directly to aninput of IC

2. This connection allows se-

lecting the oscillator’s frequency dividedby one. IC

2connects one of the eight fre-

quencies to the input of IC3.

IC3, a 74HC4017 decade counter, di-

Circuit produces variable frequency, duty cycleMark Reed, Texas Instruments, Dallas, TX


ideasdesign

vides the frequency from IC2’s output by

10. Therefore, the maximum output fre-quency for this design is the oscillator fre-quency divided by 10. Each of the decod-ed decade counter’s 10 outputs goes highfor one clock cycle only (Figure2). Using the 10 outputs, a fre-quency’s period dividesinto 10 equal intervals.Youcan use these 10 equal intervalsto generate duty cycles of 10, 20,30, 40, 50, 60, 70, 80, and 90%.For this circuit, the outputs ofIC

3, Q1 through Q8, yield the

end-of-pulse signals for duty cy-cles of 10 through 80%, respec-tively. The start-of-pulse signal isQ9’s negative edge, which occursat the same time as Q0’s positiveedge. Therefore, you can use Q9as start-of-pulse low true, andthe end-of-pulse signals are hightrue. The eight inputs of IC

4, an

eight-line-to-one-line multi-plexer, connect to eight of thenine end-of-pulse outputs fromIC

3. This circuit omits the 90%

duty cycle. You can include the90% duty cycle with a simple

wiring change. If you want to select 0%duty cycle, connect an input to IC

4. If you

select 0% duty cycle, the generator’s out-put is low. IC

4connects one of eight end-

of-pulse signals to IC5.

IC5A

is a binary ripple counter thatserves as a set-reset latch. The start-of-pulse signal sets the latch. The end-of-pulse signal resets the latch. The outputof IC

5is the variable-frequency and vari-

able-duty-cycle output of thesignal generator. For example,if the oscillator’s frequency is 4MHz and IC

2’s C B A inputs

are 0 1 0, then the generatordelivers 100 kHz. If IC

4’s C B A

inputs are 0 0 1, then the gen-erator’s output exhibits 20%duty cycle. If you need to selectfrom more than eight fre-quencies, use a larger multi-plexer than IC

2. Cascade more

or different types of dividers toachieve your frequency needs.You can use a 74HC390 to ob-tain division by five, 10, 50,100, and so on. If you needother duty cycles, cascade74HC4017s to divide the pe-riod by the desired number ofintervals. Finally, if you needto select from more than eightduty cycles, use a larger mul-tiplexer than IC

4.

CLK

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

START-OF-PULSE

END-OF-PULSE10% DUTY CYCLE



END-OF-PULSE 40% DUTY CYCLE






IC3

F igure 2

The end-of-pulse signals from IC4 determine the duty cycle of theoutput waveform.

QAQBQCQDCLR

11/512/1024/2048/4096

109

812

13

IC5A

QAQBQCQDCLR

11

109

812

DGND

7

DGND

DGND

13

IC1B

QA

5V

Y1

QBQCQDCLR

Q0Q1Q2Q3Q4Q5Q6Q7Q8Q9CO

CLK3

45

62

DGNDDGND

GND OUT

EN

1

1

4 5

8

CLK

CLK

IC1AVCC

IC3

12131415 6

5 14

13

15

123

SETFREQUENCY

49

1011

/128

/256

/64/32/16/8/4/2/1

CI

CLK

RST

7

DGND

C B A

OSCILLATOR FREQUENCYDIVIDE BY

00001111

00110011

01010101

10204080

160320640

1280

DGND

ABCD0D1D2D3D4D5D6D7

IC4 IC5B

12131415 6

5

1

2

START OFPULSE

END OFPULSE

1

23

SETDUTY CYCLE

49

1011

80%70%60%50%40%30%20%10%

W

Y

12

3

119

651

10

742

QAQBQC

QD

31

GENERATOROUTPUT

45

6

C B A DUTY CYCLE (%)

00001111

00110011

01010101

1020304050607080

74HC393N

74HC393N

74HC393N

G

ABCD0D1D2D3D4D5D6D7

IC2

W

Y

74HC151N74HC151N 74HC393N

74HC4017N

SET_FREQ_CSET_FREQ_BSET_FREQ_A

SET_DUTY_CSET_DUTY_BSET_DUTY_A

CLR

CLK

G

F igure 1

This circuit produces waveforms of variable frequency and duty cycle. Further, the frequency and duty cycle are independent of each other.


ideasdesign

H igh-speed currentsensing presents a de-signer with some sig-

nificant challenges. Mosttechniques for sensing cur-rent involve measuring thedifferential voltage the cur-rent produces as it flowsthrough a sense element,such as a resistor or aHall-effect device. Thedifferential voltage acrossthe sense element is gener-ally small and is often ridingon a common-mode voltagethat is considerably largerthan the differential voltageitself. Accurate amplifica-tion of the differential voltage requires adifferential amplifier with high input im-pedance, high CMR (common-mode re-jection); wide input-common-modevoltage range; and high, well-definedgain. Traditional instrumentation ampli-

fiers have these features and often servefor low-frequency current sensing, butthey perform poorly at high speeds.High-speed current sensing requires thekind of performance that instrumenta-tion amps provide, but their abilities

must extend to high fre-quencies. Figure 1 showshow high-speed activefeedback amplifiers, suchas the AD8129 and AD-8130 differential receivers,are ideal for these high-speed instrumentation-amp applications. TheAD8129 requires a mini-mum closed-loop voltagegain of 10 for stability,whereas the AD8130 isunity-gain-stable.

Active-feedback ampli-fier operation differsfrom that of traditionalop amps; it provides a

beneficial separation between the sig-nal input and the feedback network.Figure 1 shows a high-level block dia-gram of an active-feedback amplifier ina typical closed-loop configuration.High-speed current sensing uses a re-sistor as the sense element. The inputstages are high-impedance, high-CMR,wideband, high-gain transconductanceamplifiers with closely matched trans-conductance parameters. The outputcurrents of the transconductance am-plifiers undergo summing, and thevoltage at the summing node isbuffered to provide a low-impedanceoutput. Applying negative feedbackaround amplifier B drives V

OUTto a lev-

el that forces the input voltage of am-plifier B to equal the negative value ofthe input voltage at amplifier A, be-cause the current from amplifier Aequals the negative value of the currentfrom amplifier B, and the gm values areclosely matched. From the foregoingdiscussion, you can express the closed-loop voltage gain for the ideal case as:V

OUT/V

IN1R

F/R

GA

V.

Measurement sensitivity in volts peramp is expressed as:V

OUT/I

SENSEA

VR

SENSE.

Minimizing the values of RF

and RG

alsominimizes resistor and output-voltagenoise arising from input-referred current

+

+

–

–

+

–gm

A

+

–gm

B

ISENSE RSENSE

RF

RG

IOUT

VOUT

VSENSE

1

AD8129/30

F igure 1

Active-feedback IC serves ascurrent-sensing instrumentation amplifierJonathan Pearson, Analog Devices, Wilmington, MA

An active-feedback amplifier is ideal for current-sensing applications.

+

–gm

+

–50

1

AD8129

1

33 pF 33 pF50

NETWORK-ANALYZER Rx

NETWORK-ANALYZER Tx

150 nH

100-MHz, THREE-POLE BUTTERWORTHLOWPASS FILTER

50

50

15.8

301

gm

F igure 2

This test circuit produces flat frequency response to 10 MHz.


ideasdesign

noise. Because of the small sense resist-ance and high measurement frequencies,you must minimize parasitic effects in theinput circuitry to avoid measurement er-rors. Parasitic trace inductance in serieswith the sense element is of particularconcern, because it causes the impedanceacross the amplifier’s input to increasewith increasing frequency, producing aspurious increase in output voltage athigh frequencies. Figure 2 illustrates atest circuit with R

SENSE1 and A

V20,

which equates to a measurement sensi-tivity of 20V/A. The three-pole lowpassfilter produces a defined bandwidth and

attenuates spurious responses at the am-plifier’s output arising from input signalsat frequencies outside the desired meas-urement bandwidth. The test circuit’s fre-quency response in Figure 3 shows thatthe expected differential-to-single-endedgain of 20/101, or 14 dB, is flat toapproximately 10 MHz and is downby 3 dB at 62 MHz. Figure 3 demon-strates the effectiveness of the high CMRof active-feedback amplifiers. The com-mon-mode signal at the amplifier’s inputis approximately 50 times greater thanthe differential signal across the sense re-sistor.

F igure 3

The test circuit in Figure 2 exhibits accuratedifferential gain in the presence of large com-mon-mode signals.

It is well-known that simultaneous-ly mixing two primary-color lightsources, such as red and green, creates

a secondary color, such as yellow. Thismixing process commonly occurs in tri-color LEDs. One disadvantage of thismethod of generating a yellow color isthat the LED must use twice the cur-rent because both the red and thegreen LEDs must be on. In battery-pow-ered circuits, the LED indicator’s operat-ing current may be a significant fractionof the supply current, so using the samecurrent to generate both primary andsecondary colors is advantageous. Theoperating-current savings may be signif-icant in telecom-line-card applicationsinvolving thousands of line cards orlarge-panel RGB LED displays. This De-sign Idea proposes a sequencing methodto generate balanced secondary colorsfrom bicolor, tricolor, and RGB LEDs, us-ing only one LED’s operating cur-rent. Advantages include lower pow-er dissipation and more uniform in-tensities between primary and secondarycolors. Using the sequencing method alsoallows a bicolor LED to now producethree colors and keep a simpler pc-boardlayout using two rather than three pins.In addition, you can also produce whitelight with RGB LEDs using the sequenc-ing method.

The method uses the property of im-ages to persist in the human eye for sev-eral tens of milliseconds. If different pri-

mary colors flash sequentially and quick-ly enough from one point, humans seethem as overlapping in time, and thebrain interprets them to appear as sec-ondary colors or even white, dependingon the color components. Experimenta-tion with two or three primary-colorLEDs shows that the flash sequence must

complete within approximately 25 msecor less to produce a solid secondary col-or or white light. In testing for an upperlimit, you can use flash rates to 1 MHz toproduce this effect without degradingsecondary colors. Thus, you can use anyconvenient clock source higher than 40Hz to create secondary colors. Note that

R1 R4VCC

R2

A

B

RC

GC

CA

LED 1BILEDCA R5

VCC

R7

A

C

RC

BC

R6B GC CA

LED 4TRILEDCA

VCC

A

B

RC R3

B

A RC GC

GC

CA

LED 2BILEDCA

LED 3BILED

NOTES:CA=COMMON ANODE.CC=COMMON CATHODE.

F igure 1

Create secondary colors from multicolored LEDsClaude Haridge, Stittsville, ON, Canada

All these LED configurations can produce secondary colors, either by current control orduty-cycle control.

LEDs OFF RED LED ON GREEN LED ON YELLOW

f>40 Hz

5V

0V

5V

0V

A

B

5V

0V

5V

0V

A

B

tGREEN tRED

t<25 mSEC

F igure 2

The waveforms at the top generate yellowfrom green and red; the same result ensuesfrom duty-cycle control (bottom right).


ideasdesign

the primary-color LEDs must be physi-cally close together, such as on a semi-conductor chip, for the eye to properlymix the light. Diffused lenses also allowa wider viewing angle. These combina-tions are commercially avail-able as bicolor, tricolor, andRGB LEDs.

Figure 1 shows the variousLED-circuit configurations,and Figure 2 shows the timingto generate all three colorsfrom bicolor and tricolorLEDs, although using only oneLED’s operating current. Notethat the driver for the bicolorLED must be able to sink and source cur-rent. You may have to provide color bal-ance between the primary-color LEDs toensure that the secondary colors appearproperly. The LEDs have different effi-ciencies and intensities as the human eyesees them, and these parameters needcorrecting. For tricolor LEDs in a com-

mon-anode or -cathode configurationand 50% duty cycle, the correction iseasy to effect by adjusting the current-limiting resistors. Alternatively, you canuse one current-limiting resistor and

then vary the duty cycle to provide thenecessary color balance. For two-leaded,bicolor LEDs, it is easier to adjust theduty cycle to produce the correct sec-ondary color than to use additional cir-cuitry. The waveforms at the bottom ofFigure 2 illustrate duty-cycle control toachieve secondary-color balance for

both bicolor and tricolor LEDs.Using a sequenced bicolor LED to

generate three colors has packaging ad-vantages, particularly when you verti-cally stack several LEDs. Previously,

stacked, tricolor LEDs need-ed to use a through-hole as-sembly, because the middlelead would be inaccessible ifthe devices were surface-mounted. Because the bi-color LED has only twopins, you can vertically stackseveral of them and bendout the leads for surfacemounting. The generation

of secondary colors can also extend toRGB LEDs (Table 1). You can achievecolor balancing by adjusting the cur-rent-limiting resistors or the duty cycle.You can program three pins from a mi-crocontroller’s port to sequence throughthe various primary-color combina-tions.

TABLE 1—SECONDARY COLORS FROM RGB LEDsRed Green Blue Emitted color Notes

0 0 0 None1 0 0 Red0 1 0 Green0 0 1 Blue1 1 0 Yellow Red/green sequenced0 1 1 Cyan Green/blue sequenced1 0 1 Magenta Blue/red sequenced1 1 1 White Red/green/blue sequenced

www.edn.com August 7, 2003 | edn 77


Building a stable noise generatorfor audio-frequency purposes re-quires only a few components. The

circuit in Figure 1 relies on linear-feed-back shift registers and some simple soft-ware. An eight-pin Microchip (www.microchip.com) PIC12C508 controller(IC

2) with a short program generates

pseudorandom noise at its output pin,GP0. A single controller is sufficient forsimple applications. To obtain Gaussian-distributed noise, you can use a numberof identical PIC controllers in parallel ina true realization of the central-limit the-orem. (The central-limit theorem statesthat the sum of an infinite number ofnoise sources has Gaussian distribution,regardless of the individual noise distri-bution of each generator.) Using an infi-nite number of noise generators is im-practical, but 10 to 16 are sufficient in

most cases. And, because the smallestmember of the PIC family is an inexpen-sive chip with low current consumption,the circuit is easy to realize.

All noise generators run the same pro-gram (Listing 1 on the Web version ofthis Design Idea at www.edn.com). Per-fectionists might program each PIC withan individual initial value for the shiftregister, but, because all controllers rununcorrelated with their own internal os-cillators and start out of reset at differ-ent times, this measure is unnecessary.Op amp IC

1Asums and level-shifts the

noise signals. Summing resistors R1

andR

2must have a value of 10 k times the

number of noise generators you use. Theoutput signal of IC

1Afeeds a 3-dB/oc-

tave filter to obtain pink noise. Buffer IC1B

decouples the filter and provides low out-put impedance. The signal amplitude is

approximately 400 mV p-p with a flatspectral distribution of 20 Hz to 20 kHz.Closing S

1or applying a low level at pin

GP4 immediately stops all noise genera-tors and freezes the prevailing signal am-plitude. You can download the PIC soft-ware from the Web version of this DesignIdea at www.edn.com.

Make noise with a PICPeter Guettler, APS Software Engineering GmbH, Cologne, Germany

_

+_

+

GP5/CINGP4/COUT

GP3/MCGP2GP1GP0

GP5/CINGP4/COUT

GP3/MCGP2GP1GP0

234567

PIC12C508P

S1

DISABLE

NOISEGENERATORS SUMMING AMPLIFIER –3-dB/OCTAVE FILTER OUTPUT BUFFER

234567

VOUT

IC3

1

1

2

8

1

8PIC12C508P

ADDITIONALPICs

5V 5V

5V

5V

5V

R1

nR

R

6.8k

10k

3.3k

3k

0.1 µF1 µF

1k 300

0.27 µF 47 nF 47 nF 33 nF

2

3

6

51

8

4

7

PINK NOISE400 mV P-P

R2

nR

220

VSS

VDD

IC2

10k

TL072PIC1B

TL072PIC1A

VSS

VDD

This simple circuit generates Gaussian-distributed noise for audio applications.

Make noise with a PIC ..................................77

Circuit provides linear resistance-to-time conversion ....................78

PC-configurable RLC resonator yields single-output filter ..........................................82

Single IC provides gains of 10 and 10 ..............................................86


F igure 1

78 edn | August 7, 2003 www.edn.com

ideasdesign

Resistance-based transducers, suchas strain gauges and piezoresistivedevices, find common use in the

measurement of several physical param-eters. For applications in which digitalprocessors or microcontrollers serve fordata acquisition and signal processing,the transducer’s response must assume aform suitable for conversion to digitalformat. It is desirable to convert the re-sistance change of such sensors into aproportional frequency or a time intervalso that you can easily obtain an outputin digital form, using a counter/timer.The circuit of Figure1 linearly convertsthe sensor resistance, R

S, into a propor-

tional time period. The circuit is essen-tially a relaxation oscillator, comprising acurrent source, a bridge amplifier, a com-parator, and a flip-flop. The current, I

S,

divides in the paths of R1

and R2

as if thetwo resistors were connected in parallel.Assuming ideal op amps, the circuit func-tions as an oscillator when R

X(R

4R

S) is

greater than R1R

3/R

2.

The circuit produces waveforms at theinput and output of the comparator, IC

2

(Figure 2). T1and T

2are the time intervals

for which the comparator’s output as-sumes levels V

S1and V

S2, respectively.

The output voltage from IC2, with its lev-

els changed via a zener-diodecircuit, serves as clock input toa D flip-flop. From the 7474flip-flop,you obtain a square-wave output that is high andlow alternately for a time pe-riod T4C(R

2R

XR

1R

3)/R

1.

This equation indicates thatthe circuit converts a changein sensor resistance into aproportional time period T with sensitivityT/R

S4C(R

2/R

1).

The following salient featuresof Figure 1 merit mention:

The sensor is grounded;you can easily vary the con-version sensitivity by varyingeither R

1or R

2.

You can adjust the offsetvalue, T

0(about which

changes in T occur becauseof a change in the sensor’sresistance), by changing either R

3or R

4without af-

fecting the conversion sensi-tivity.

The offset voltages of the op amps al-ter T

1and T

2in opposite ways, such that

their overall effect on T(T1T

2) is not ap-

preciable.

Thanks to the current source, theoutput is largely insensitive to noise volt-ages in the line of the current source andto changes that occur in V

S1and V

S2.

Consider the example of converting a

D1

D3

D2

R2

R3

R4

RS(SENSOR)Pt 100)

RX

R1

65.4k

34.3k

C

7 6

FF

52

36

6 3

2

5VZENER

NOTE: D1, D2, D3, AND D4 ARE IN4002s.

2

3

4

7

4

1 µF

IS

IN5287

SENSITIVITYADJUST

OFFSET ADJUST

OUTPUT

2k

1k

D4

V0UTVCC15V

VEE–15V

VCC15V

R5

10kLF411

LF 411

VEE–15V

IC1

IC2

_

+

+

_

Q

QD

CLK

7474

F igure 1

Circuit provides linear resistance-to-time conversionS Kaliyugavaradan and D Arul Raj, Anna University, Chennai, India

T1

T1

T1T2

T1T2

t

t

kIS

kIS

0

0

VS1

VS2

COMPARATOROUTPUT VOLTAGE

COMPARATORINPUT VOLTAGE

F igure 2

These waveforms represent the input and output ofcomparator IC2.

This simple circuit converts a resistance reading to a time period.


ideasdesign

Pt-100 (platinum RTD) sensor in therange of 119.4 to 138.51, which corre-sponds to a temperature range of 50 to100C, into time periods of 10 to 12.5msec. The design is simple. Because thecurrent through the sensor is a fractionof I

S, I

Sshould be low enough to keep the

self-heating error to an acceptably low

level. This design uses an IN5287 currentregulator; it provides an I

Sof approxi-

mately 0.33 mA and has a dynamic im-pedance better than 1.35 M. For a bet-ter current source, you could use a circuitbased on a voltage-regulator IC. In thenext step, with suitable and practical fixedvalues for R

1and C, you adjust R

2until

you obtain the needed sensitivity: 130.82sec/. Following this step, with a fixedR

4, you adjust R

3to obtain the offset re-

quired in the output (T). Figure 1 showsthe values of components for this exam-ple. The resistors all have 1% toleranceand 0.25W rating, and C is a polycar-bonate capacitor.

This Design Idea pres-ents a versatile filter cir-cuit for low-power-

consumption instrumen-tation that you can pro-gram from your PC usingthe parallel port. The cir-cuit uses analog switchesand latches instead of digi-tal potentiometers for thedigital control (figures 1and 2). By running simplesoftware code on the PC,you can configure a singlerobust design to work as alowpass, highpass, or band-pass filter, and you can alsoselect the desired center fre-quency,

0 (Listing 1). Un-

like a similarly controllabledesign (Reference 1), thisdesign is a single-out-put-at-a-time filter.Many power-sensitive sys-tems do not require simul-taneous-filter functions.

The design exploits thefact that a series RLC resonator can pro-vide various filter functions with its ele-ments. Because the design is based on anRLC section, it is trivial to convert the de-sign into a PC-controlled resonator. In

Figure 1, the inductor, LP, is implement-

ed as a PC-controlled synthesized induc-tor. The value of the inductor isL

PC

2R

PR

3R

5/R

2. Here, R

Pcan assume

any of 15 possible values, depending

upon the state of switches S1 through S

4

(determined by PC-port data bits D2through D5). The expression for the fre-quency is

0(R

2/C

1R

PR

3R

5)1/2. You can

thus effectively select 15 frequency values.(This design uses 12 values of practicalinterest.) Data bits D6 through D9 fromthe PC’s parallel port set the state of ana-log switches S

5through S

8. The state of

the switches determines the type of fil-ter.

Figure 3 shows the software-generateddisplay for the circuit. This design uses a

_

+

_

+

C2

S4

S8

S7

S6

S5

S3

S2

S1

10V

D2

OUTPUTTRANSCONDUCTANCE

AMPLIFIERD6 TO D9

D2 TO D5PC

PORT

D3

D4

D5

PC-PROGRAMMABLE

INDUCTOR

10V

10V

R

100k

10k

2.2k

1k

RP

10V

R5

LP

R3

R2

R1

C1VIN

VOUT

F igure 1

PC-configurable RLC resonator yields single-output filterSaurav Gupta, New Delhi, India

A PC-configurable filter uses a synthesizedinductor and analog switches to determinefilter type and center frequency.

TABLE 1—REPRESENTATIVE PORT SETTINGS AND FILTER PARAMETERSFilter type/center Port setting Hex outputfrequency D9 D8 D7 D6 D5 D4 D3 D2 from PCLowpass/9.93 kHz 0 0 1 1 0 1 0 0 X34Highpass/22.9 kHz 1 0 1 0 0 1 1 0 XA6Bandpass/3.16 kHz 0 1 0 1 1 0 0 0 X58Bandpass/37.3 kHz 0 1 0 1 0 1 1 1 X57


ideasdesign

141516171819202122232425

123456789

10111213

OC1D2D3D4D5D6D7D8D

GND

VCC1Q2Q3Q4Q5Q6Q7Q8QEN

74573

IN1D1S1V

GNDS4D4IN4

IN2D2S2V

NCS3D3

IN3

DG308

IN1D1S1V

GNDS4D4IN4

IN2D2S2V

NCS3D3

IN3

DG308

V+IN+Z+NCZ

IN

V

V+IOUT

V+ISETV

NCV

MAX436

1k

100k 10k

2.2k

VIN

R14.7k

C1

0.1 F

50

50

500

VOUT

500

1/2OPA2241

1/2OPA2241

R2

100kR3

100C2

0.1 FR51k

_

+

_

+

F igure 2

You must take the finite on-resistance value ofthe analog switches into account in determiningthe center frequency of the filter.

9.93-kHz bandpass filter for demonstra-tion and testing. Increasing the numberof analog switches can provide a widerrange. Moreover, you could use addi-tional switches for gain programmabili-ty. The 74573 latch provides the interfaceto the PC. Table 1 shows the port/switchsettings for a few frequency and filter-type selections. Note that the analogswitches (DG308) have a finite operatingon-resistance of approximately about110; you must take this resistance intoaccount when you calculate the centerfrequency. For precision instrumenta-tion, other switches are available withoperating on-resistances as low as 30 to50. You can download Listing 1 fromthe Web version of this Design Idea atwww.edn.com.

Reference1. Gupta, Saurav, and Tejinder Singh,

“PC-based configurable filter uses nodigital potentiometers,” EDN, Jan 23,2003, pg 76.This user-friendly configuration screen allows you to determine filter type and

frequency.F igure 3


ideasdesign

Real-world data-acquisition sys-tems require amplifying weak sig-nals to match the full-scale input

range of an A/D converter. Unfortunate-ly, when you configure them as gainblocks, most common amplifiers haveboth gain errors and offset drift. The typ-ical two-resistor gain-setting arrange-ment found in many op-amp circuits hasserious accuracy and drift limitations.With standard 1% resistors, the circuitgain can be off by as much as 2%. Also,the gain can vary with temperature, be-cause each resistor drifts differently. Youcan use monolithic resistor networks forprecise gain setting, but these compo-nents are expensive and consume valu-able pc-board space. The circuits of fig-ures 1 and 2 offer improved performanceand lower cost; they are also smaller. The

single-SOIC approachis the smallestavailable for thisfunction, and the circuitsrequire no external com-ponents. Figure 1 showsan AD628 precision gainblock connected to pro-vide a voltage gain of 10.The gain block itselfcomprises two internalamplifiers: a gain-of-0.1difference amplifier, A

1,

followed by an uncom-mitted buffer amplifier,A

2. You can configure it

to provide different gainsby strapping or grounding the appropri-ate pins.

For a gain of 10, the input signal con-

nects between the VREF

pin (Pin 3) andground, instead of to the op amp’s inputs.With the input tied to the V

REFpin, the

Single IC provides gains of 10 and 10Moshe Gerstenhaber and Charles Kitchin, Analog Devices, Wilmington, MA

+

–+

–

IN

INA2

IN

INA1

15V

47

5

AD628

VOUT

32

1

8

6

VIN

VREF RG

VS

–VG0.1 F

0.1 F

–15V

10k

10k

10k

100k

100k

F igure 1

This circuit has a precise gain of 10 and uses no externalcomponents.


ideasdesign

voltage at the noninverting input ofA

1equals V

IN(100 k/110 k), or

VIN

(10/11). The inverting input of A2

(Pin 6) is grounded; therefore, feedbackfrom the output of A

2forces the nonin-

verting input of A2

to be 0V. The outputof A

1must then also be at 0V. The volt-

age on the inverting input of A1

must beequal to the voltage on the noninvertinginput of A

1, so both equal V

IN(10/11).

Thus, the output voltage of A2, V

OUT,

equals

providing a precise gain of 10 with no ex-ternal components.

The companion circuit of Figure 2provides a gain of 10. This time, the in-put connects between the inverting inputof A

2(Pin 6) and ground. Operation is

similar to that of Figure 1, but A2now in-

verts the input signalby 180. With theV

REFpin grounded, the

noninverting input of A1

is at 0V, so feedbackforces the inverting inputof A

1to 0V as well. Be-

cause A1

operates at again of 0.1, the output ofA

2necessary to force the

inverting input of A1 to0V is 10V

IN. The two

connections exhibit dif-ferent input impedances.When you drive the V

REF

input (Pin 3) for a gain of10, the input impedanceto ground is 110 k; it is approximately50 G when you drive the noninvertinginput of A

2 (Pin 6) for a gain of 10. All

resistors are internal to the gain block, soboth accuracy and drift are excellent.These circuits have gain accuracy betterthan 0.1%, with a gain temperature co-

efficient lower than 5 ppm/C. The 3-dB bandwidth is approximately 110 kHzwith a 10-mV input and 95 kHz with a100-mV input. Although 15V suppliesare appropriate, you may operate thesecircuits with dual supplies from 2.25Vto 18V.

+

–+

–

IN

INA2

IN

INA1

15V

47

5

AD628

VOUT

32

1

8

6

VIN

VREF RG

VS

–VG0.1 F

0.1 F

–15V

10k

10k

10k

100k

100k

F igure 2

This companion circuit to the one in Figure 1 deliversan accurate gain of 10.

V Vk

k

V

OUT IN10

111

100

10= × × +

= IIN INV× × =10

1111 10 ,

Video multiplexers routevideo from severalsources to a single chan-

nel. Low-end consumer prod-ucts use CMOS analog switch-es and multiplexers, such asthe 4066 and 4051. Unfortu-nately, these devices have a se-ries on-resistance that rangesfrom approximately 100 to 1k, a resistance that is notconstant with video level andthat appears in series with thesignal. The traditional way ofsolving this problem is bybuffering the analog-switchoutputs with transistor stages.With this approach, the char-acteristics of the CMOSswitch and the bufferstage degrade video perform-ance. However, if you forgetthe multiplexing action for amoment and consider just thebuffer-amplifier function,you will see thata better approach exists. It must presenthigh enough input impedance to theswitch that a 1-k switch resistance is in-consequential and that variation in resist-ance of the switch with IRE (Institute ofRadio Engineers) level produces no lumi-

nance shifts. Figure 1 shows a configura-tion using high-speed op amps in a video-multiplexing application.

High-speed op amps have plenty ofbandwidth for video applications. By us-ing an op amp that has 20 or more timesthe video bandwidth, roll-off and phaseshift at 6 MHz are negligible. An op amphas high input impedance in the nonin-verting mode. You can terminate it for75 input impedance by connecting asimple resistor. Two equal resistors createa gain of two in the noninverting config-uration. The gain compensates for a 75back-termination resistor on the op amp’soutput. The overall stage gain is thereforeone. Now, consider the multiplexing func-tion. Some video op amps have a “power-down” feature. This feature allows dis-abling the output of the op amp,producing a 0V (0 IRE) black level on itsoutput. Its output can therefore connectin parallel with the outputs of other opamps, because it contributes no lumi-

nance or sync pulses. This fea-ture enables the op amp to op-erate as a video multiplexer.The multiplexer in Figure 1shows a three-position, single-pole rotary switch.This switchcould be a “break-before-make”or an electronic switch-ing system, perhaps with anintelligent infrared interface.

To test the quality of signalspassed through the videomultiplexer, this design usesthe Lucasfilm THX (www.thx.com) test patterns on onevideo input and a high-quali-ty NTSC program source onanother input.When the con-trast/picture test goes throughthe video multiplexer as theactive source, the presence ofthe op amp as a buffer has noeffect on black and white lev-els. No bleeding or blooming

occurs. Any crosstalk results in a visiblebrightening of the center of the picture inthe video-program source, but none oc-curs. You set the brightness level with thevideo multiplexer, not in the circuit. Then,you insert the video buffer into the signalpath. You’ll find that brightness level doesnot change. The brightness setup test isalso an ideal way to test for crosstalk be-tween two video channels. Crosstalkwould show up on the black backgroundas a “ghost” image of the program mate-rial on the inactive channel; however,noneoccurs. No color shifts appear in theSMPTE (Society of Motion Picture andTelevision Engineers) bars with or with-out the video multiplexer in the signalchain. The color-bar patterns would alsoproduce color shifts in the other channelif crosstalk were a factor. Human skin isthe toughest color to get “right,” and anychange in skin tone arising from colorcrosstalk is apparent. No flesh-tone colorshifts occur in the test.

+

–11

12

75

1.3k1.3k

THS4227

10

3

SD 75

+

–15

14

75

1.3k1.3k

THS4227

THS4227

16

2

SD 75

3IN

2IN

+

–

5

6

75

1.3k1.3k

REFERENCE

7

1

SD 751IN

4

13 8

VCC–

VCC

VOUT

Video multiplexer uses high-speed op ampsBruce Carter, Texas Instruments, Dallas, TX

www.edn.com August 21, 2003 | edn 87

ideasdesign

Video multiplexer uses high-speed op amps ....................................87

Single resistor tunes lowpass filter ............88

Simple circuit provides precision ADC interface ................................88

Buck regulator operates without a dedicated clock ............................90

LED driver combines high speed, precision ....................................94

Filament transformer adjusts line voltage ......................................................96


High-speed video op amps make ideal video multiplexers, devoid of videodistortion or other artifacts.

F igure 1



ideasdesign

Any tunable, second-order, activeRC-filter section requires at least twothoroughly matched variable resis-

tors. But the lowpass implementation inFigure 1 provides for wide-range cutoff-frequency control using only a singlevariable resistor, R. In addition to the re-sistor, this filter comprises an operationalamplifier, IC

2, which serves as a unity-

gain buffer; two capacitors, C1

and C2;

and a single-pole, double-throw analogswitch, IC

1, driven by a periodic sequence

of square-wave switching pulses appliedto the SW input. Thanks to the high-fre-

quency periodic switching, you can si-multaneously control thetime constants of both C

1

and C2

in their recharging processes us-ing only R. The approximate voltage-transfer function of the filter, assumingthat the switching frequency is muchhigher than the filter’s cutoff frequency,is:

where P1/(RC

1C

2(1) is the

pole frequency; Q(1)C

1/C

2is the

quality factor; isthe online time ratio(duty cycle); is thepulse width; and T is theswitching period.

Obviously, controllingR results only in varia-tions of pole frequencyand does not affect thequality factor. So, youcan tune this filter over awide frequency range,

preserving its passband gain and ripple.You can achieve a stable value of by us-ing a binary counter. A high-resolution,digitally programmable potentiometer isprobably the most appropriate choice forR in this filter. Figure 2 shows the filter’sfrequency response, simulated in PSpice.This design tunes the cutoff frequencyover 20 Hz to 20 kHz by varying the re-sistor value from 1.2 M to 1.2 k, withC

110 nF, C

21 nF, 0.5, and a

switching frequency of 500 kHz. Usingthis method, you can also implement ahigh-order lowpass filter by cascadingsecond-order sections or by joining themto multiple-feedback structures.

IN

SW

R

OUT

C1

IC1 IC2

C2

Single resistor tunes lowpass filterVladimir Tepin, State Radioengineering University, Taganrog, Russia

This second-order lowpass filter uses a singleresistor to control cutoff frequency.

10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

0

–20

–40

–60

1.2 M 120 k 12 k 1.2 kdB

CUTOFF FREQUENCYF igure 2

By varying one resistor, you can adjust the cutoff frequency over20 Hz to 20 kHz.

Real-world measurement requiresthe extraction of weak signalsfrom noisy sources. High com-

mon-mode voltages are often presenteven in differential measurements. Theusual approach to this problem is to usean op amp or an instrumentation ampli-fier and then perform some type of low-pass-filtering to reduce the backgroundnoise level. The problems with this tra-ditional approach are that a discrete op-amp circuit has poor common-mode re-jection, and its input voltage range isalways lower than the power-supply volt-age. When you use a differential signalsource with an instrumentation-amplifi-er circuit, using a monolithic IC can

Simple circuit provides precision ADC interfaceMoshe Gerstenhaber and Charles Kitchin, Analog Devices, Wilmington, MA

RG

RG

CFILTER

VREF

10k

10k

10k

100k

100k

VOUT

VOUTTO ADC

VCM

VIN

–VS

VS

C2

RF–15V

15VC1

A1

DIFFERENTIALINPUTSIGNAL

IN

IN A2

AD628

IN

IN

0.1 µF

0.1 µF

0.1 µF

4 7

5

632

1

8_

+_

+

An instrumentation-amplifier IC provides precision drive and lowpass filtering for an ADC input.

F igure 1

H ss s

QP P

1

1

2( ) ,=

+

+ω ω

F igure 1


ideasdesign

greatly improve common-mode rejection. However, astandard instrumentationamplifier cannot handlesources greater than thepower-supply voltage or sig-nals riding on high com-mon-mode voltages. Instru-mentation amplifiers usinga single external gain resistoralso suffer from gain drift. Inaddition, lowpass filteringrequires the use of a separateop amp along with severalexternal components. Thisapproach uses up valuableboard space. The circuit ofFigure 1 overcomes all ofthese performance limitations on oneSOIC.

An AD628 precision-gain-block IC isconfigured as a differential-input ampli-fier and a two-pole lowpass filter. Thiscircuit can extract weak signals riding oncommon-mode voltages as high as120V. The precision-gain block direct-ly drives an ADC. A separate V

REFpin is

available for offsetting the AD628 outputsignal so that it is centered in the mid-dle of the ADC’s input range. Al-though Figure 1 indicates 15V, thecircuit can operate with 2.25 to 18Vdual supplies. The V

REFpin can also al-

low single-supply operation; for thispurpose, you simply bias V

REFat V

S/2.

The gain block has two internal ampli-fiers: A1 and A2. Pin 3 connects toground, thus operating amplifier A1 ata gain of 0.1. The output of A1 directlydrives the positive input of amplifier A2.

The first pole of the lowpass filter is a

function of the internal 10-k resistor atthe output of A1, and an external capac-itor, C

1. The gain of A2 is a function of

external resistors RF

and RG. An external

RC time constant in the feedback of A2

creates the second pole.This time constant com-prises capacitor C

2across

resistor RF. Note that this

second pole provides amore rapid roll-off of fre-quencies above its RC“corner” frequency (1/(2RC)) than does a sin-gle-pole lowpass filter.However, as the input fre-quency increases, the gainof amplifier A2 eventual-ly drops to unity and doesnot decrease. So, the ratioof R

F/R

Gsets the voltage

gain of amplifier A2 atfrequencies below its 3-

dB corner and unity gain at higher fre-quencies.

Figure 2 is a graph of the filter’s out-put versus frequency using componentsto provide a 200-Hz, 3-dB corner fre-quency. Note the sharp roll-off betweenthe corner frequency and approximate-ly 10 times the corner frequency. Abovethis point, the second pole starts to be-come less effective, and the rate of atten-uation is close to that of a single-pole re-sponse. Tables 1 and 2 provide typicalcomponent values for various 3-dBcorner frequencies and two full-scale in-put ranges. The values are rounded off tomatch standard resistor and capacitorvalues. Capacitors C

1and C

2must be

high-Q, low-drift units; avoid low-gradedisc ceramics. High-quality NP0 ceram-ic, Mylar, or polyester-film capacitors of-fer the best drift characteristics and set-tling time.

TABLE 1—COMPONENT VALUES FOR 10V P-P FULL-SCALEINPUT FOR A TWO-POLE LOWPASS FILTER

3-dB cornerfrequency

200 Hz 1 kHz 5 kHz 10 kHzCapacitor C2 0.01 F 0.002 F 390 pF 220 pFCapacitor C1 0.047 F 0.01 F 0.002 F 0.001 FNote: Output is 5V p-p; RF=49.9 k, and RG=12.4 k.

TABLE 2—COMPONENT VALUES FOR 20V P-P FULL-SCALEINPUT FOR A TWO-POLE LOWPASS FILTER

3-dB cornerfrequency

200 Hz 1 kHz 5 kHz 10 kHzCapacitor C2 0.02 F 0.0039 F 820 pF 390 pFCapacitor C1 0.047 F 0.01 F 0.002 F 0.001 FNote: Output is 5V p-p, RF=24.3 k, and RG=16.2 k.

8

1

10 100FREQUENCY (Hz)

1k 10k

OUTPUT VOLTAGE P-P (V)

0.10

0.01

RF=49.9k; RG=12.4k. C1 = 0.047 µF; C2=0.01 µF.

F igure 2

The frequency response of the two-pole filterin the circuit of Figure 1 shows a sharp roll-offbetween the corner frequency and approxi-mately 10 times the corner frequency.

Buck regulator operates without a dedicated clockRobert Bell, National Semiconductor, Phoenix, AZ

Most switching regulators relyon a dedicated clock oscillator todetermine the switching frequen-

cy of operation. A dedicated oscillatorcircuit within the power controller usu-ally generates the clock signal. A class ofhysteretic switching regulators can actu-ally operate at a relatively fixed frequen-cy without a clock, even with changing

input-line and output-loading condi-tions. Figure 1 shows a simplified buckregulator operating in continuous-con-duction mode. (The inductor current al-ways remains positive.) The output volt-age,V

OUT, is equal to DV

IN, where D is the

duty-cycle ratio of buck switch Q1

andV

INis the input voltage. The duty cycle,

D, at fixed-frequency operation is TON

/TS,

where TON

is the on-time of Q1

and TS

isthe switching-frequency period, 1/F

S.

Some rearranging and substitution leadsto the expression DV

OUT/V

INT

ON/

(1/FS)T

ONF

S.

Now, look at a regulator circuit, which,rather than using a fixed clock and aPWM, uses a circuit that turns on Q

1for

a time, TON

, that’s inversely proportional


ideasdesign

to the input voltage, VIN

. Figure 2 showsa regulator based on this principle. Thisregulator does not contain a clock oscil-lator, yet it remains at a fixed operatingfrequency even while the input voltagevaries from 14 to 75V. The two main reg-ulation blocks within this regulator arethe on-timer and the reg-ulation comparator. Thecomparator monitorsthe output voltage. If theoutput voltage is lowerthan the target value, thecomparator enables theoutput switch, Q

1, for a

period of time that theon-timer determines.The time period of theon-timer is T

ONKR

ON/

VIN

, where K is a constant(1.3 1010), R is aconfiguration resis-tor, and V

INis the in-

put voltage. If you now substitute TON

inthe previous buck-regulator equations,an interesting result occurs: V

OUT/V

IN

FSKR

ON/V

IN. If you solve for F

S, you ob-

tain FSV

OUT/KR

ON. Because V

OUTre-

mains regulated and the K and RON

terms

are constants, the switching frequencyalso remains constant.

The constant-frequency relationshipholds true provided that the inductorcurrent remains continuous. At lighterloading, the current in the inductor be-comes discontinuous. (The inductor

current is zero for some portion of theswitching cycle.) At the onset of discon-tinuous operation, the switching fre-quency begins to decrease. This reduc-tion is a desirable feature to maintainhigh efficiency as the load decreases, be-

cause switching losses greatly decrease atlower switching frequencies. You derivethe switching frequency in discontinu-ous mode as follows: The peak inductorcurrent I

PV

INT

ON/LV

INKR

ON/LV

IN

KRON

/L, where L is the output-inductorvalue. The output power is P

OUTV

OUT2/

ROUT

LIP

2F/2FK2RON

2/L.Solving for F: F(V

OUT2L)/

(ROUT

K2RON

2). As you can see,the switching frequency variesinversely with the output re-sistance, R

OUT.

Fixed-frequency operationwithout an oscillator offers alow-cost, easy-to-implementstep-down regulator. Youneedn’t worry about anyloop-compensation or stabil-ity issues. The transient re-sponse is fast because the cir-cuit has no bandwidth-lim-iting feedback components.

Depending on the inductor value andloading, the operating frequency remainsconstant for most of the output-powerrange. A desirable reduction in operatingfrequency occurs at low loading levels.

_

+

_

+

_

+

VIN

SD/RON

RON

VCC

RCL D1

RCL

FB

FB COMPLETE

2.5V

2.875V

OVERVOLTAGECOMPARATOR

SD

SD

DRIVER

SW

3k 1

10V

1k

1

BST 2

7

ON-TIMER

REGULATIONCOMPARATOR

START

CURRENT-LIMITOFF-TIMER

8 LM5007

UNDER-VOLTAGELOCKOUT

7V SERIESREGULATOR

START

COMPLETE

300-nSEC-MINIMUMOFF-TIMER

UNDER-VOLTAGELOCKOUT

LEVELSHIFT

BUCK-SWITCH

CURRENTSENSE

THERMALSHUTDOWN

6

5

4 RTN

0.5A

S

R

Q

Q

100k

200k

SHUTDOWN

1 µF

0.01 µF

15 µF

100 µF

0.1 µF

14 TO 75V

3

START

COMPLETE

SET

CLR

VIN

F igure 2

In this buck regulator, the switching frequency remains constant over a wide range of input voltages.

VOUT

VOUTDVIN

L1

D1

DTS

TS

VIN

IL

C1

Q1

I(D1)

I(Q1)

In a typical buck regulator, the output is the switching dutycycle times the input.F igure 1


ideasdesign

Applications such as turbidity meas-urement and densitometry requirecleanly pulsed light sources with sta-

ble amplitudes. The LED driver in Figure1 illuminates retinal neurons in a biolog-ical experiment that has similar require-ments. For a given LED at a given current,the intensity is stable, so switching a sta-ble current is a simple and effective wayto obtain the needed function. The cir-cuit provides current pulses to the LEDwith rise and fall times lower than 500nsec and overshoot lower than 7%. Youcan make the current computer-pro-grammable by replacing the poten-tiometer with a DAC. The circuit com-prises an adjustable, regulated currentsource (IC

1and Q

2), an overdriven dif-

ferential amplifier (Q3

and Q4) acting as

a switch, and a level shifter (Q1) to shift

the TTL input signal to levels needed todrive the differential pair.

Voltage at the wiper of R6

results in an equal voltageacross R

9because of feed-

back to the op amp. Becausetransistor Q

2has a high al-

pha, most of the emitter cur-rent that produces the volt-age across R

9comes from the

collector of Q2. Because al-

pha varies little with tem-perature, this current re-mains stable. Transistors Q

3

and Q4constitute a differen-

tial pair. Depending onwhich transistor is conduct-ing, the emitter of one or theother sources current to thecollector of Q

1. When the

base of Q3

becomes severalhundred millivolts morepositive than the base ofQ

4, current from Q

2

shunts to the 5V power sup-ply. No current flowsthrough Q

4, so the LED is

off. When the base of Q3

isless positive than that of Q

4,

current from Q2

passesthrough the LED. The all-or-nothing switching action re-

sults from the large differential voltageacross the bases. Similar to the case of Q

2,

the collector current in Q4, when it is con-

ducting, is a high and stable percentageof the emitter current. The constant loadthe emitters of Q

3and Q

4 present to the

current source enables the current sourceto operate continuously, allowing the useof a low-bandwidth op amp.

Q1

is a common-base amplifier con-nected in a manner essentially the sameas a TTL-input stage with the exceptionof C

3, the 1000-pF capacitor across base

resistor R4. When the input signal is

greater than 2V, the base of Q1

remainsat 2.5V, and the collector of Q

1rises

enough to ensure that Q4

and the LEDconduct no current. When the input isbelow 0.4V, Q

1’s emitter voltage is low

enough and the base current through R4

is high enough to saturate Q1. This action

holds the base of Q3

low enough to en-sure that all the collector current from Q

2

passes through Q4

and the LED. Whenthe input signal swings positive again, theenergy stored in C

3develops a reverse

bias across Q1’s emitter-base junction to

quickly deplete the stored charge, result-ing in a rapid turn-off. Make sure thatyou don’t exceed the power rating of Q

4.

Take the current and collector-to-emittervoltage into account. Using transistors inTO-92 packages and an LED that drops2V at 50 mA, the circuit in Figure 1 op-erates at temperatures greater than 55Cwith a jumper in place of R

12. If you need

higher currents or use smaller transistorpackages, you may find it necessary to usea finite resistor for R

12to lower the dissi-

pation in Q4

to a safe level.

LED driver combines high speed, precisionRichard Cappels, Mesa, AZ

IC17805

5V TOCIRCUIT

TTL INPUT

POWER-SUPPLYRETURN

OFF

>2V

ON

<0.4V

12V INPUT

5V 5V 5V 5V

5V

5V

C210 µF

1000 pF

C5330 µF

C40.1 µF

Q22N4401

Q42N4401

Q12N4401

Q32N4401

10k

C1100 µF

R11k

(SEETEXT)

R32.2k

R10330

R11330

R910

R610k

R210

R5100k

R84.7k

R7330

¼ LM324

D11N916

D4LED

D21N916

D31N916

+

+

+

R120

C3

R4

_

+

This circuit delivers a stable, precision dose of current to an LED.

F igure 1


ideasdesign

The problem: I couldn’t use myHeathkit oscilloscope in a house Ilived in during the 1960s because my

lab was too far from the power-line inputto the house, and the line drop through

the house was substantial. De-pending on the time of day, the screenwould shrink to perhaps half the normaldisplay size. I checked the line voltage,and it was down to just approximately

100V. I lacked the funds to buy a high-wattage Variac to deal with the problem.

The solution: I had a couple of 12.6Vfilament transformers, rated at 3 or 4A. Isimply connected one of these in my lab,with the primary winding across the acline (Figure 1). Then, I connected thesecondary winding such that one sideconnected to the ac line, and the otherside provided the new, boosted ac line.Because the transformer had a center tap,I could adjust the line voltage in 6.3Vsteps. The beauty of this approach is thatthe transformer handles only the incre-mental power from the slight boost involtage. And the technique uses less spaceand is less expensive than using a Variac.

Note that, by changing the polarity ofthe filament transformer’s output, youcan decrease rather than increase the acoutput. This fact could come in handy insituations in which the line voltage is toohigh, causing incandescent-lamp burn-out. Reduction in lamp life is a functionof approximately the 13th power of theovervoltage (Reference 1). For the long,skinny, and expensive European incan-descent lamps that some bathrooms useas a vertical light source, the lamp-life re-duction can be significant.You can buck,or subtract, the line voltage to increasethe lamps’ life. Even at nominal line volt-age, you can use the method to drop thevoltage to an expensive or particularly in-accessible incandescent lamp.

Reference1. Fink, Donald and Christiansen,

Donald, Electronic Engineers’ Handbook,1975, McGraw-Hill, pg 11-6.

120VINPUT

12.6 V

120+12.6VOUTPUT

12.6V CENTER-TAPPEDFILAMENT

TRANSFORMER

CENTERTAP

Filament transformer adjusts line voltageEE Barnes, Cochranville, PA

You can use a small, inexpensive filament trans-former to buck or boost the ac-line voltage.

F igure 1

www.edn.com September 4, 2003 | edn 89


You can connect seven-segmentLCDs using only a two-wire inter-face (Figure 1). The two-wire inter-

face may be at the field-effect, direct-drive LCD or at a serial interface (such asI2C) that uses an eight-pin microcon-troller. The design in Figure 1 uses an At-mel (www.atmel.com) ATtiny12 micro-controller, IC

1. V

CCcan range from 2.7 to

5.5V. Each digit receives drive from an 8-bit 74HC164 shift register, which pro-vides seven outputs for each of the seg-ments and one output for a decimal pointor a colon. The data input to the shift reg-ister drives the LCD’s common terminal.Software for the eight-pin microcon-troller generates the required symmetri-cal ac square wave between the segmentsand the common terminal (Listing 1,which you can find at the Web version ofthis Design Idea at www.edn.com). Thisgeneration entails shifting the seven-seg-ment data and decimal points to the ap-propriate outputs and setting the shift-register-input/LCD-common-terminalto low at a less-than 1-msec rate. A delay

of 16 msec followed by shifting the samedata complemented, as well as the com-plement of the LCD common terminalwith another 16-msec delay, provides thesecond half of the required ac waveform.Because field-effect LCDs takes tens ofmilliseconds to respond, the rapid data-shifting and display-common changingdoes not affect the displayed image. Youcan use the two 16-msec delays per cyclefor application processing.

Directly driving the segments allowsthe display of not only the numbers zeroto nine, but also any combination of seg-ments and decimal points. You can usethe eight-pin ATtiny12 with a built-in, 1-MHz clock oscillator to produce the de-scribed two-wire signal and to provide atwo-wire I2C application interface. Thededicated use of the microcontroller fordisplay control and its I2C interface freesthe application hardware and softwarefrom timing and resource restrictions.The implemented I2C interface operatesat 0 to 40 kbps and is bit-synchronous.One data protocol allows for the input of

a two-byte binary integer, which convertsto decimal for display. A third byte in theprotocol indicates any decimal points orcolons. This data format allows the easi-est interface from binary measurement orcalculation. A second protocol acceptsfour bytes that directly control the seg-ments and decimal points, allowing thedisplay of a variety of characters andsymbols possible on a seven-segment dis-play. You can download the source codeand hex object file for the ATtiny12 fromthe Web version of this Design Idea atwww.edn.com. The code provides a two-wire I2C interface for a four-digitLumex (www.lumex.com) LCD-S401C-52TR display.

37 36 345 6 7 35 8

3 4 115 6 10 12 13

A B CLK

CLR

QA QB QC QD QE QF QG QH

9821

VCC

VCC

VCC

32 31 299 10 11 30 12

3 4 115 6 10 12 13

A B CLK CLR


9821

VCC

IC6LCD40

27 26 2413 14 15 25 16

3 4 115 6 10 12 13

A B CLK

CLR


9821

VCC

23 22 2017 18 19 21 28

3 4 115 6 10 12 13

A B CLK

CLR


1G 1F 1E 1D 1C 1B 1A 1DP 2G 2F 2E 2D 2C 2B 2A 2DP 3G 3F 3E 3D 3C 3B 3A 3DP 4G 4F 4E 4D 4C 4B 4A COL

CM2CM1

9821

VCC

IC574HC164

IC474HC164

IC374HC164

IC274HC164

401

1234

8765

ATTINY12

SCK

RSTPB3PB4GND

VCCPB2PB1PB0

IC1

BACKLIGHT CONTROL

R110k

C10.1 F

DSD

SRDASRCL

TOINTO

F igure 1

Seven-segment LCD uses two-wire interfaceHans Krobath, EEC, Nesconset, NY

A minuscule 8-bit microcontrollerlets you use a two-wire interface todrive a seven-segment LCD.

Seven-segment LCD uses two-wire interface ..........................................89

Open-collector output provides fail-safe operation..........................................90

Low-battery indicator uses fleapower ......90

Indicator has “electronic lens” ....................92

Thermal switches provide circuit disconnect ............................................98

Buck-boost regulator suits battery operation ........................................100


90 edn | September 4, 2003 www.edn.com

ideasdesign

It is common practice to use digitalopen-collector outputs for controlunits in industrial applications. Using

these outputs, you can switch loads, suchas relays, lamps, solenoids, and heaters.One possible problem inherent to thistype of output stage is a short circuitfrom the output to the supply voltage (of-ten, 24V). This condition can destroy theoutput transistor if it lacks protection.The simplest approach to solving thisproblem is to use a fuse. This method hasa disadvantage, however: You have to re-place the fuse after it blows. APTC (resettable) fuse is often tooslow to protect the transistor under theshort-circuit condition. Another possi-bility is to use a current source as theswitching element. This approach is safeand simple, but it produces heat duringthe error condition. If the power ratingand the cooling of the transistor are in-adequate, the transistor fails because ofthermal overload. The circuit in Figure1 shows another simple approach to thefail-safe protection of such switching de-vices.

The principal function of the circuit isto switch off the transistor if the voltageon the collector is higher than a prede-termined value. Under normal switchingconditions, transistor Q

1should saturate

when it turns on with a voltage lowerthan 0.2V between the collector of Q

1and

ground. If a short circuit exists on theoutput J

1or if the impedance of the load

is lower than specified, the voltage on thecollector of Q

1rises because too little

base-current feed comes from the controllogic (via R

4) to saturate Q

1. If the collec-

tor voltage of Q1

reaches the switchingvoltage on the base of Q

2, Q

2turns on,

and Q1

switches off. You can adjust thisswitching point with the R

1-R

2voltage di-

vider. Now, the voltage on the collector ofQ

1rises to 24V, and the output stays in

the switched-off condition. To reset thecircuit, you must switch the steering out-put from the control logic to low. Now,

the Schottky diode, D1, is forward-biased

and thus discharges C1

and switches offQ

2. If the steering output from the con-

trol logic again switches to the high state,Q

2stays in the switched-off condition

during the charging of C1. If the output

of Q1

is not overloaded, Q1

saturatesagain and stays switched on. If the outputhas a short circuit to the supply or it isoverloaded, then Q

1 switches on only

during the charging of C1; after this time,

Q2

switches off Q1. The maximum load

current depends on the value of R4, the

output voltage from the control logic,and the current gain of Q

1.

FROM CONTROL LOGIC OR MICROCONTROLLER

2

3 IC11

R41.2k

D1BAT85

C147 F

R12.2k

R210k

R3100

Q2BC548

J1 OUTPUT2

1

24V

D21N4004

Q1BD139

F igure 1

Open-collector output provides fail-safe operationSusanne Nell, Breitenfurt, Austria

This circuit provides fail-safe protection of an open-collector output stage.

It is always desirable to use a low-battery indicator that consumes as lit-tle power as possible. For a 9V, 450-

mAhr alkaline battery, a 50-A low-battery indicator can by itself run the bat-tery down in a little more than a year. Bat-tery-powered devices that need to runcontinuously for a long time require bat-tery indicators that consume minimalpower. The circuit in Figure 1, designedfor a 9V battery, uses extra-low power.When the battery is at full charge (9V),

the circuit draws 1.4-A current. At theindication-threshold voltage, 6.5V, thecircuit draws 1 A. Assume that the av-erage operating current is 1.2 A. Thecircuit uses 42 mAhr in a four-year peri-od, less than 10% of the battery’s ratedenergy. A red LED, D

2, flashes periodical-

ly when the battery voltage drops below6.5V. IC

1, an LTC1540, is a nanopower

comparator with a built-in 1.18V refer-ence. A battery-voltage divider compris-ing R

1and R

2, and a positive-feedback

network, R3, feed the positive input of the

comparator. The positive feedback gen-erates hysteresis in the comparator. Thenegative input of the comparator receivesbias from the reference voltage, throughthe R

4-C

1delay circuit.

During normal operation, the voltageat the positive input is approximately1.62V when the battery is at 9V. The out-put of the comparator is at a high state,such that no current flows through D

1

and D2. When the battery voltage drops

Low-battery indicator uses fleapowerYongping Xia, Navcom Technology, Redondo Beach, CA


ideasdesign

below 6.5V, the voltage at the positive in-put drops below the reference voltage atthe negative input. The output of IC

1

switches from high to low, thereby light-ing the LED, D

2. The switching

changes the voltage at the positiveinput to 0.58V and causes C

1to discharge

through D1

and R6. Because the value of

R6

is much smaller than that of R4, the

voltage at the negative input dropsquickly, according to the time constantthat C

1and R

6 set. Once the voltage at the

negative input falls below 0.58V, thecomparator switches back to a high state.This change sets the voltage at the posi-tive input to 1.18V, turns off the LED,and reverse-biases D

1, so the reference

charges C1

through R4. When the volt-

age at the negative input again reaches1.18V, the cycle repeats. The LED’s on-time is a function of C

1and R

6, and the

off-time is a function of C1

and R4. With

the values in Figure 1, the on- and off-

times are 20 msec and 10 sec, respective-ly, at 6.5V threshold voltage.At this point,the LED’s on-state current is (6.5V

1.8V)/2.2 k2.1 mA. The average LEDcurrent is (20 msec2.1 mA)/10 sec4.2A.

R22.2M

R410M

IC1LTC1540

C10.33 µF

R120M

R320M

R620k

R52.2k

D2LED

D11N4148

9V

V+3

4

8

5

6

HYST

REF

7

2 1

GND

_

+

F igure 1

This fleapower low-battery indicator draws just 1.2-A operating current.

The method for implementing an ex-tended-scale meter described in anearlier Design Idea had a conceptual

error: The meter impedance must changecontinuously, not discretely as expressed(Reference 1). You could achieve the de-sired result by using a digital poten-tiometer controlled by an input voltagevia an appropriate interface. But this ap-proach is probably too sophisticated. Fig-ure 1 shows an alternative approach thatneeds only a small and inexpensive mi-crocontroller. The method exploits thefact that a dc meter measuresthe average value of a PWM sig-nal: I

AVGI

PEAK(T

PULSEWIDTH)/(T

PERIOD).

Therefore, you can control the currentthrough the meter by changing the pulsewidth of the PWM signal. The PWM-generating software determines the lawthat governs the change in current in themeter. In the process of creating this soft-ware, you can choose expansion of anypart of the scale (Figure 2).

The transfer function, a, represents alinear meter response; b denotes expan-sion of the beginning of the scale; c indi-cates expansion of the middle of the scale;

and d denotes the expansion of the upperend of the scale. The curves with highslopes in the graph of Figure 2 corre-spond to expanded scales. You can createthe scale patterns by choosing the thresh-old voltages (breakpoints) and slopes.The circuit resembles an “electronic lens”attached to the meter, which magnifiesany chosen part of the scale. The ADC inthe microcontroller of Figure 1 trans-forms the measured input voltage into its

8-bit hex equivalent. The microcontrollerprogram (Listing 1 at the Web version ofthis Design Idea at www.edn.com) readsthe hex value and finds a correspondingpulse width from a table in its memory.Finally, the routine generates the PWMsignal with the given pulse width. Figure3 shows the software flow chart for theprocess.

As an example of the method, calculatethe scale expansion of a 100-A dc me-

IOIPPW

PERIOD

OSC

PB7ADC

6PWM

A

RVPD4

2VIN

C

R

3

5 MC68HRC908JK1

PERIOD

PW

IQ

IP

TIME

19

F igure 1

Indicator has “electronic lens”Abel Raynus, Armatron International Inc, Melrose, MA

An inexpensive microcontroller allows you to expand any portion of the scale of a linear meter.


ideasdesign

ter with a measured-voltage range of 0 to5V. You need to magnify the portion ofthe input from 2 to 3V, from 20 to 70%,leaving 10% at the beginning and 20% atthe end of the scale (Figure 2, character-istic c). Table 1 shows the steps of the cal-culations, which you execute as follows:

1. Choose a number (N) and the val-ues of the measured input voltages, V

IN.

These parameters depend on the desiredaccuracy of the meter scale. As an exam-ple, assume voltages with increments of0.5V for the low slope (Figure 2) and0.1V for the high slope (Table 1, column2). Therefore, N19.

2. Calculate the 8-bit ADC’sdigital output, N

IN, for the se-

lected input voltages (column 3): NIN

(256/5)V

IN51.2V

IN.

3. Transform NIN

from decimal tohexadecimal format (column 4). The er-rors arising from the 8-bit quantizationare insignificant for an analog indicator.

4. Choose the PWM period, T. Thisvalue depends on the rapidity of the in-put-voltage change and should be rela-tively short to prevent needle chatter. As-sume T10 msec for easy Table 1calculations.

5. Calculate the number of timer cyclesfor the PWM period. The accuracy of any

microcontroller’s time intervals is a func-tion of the accuracy of its oscillator fre-quency, which for the MC68HRC908K1depends on the external RC circuit. Thedata sheet for the IC recommends a tol-erance of 1% or less for these componentsto obtain a clock tolerance of 10% or bet-ter. But it is difficult to find a 10-pF1%capacitor, so this design uses a less ex-pensive 5% capacitor and measures theoscillation frequency. According to themicrocontroller manual, the timing com-

ponents R20 k and C10 pF shouldyield a frequency of approximately 4.5MHz. The measured frequency is 5.75MHz. With the timer/counter prescalerset at 64, the timer-clock period is 44.5sec. Hence, you can calculate the num-ber of timer cycles for any time interval asN

t(t in milliseconds)/(44.5103)

22.5(t in milliseconds). Thus, for T10msec, N

10225 or N

HEX$E1.

6. Determine the duty cycle () of thePWM signal for each chosen input volt-age, V

IN, as well as the scale-expansion

pattern (column 5); (IV/I

MAX)100%.

You could either read the current value di-rectly from the diagram in Figure 2 (char-acteristic c) or calculate it for three linearparts of the scale with the following equa-tion: I

VI

TiS

i(V

INV

Ti), where I

Vis the

current for the given input voltage VIN

, ITi

is the current for the threshold voltage VTi

(i1,2,3), and Siis the slope of each lin-

ear portion of the scale in Figure 2 (char-acteristic c). The expressions for the threepiecewise-linear segments are as follows:

7. Determine the pulse width of thePWM signal: PWT (column 6).

8. Calculate the number of timer cy-cles, N

OUT, for this pulse width by using

50

100 100

40 6050

VOLTSb

20 8030 70

100

90

80

70

60

50

40

30

20

10

0

CURRENT(µA)

VIN

0 1 2 3 4 5

bc

a

d

10 900 100

40 60

VOLTSc

2030 70

10 90

0100

40 6050

VOLTSa

µA

µA

µA

µA

20 8030

1

0

4

5

2 3

70

90

10 900 100

40 6050

VOLTSd

01234

01

2

3

1

0

23

45

45

20 8030 70

80

5F igure 2

By selecting slopes and breakpoints, you can expand the bottom (b), the middle (c), or the top (d)portions of a linear meter’s response.

RESET

MAIN

START

YES

YES

YES

INITIALIZATION

CLEAR X-REGISTER

CONVERT VIN TOHEX FORMAT BY ADC

COMPARE VIN WITH VXFROM THE C MEMORY

COMPARE VIN WITH THE NEXT VX

DOES IT MATCH?

ARE ALL VXCHECKED?

VINV0?

SET PWX FROM MEMORY

GENERATE PWMSIGNAL

STOP GENERATINGPWM

F igure 3

This flow chart shows the steps in the scale-expansion process.

V I S A VT T0 010

251 1 1= = = =; ; / .µ

V V I A

S A V

T T2 1080 10

3 270

2 2

2

= =

= −−

=

; ;

/ .

µ

µ

V V IT 33 = ; TT A

S A V

3

3

80100 80

5 310

=

= −−

=

µ

µ

;

/ .

Asingle temperature sensor canprovide an interrupt to a micro-controller when the measured tem-

perature goes out of range. You needmultiple temperature sensors when youhave to monitor more than one hotspot. A microcontroller implements theproper protective action when one ofthe temperature monitors detects anovertemperature condition. It is some-times easier and more cost-effective tosimply disconnect the offending circuitfrom the power supply without involv-ing a microcontroller. A simple ther-mal-protection circuit (Figure 1) in-cludes two temperature switches, IC

1

and IC2, with active-high outputs. Tem-

perature thresholds for these switchesdepend on resistors R

1and R

2, and the

switch outputs connect to the inputs ofa dual-input OR gate, IC

3. OR gates

with more than two inputs are availableif you need more than two tem-perature switches. When excessivetemperature drives either input high,the OR gate’s output switches high,causing an SCR (silicon-controlled rec-tifier) to crowbar the power supply and

blow the fuse. You must take precau-tions to ensure that the SCR does nottrigger on a false gate pulse. Power-sup-ply transients can cause a false high sig-nal at the output of the OR gate and

cause the SCR to turn on. Once trig-gered, the SCR cannot turn off, and thefuse blows. A small RC filter, R

3and C

3,

suppresses any gate transients thatwould otherwise turn on the SCR.

Thermal switches provide circuit disconnectMark Cherry, Maxim Integrated Products, Sunnyvale, CA


ideasdesign

the equation for Nt

and transform thenumber into hexadecimal format(columns 7 and 8).

9. Enter NIN

and NOUT

Listing 1.You can use any microcontroller with

a PWM function and built-in ADC. Theone in Figure 1 has a 12-channel, 8-bitADC and the capability to generate aPWM signal. This microcontroller has 15I/O pins, which are necessary for execut-ing other functions. If your applicationneeds only to effect the meter-scale ex-pansion, then the eight-pin 68HC908-QT2 is probably a better choice. This mi-crocontroller has a built-in oscillator andcosts less than $1.You can download List-ing 1 from the Web version of this DesignIdea at www.edn.com.

Reference1. Raynus, Abel,“Expanded-scale indi-

cator revisited,” EDN, Aug 8, 2002, pg112.T

TABLE 1—EXAMPLE OF MIDSCALE EXPANSION1 2 3 4 5 6 7 8

VIN NIN Pulse width NOUTx (V) NIN (hexadecimal) (%) (msec) NOUT (hexadecimal)0 0.04 2 $2 0 0 0 $01 0.5 25.6 $1A 2.5 0.25 5.6 $62 1 51.2 $33 5 0.5 11.2 $0b3 1.5 76.8 $4D 7.5 0.75 16.87 $114 2 102.4 $66 10 1 22.5 $165 2.1 107.5 $6C 17 1.7 38.25 $266 2.2 112.6 $71 24 2.4 54 $367 2.3 117.8 $76 31 3.1 69.75 $468 2.4 122.9 $7B 38 3.8 85.5 $559 2.5 128 $80 45 4.5 101.25 $6510 2.6 133.1 $85 52 5.2 117 $7511 2.7 138.2 $8A 59 5.9 132.75 $8512 2.8 143.3 $8F 66 6.6 148.5 $9513 2.9 148.5 $94 73 7.3 164.25 $A414 3 153.6 $9A 80 8 180 $B415 3.5 179.2 $B3 85 8.5 191.25 $BF16 4 204.8 $CD 90 9 202.5 $CB17 4.5 230.4 $E6 95 9.5 213.75 $D618 5 250.9 $FB 99 9.9 222.75 $DF

VCC OUTSETOUT

SET

GNDHYST

IC1MAX6510

IC374HC32

C10.1 F

C20.1 F

C30.033 F

R113.7k

R310k

D1EC103A

1

24

5

3

3

6

VCC OUTSETOUT

SET

GNDHYST

IC2MAX6510

R213.7k

1

24

56

TO CIRCUIT

5VPOWERSUPPLY

F igure 1

This thermal-protection circuit includes a crowbar device, D1, driven by thermal switches IC1 and IC2.


ideasdesign

Abuck/boost converter canstep a voltage up or down. Sucha converter is appropriate for

battery-powered applications. Oneapplication derives a regulated14.1V at 1A from 12V solar panelswith 9 to 18V variation. In this typeof battery application, efficiency isan important factor; hence, this de-sign uses an inexpensive synchro-nous-rectifier-based MC33166/7circuit. It is difficult to find abuck-boost controller in themarket. It is even more difficult tofind an inexpensive one with an in-tegrated high-current switch. Oneway to build a buck-boost convert-er is to use a buck regulator with an in-ternal switch, such as the MC33166/7(Figure 1). The negative-polarity outputvoltage connects to the IC’s ground pin,

and a resistor pair divides the 14.1V out-put voltage to 5V for connection to the FBpin of the IC. So, the IC effectively regu-lates an input of V

INV

OUT1814.1

32.1V to an output of 14.1V.The MC33166/7 has a 40V max-

imum switch rating, and it can ac-commodate 95% duty cycle, so it’sadequate for the application. Toimplement synchronous rectifica-tion for better efficiency, the designuses an additional transformerwinding and a MOSFET. The aux-iliary winding provides bias volt-age to turn on the MOSFET whenthe switching-node polarity turnsnegative. Note that the synchro-nous rectifier is an important fac-tor in the efficiency of this circuit,because the input-to-output ratiois approximately 1-to-1. So, the

duty cycle is approximately 50%, whichmeans that the MOSFET conducts forhalf the switching-frequency period.

5V

COMP

VIN

GROUND

SWITCH

FB

INPUT OUTPUT

MC33166/7

F igure 1

Buck-boost regulator suits battery operationKahou Wong, On Semiconductor, Phoenix, AZ

This inexpensive buck-boost controller uses synchronous recti-fication for high efficiency.


Most manufacturers recommendthat you don’t change lithium-ionbatteries at temperatures lower

than 0C or higher than 50C. You canmonitor both thresholds by adding athermistor and dual (window) compara-tor to a lithium-ion battery charger (Fig-ure 1). Set the low-temperature trip pointat 2.5C and the high-temperature trippoint at 47.5C. A precision voltage ref-erence is unnecessary, because the com-parator’s resistor network is ratiometric,so variations on the supply voltage, V

BUS,

do not affect the trip thresholds. By driv-ing the charger’s enable input, EN, thecomparators’ open-drain outputs ensurethat charging is inhibited when the bat-tery temperature is out of range. As an al-ternative, you can substitute a dual com-parator with push-pull CMOS outputs,

such as the MAX9032, if you also add atiny, SOT-323 dual diode (the dashedlines in Figure 1). The dual comparatorand the MAX9032 are available in SOT-23 packages, and both offer built-in hys-teresis of 2 or 4 mV, respectively.

IC2

is a single-cell lithium-ion batterycharger that can derive its power directlyfrom a USB port or from an external sup-ply as high as 6.5V. The 0.5% accuracy ofits battery-regulation voltage allows max-imum usage of the battery’s capacity. Thecharger’s internal FET delivers as much as500 mA of charging current, and you canconfigure its SELV input for charging a 4.1or 4.2V battery. The SELI input sets thecharge current to either 100 or 500 mA,and an open-drain output,CHG, indicatesthe charge status. For near-dead batteries,a preconditioning capability soft-starts the

cell before charging. Other safety featuresinclude continuous monitoring of voltageand current and initial checking for faultconditions before charging.

_

+

_

+

GND

BATTERY PACKNTC THERMISTOR(SUCH AS FENWAL

ELECTRONICS140-103LAG-RB1)

10k AT 25oC

HOT (47.5oC): 3.97kCOLD (2.5oC): 28.7k

GND

OUTA

OUTB

DUAL SCHOTTKYDIODE, SOT-323

CMSSH-3A

NOTE: YOU SHOULD ADD THE DUAL SCHOTTKY DIODEIF YOU SUBSTITUTE A CMOS-OUTPUT DUAL COMPARATOR, SUCH AS THE MAX9032.

GND

SELI

BATT

SINGLELI-ION

BATTERY

500 mA

100 mA

OUTB

INB–

INB+

INA–19.1k1%

13k1%

18k1%

10k1%

INA+

IC1LMX393

IC2MAX1811

VCC

VBUS

OUTA

IN

SELV

CHG

EN

270

10kOPEN-DRAIN

OUTPUTS

100k

0.1 µF4.7 µF

2.2 µF +

EN

F igure 1

Dual comparator thermally protects lithium-ion batteryMike Hess, Maxim Integrated Products, Sunnyvale, CA

While charging a lithium battery from a USB port, this circuit provides thermal protection for the battery.

Dual comparator thermally protects lithium-ion battery..........................91

Lowpass filter discriminates step input from noise ....................................92

Voltage-to-current converter makes a flexible current reference ............96

Circuit forms single-pulse voltage multiplier ..........................................98

Feedback circuit eliminates CCD-driver delay mismatch......................100

Publish your Design Idea in EDN. See the

What’s Up section at www.edn.com.



ideasdesign

Numerous applications exist in in-dustry, particularly with controlsystems, in which it is desirable to

remove all but the lowest frequency com-ponents from a signal to effectively yielda dc voltage. This voltage may, for exam-ple, serve as a setpoint to a PID controllerin a process-control or an HVAC appli-cation, in which the cable that is carryingthe analog signal is exposed to a widespectrum of noise, including low-fre-quency noise components from varioussources. These sources could includevariable-speed drives, ballasts, transientsfrom switching gear, and motors. Inmany cases, noise reduction using a con-ventional lowpass filter can create adverseeffects in the response time of the system,even if you use a multipole filter.As an al-ternative, the circuit of Figure 1 is ideal-ly suited to provide extensive noise re-duction for applications such as thesewithout impairing a system’s ability totrack rapid changes in signal level. Theconcept involves a lowpass filter with aslewing mechanism that has significantperformance advantages over other non-linear-lowpass-circuit topologies, givenits ability to discriminate step changes insignals from noise.

The basic operation of the circuit is tomomentarily increase the corner fre-quency of the lowpass filter formed by R

6

and C3, using an analog switch, IC

1, upon

detection of a step change in signal, al-lowing V

OUTto track V

INwith little delay.

IC1

has an on-resistance of about 100,so when it closes across R

6, the corner fre-

quency of the circuit changes from 0.016Hz to approximately 160 Hz, which isample bandwidth for the target applica-tions for this circuit. IC

2B, along with R

4,

R5, and C

2, operates as an error amplifi-

er with a corner frequency off

CERR1/2R

5C

21.59 Hz. The amplifi-

er generates an error signal, VERR

, thatIC

2Ameasures in reference to V

OUT. IC

2A

acts as a floating window comparatorthat places the lowpass filter into slewmode when V

ERRexceeds the predeter-

mined threshold that zener diode D3

es-tablishes. For values of V

ERRthat are

greater than VOUT

, diode D2

conducts,causing the noninverting input of IC

2Ato

track this signal. IC2A

compares the sig-nal to a threshold voltage of approxi-mately V

OUT5.2V at its inverting input.

When a negative-step change (VIN

V

OUT) to the input, V

IN, is of sufficient

amplitude such that VERR

becomes ap-

proximately 5.7V (accounting for thebarrier potential of D

2), IC

2A’s output

switches high. This action activates IC1,

causing a short circuit across R6, thus al-

lowing VOUT

to track VIN

.For values of V

ERRbelow V

OUT, the ac-

tion is similar, except that the inverting in-put of IC

2Atracks V

ERRthrough D

3and D

4,

and the comparator’s output toggles highat the point at which V

ERRis approxi-

mately 5.2V below VOUT

. Although theasymmetry in the window comparator’sperformance is not of great significance,you could realize improved symmetry byreplacing D

2with a Schottky diode, which

has a lower barrier potential. The com-parator’s trip points, along with the dcgain of the error-amplifier stage (IC

2B)—

determined by the ratio R5/R

4—establish

the upper and lower deadband of Figure1. With the values shown in Figure 1 thecircuit triggers to slew in response to neg-ative-step changes in V

INas small as

0.260V and positive-step changes that areas small as 0.285V. You can realize bettersensitivity by reducing the zener voltageof D

3or by increasing the ratio R

5/R

4and

ensuring that the error-amplifier stageprovides adequate roll-off. The roll-offmust ensure that noise levels that may ex-

IN/OUT OUT/IN

VDDVSS

12V

IC1TC4S66F

R310k

R4500k

R210k

R510M

R110k

D11N914

C310 F

TANTALUM

C20.01 F

D21N914

D41N914

D51N914

D31N5230

C10.1 F

R61M

+

CONT

VIN

IC2ATL074

_

+

12V

12V

IC2BTL074

_

+FC=0.016 Hz

12V

4.7V

VERR

_

+

VOUT

IC2CTL074

F igure 1

Lowpass filter discriminates step input from noiseEric Desrochers, Aircuity Inc, Newton, MA

This unique lowpass-filter design providesgood noise reduction and retains the abili-ty to track rapid changes in signal level.



ideasdesign

ist in a given application cannot triggerthe circuit into slew mode.

Another important parameter to con-sider when choosing component valuesfor the error- amplifier stage is the step

response of that circuit, becauseit directly impacts the overallsettling time of the lowpass filterwhen it encounters stepchanges in signal. To be con-

servative, choose valuesfor R

5 and C

2such that

three times the RC timeconstant they form iswell within the settlingtime desired for the low-pass filter. For example,with R

510 M and

C20.01 F, 30.3 sec.

This case represents the approx-imate worst-case delay to the re-sponse to a step change in V

IN

that is outside the deadband ofthe circuit. In practice, however,the delay is much smaller for stepchanges in V

INthat are larger in

magnitude, given the first-ordernature of this circuit. Figure 2 il-

lustrates the response of the lowpass-fil-ter design to a 600-mV step change in V

IN.

The graphic also illustrates the circuit’ssignificant filtering capabilities on a se-vere, 30-Hz, 640-mV p-p noise compo-nent superimposed on the signal. An ac-coupled view of the filter’s performanceat steady state illustrates more than 65 dBof attenuation at 30 Hz (Figure 3).

F igure 2

The circuit in Figure 1 has good step response, evenwith a nasty 640-mV p-p, 30-Hz noise term superim-posed on the input.

F igure 3

This ac-coupled view illustrates more than 65 dB ofattenuation at 30 Hz.

VOUT

VIN

VOUT

VIN

The voltage-to-current converterin Figure 1 can both source and sinkcurrent. The circuit is more flexible

than some traditional current referencesthat require different topologies for cur-rent sourcing and sinking. Also, you caneasily adjust the value of the current ref-erence by simply adjusting the circuit’sinput voltage. Performing a simple nodalanalysis generates the followingequation:

You typically set R1equal to R

2.

The output current is a functionof R

3and the gain of the instru-

mentation amplifier. Note thatcapacitor C

1stabilizes the circuit.

In this example,R310 M, and

the instrumentation amplifier’sgain is unity. Varying the input,V

IN, by 10V yields a current-

output range of 1 A. Per-forming a more detailed nodalanalysis on the circuit in Figure 1yields the following equation:

where VOS1

and VOS2

are the offset voltages

of IC1

and IC2, respectively, I

B2is the in-

put-bias current of IC2, and A

IC2is the

gain of IC2.

This second equation is useful in un-derstanding error sources and, conse-quently, can aid in selecting the compo-nents that are best suited to anapplication. For example, for a nano-ampere current reference, you should

consider the error that the in-strumentation amplifier’s biascurrent generates. The example inFigure 1 uses the INA121P FET-input instrumentation amplifierto minimize the input-bias cur-rent. A milliampere reference, onthe other hand, would focus moreon the input offset voltage of theinstrumentation amplifier. Ingeneral, you can neglect the errorthat the offset voltage of the opamp generates if you use a preci-sion, low-offset amplifier. How-ever, resistor-mismatch and in-strumentation-amplifier gainerrors are inevitable, regardless ofthe application.

–

+IC1

VIN

––

++

OUT

INRGRGIN

3812 IC2

INA121P

0.01 F

0.01 F

0.01 F

15V

–15V

7 V+

0.01 F

0.01 F15V

7 V+

15VVREF4 V–

4 V–6

5

6

R310M

R21k

R11k

OPA277P

C1

NOTES: AIC2=1+ 50 kRG

IS THE GAIN FOR THE INA121P.

IN THIS EXAMPLE, RG =, SO GAIN AIC2=1.

LOAD

3

2

Voltage-to-current converter makes a flexible current referenceArt Kay, Texas Instruments, Tucson, AZ

This current reference delivers an outputthat’s a linear function of the input voltage.

IR V

R R AOUTIN

IC

2

1 3 2

= .

F igure 1

IR V

R R A

CURRENT TERM

R V

R R A

OUTIN

IC

OS

2

1 3 2

2 1

1 3

=

+

IIC

OS OS

ICB

R V

R R

R V

R R AI

2

1 2

1 3

1 1

1 3 22+ + +

,

ERROR TERM


ideasdesign

It is sometimes necessary for a mi-crocontroller to generate a pulsewhose voltage is higher than the pow-

er-supply voltage of the microcontroller.The circuit in Figure 1 allowsyou to generate 14V pulses froma 5V power supply. An adaptation of thecircuit provides a 5 to 12V programmingpulse for programming the fuse bits inAtmel (www.atmel.com) microcon-trollers (Figure 2). The approach is eco-nomical, in that it combines the voltage-multiplier and pulse-amplifier functions.Moreover, the technique benefits fromthe absence of noise that would arisefrom a continuously running switchingpower supply. In Figure 1, when the mi-crocontroller’s output is low, C

1and C

2

charge in parallel to nearly 5V. When themicrocontroller switches to 5V, it effec-tively makes the capacitors appear in se-ries with the 5V pulse, resulting in a pulseapproaching three times the power-sup-ply voltage at the output. C

1charges

through D1, and R

1limits the

charging current from the mi-crocontroller’s output to a few mil-liamperes. C

2charges through D

2and R

3.

During the output pulse, C1

must sup-ply the base current for Q

1and Q

2, as well

as the load current. Because the voltagedrop across the diodes decreases as cur-rent through them diminishes, after acharging time of several time constants,the diode drop is only a couple of hun-dred millivolts. Therefore, pulses of near-ly three times the power-supply voltageare possible. When the pulses are contin-uous or when they occur within a coupleof time constants of power application,diode drops of approximately 1.5V sub-tract from the output. Additional lossescan arise from voltage drops across the re-sistance of the microcontroller and satu-ration losses in the transistors.You can re-duce the saturation losses by reducing thevalues of R

2and R

4, but be aware that re-

ducing these values increases the drooprate of the output pulse. For some appli-cations, you could omit D

1and replace D

2

with a resistor, but the result would be longer charging and faster dischargingfor the capacitors. These trade-offs are

acceptable for some applications.The circuit in Figure 2 provides a 5 to

12V programming pulse for Atmel ATVmicrocontrollers for the couple of hun-dred milliseconds the ICs require. Be-cause the output during the time the mi-crocontroller’s output is low needs to be5V, you omit the second transistor andtake the output directly from the cathodeof D

2. Because the output voltage needs

to go to only 12V, C2

charges from a volt-age divider. C

2charges to only 2V, which

then appears in series with the 10V from

the series combination of C1

and the out-put of the microcontroller. You get no“free lunch” with this circuit. If the pulseinitiation occurs before R

3and R

4suffi-

ciently charge C2

(60 k100 F6sec), the voltage is lower than intended.You can reduce the charge time of thecircuit by reducing the values of the ca-pacitors. C

2has the most effect because

of the high-resistance charging path.However, reducing the capacitor valuesmakes the output pulse droop morequickly.

MICRO-CONTROLLER

5V

R11k

R256k

R356k

R556k

R456k

D11N916

D21N916

Q1 Q2C1100 F

C2100 F

+ +

2N2907 2N2907

5V

0V

14V

0V

F igure 1

Circuit forms single-pulse voltage multiplierRichard Cappels, Mesa, AZ

This simple circuit provides single pulses of 14V from a 5V power supply.

MICRO-CONTROLLER

5V

R11k

R2100k

R3100k

R4150k

D11N916

D21N916

C1100 F

C2100 F

+

+2N2907

5V

0V

12V

5V

F igure 2

This variation on the circuit of Figure 1 supplies fuse-programming pulses for Atmel ATVmicrocontrollers.


ideasdesign

In a CCD (charge-coupled device),packets of charges shift across the ar-ray. The transistor array, also called a

bucket-brigade shift register, receivesdrive from a dual-phase clock signal.Dual-phase clock signals comprise twosynchronized clock signals that are 180out of phase. High peak-output-currentCCD drivers can buffer the logic-levelclock signals and turn them into high-voltage and high-peak-current signals todrive the heavily capacitive gates of themany CCD transistors. Because of thespeed mismatch of CCD-drivers’ n- andp-channel FETs, the turn-on and -offdelay times are poorly matched. Figure1 shows the outputs of one such currentCCD driver, Intersil’s EL7212 (www.elantec.com), with a dual-phase inputclock. The overlap in the output stemsfrom the turn-on and -off delay mis-matches of the EL7212.

In a low-resolution system with alower clock frequency, the delay mis-match is an insignificant part of theclock period. As CCD scan rate in-creases, the mismatch becomes alarge part of the clock period. You needa new approach to correct the CCD-driver delay mismatch. Figure 2 showsa circuit that uses amplifiers to sense thedelay mismatch and correct it. BecauseV

OUTand V

OUTare 180 out of phase, if

their turn-on and -off times coincideperfectly, the voltage between R

4, R

7, and

C2

is 1/2VCC

. Amplifiers IC2A

and IC2B

compare voltage on C2

with the 1/2VCC

reference voltage and adjust the voltagebetween R

3and R

6. IC

2Aprovides the

phase inversion, and IC2B

is the high-dc-gain error-correction amplifier. Theoutput of the error amplifier drives R

3

and R6, which shift the voltage offset of

the incoming clock signal. When the off-set-voltage level of the input clock sig-nal shifts, the time at which the CCDdriver is triggered also shifts. IC

2Aand

IC2B

guarantee that the proper offsetvoltage goes to the input clock signals sothat the delay mismatch cancels. D

1and

D2

rectify the input clock signals andcreate the supply voltage to theIC

2Aand IC

2Bamplifiers. When the

input signals are removed, the power to

the amplifiers shuts off, and the error-correction loop deactivates to preventoutput oscillation with no inputs.

IC1B

_

+

IC2B

EL5220

EL7212

_

+

IC2A

IC1BVIN

VCC

VCCD1

5k

3 4

7

C40.1 µF

C10.1 µF

C20.1 µF

C30.1 µF

D2

R250

R550

R35k

R65k

R45k

R75k

R95k

R115k

R105k

R15k

R8VIN VOUT

VOUT

F igure 2

This circuit can correct the mismatch in turn-on and -off delays in a CCD-driver IC.

F igure 3After the circuit in Figure 2 doesits job, the turn-on and -off wave-forms line up nicely.

F igure 1 In a CCD driver, a mismatch mayoccur in the turn-on and -offdelay times.

Feedback circuit eliminates CCD-driverdelay mismatchMike Wong, Intersil-Elantec, Milpitas, CA



Designing and testing embeddedhardware can be frustrating if youhave to rely on somebody else’s per-

haps-unready firmware to test your hard-ware. Often, hardware is ready for test-ing before debugging and system firm-ware are available from software devel-opers. Microprocessor emulators are so-lutions but are often expensive, hard touse, and sometimes inappropriate for useby hardware developers, who often justneed to read and configure registers ondevices on their boards. If you are notprimarily concerned with your proces-sor’s bus performance and need simpleread and write access to registers on chips

on your board to configure and test hard-ware, then building a simple processor-bus emulator, such as the one in Figure1, may be an attractive option. The sim-ple emulator shown uses an easy-to-useBasic Stamp microcontroller (www.parallax.com) on a carrier board and asmall CPLD to emulate a 16-bit “ISA-like” I/O bus. Figure 2 shows the timingparameters for the bus (Figure 2a showswrite-cycle timing; Figure 2b shows read-cycle timing). Note that the bus emulatorruns much slower than a “normal”processor bus but is useful to read andconfigure registers that you need to testhardware. This design uses the 16-bit

ISA-like bus mainly for illustrative pur-poses; you could emulate almost anyprocessor bus with a similar setup.

The simple emulator consists of twoparts, the hardware (Figure 1) and theBasic Stamp firmware (Listing 1, whichyou can download from the Web versionof this Design Idea at www.edn.com).You must connect the emulator itself toa 5V power supply and a PC with a key-board, monitor, and serial port, and youload any simple terminal-emulator soft-ware, such as Hyper Term. The serial pro-gramming cable you use to program theBasic Stamp also communicates with theterminal-emulator software by insertinga switch, S

1, that lets you disconnect or

connect the DTR/ATN connection.When the switch is closed, you can pro-gram the Basic Stamp, and, when it isopen, you can use the terminal-emulatorsoftware to communicate with the BasicStamp. You enter commands on the key-board, and the results appear on themonitor. The emulator connects to theboard and devices to test and configure,such as a custom FPGA, through theboard’s normal processor bus. (You needto either socket the original processor orprovide a test port on the board.) Youtristate the original processor or removeit from the board to use the emulator.

The Basic Stamp firmware emulatesprocessor-bus cycles by changing the ap-propriate control signals on its pins. The

5 ADDPIN6 ADDCLK7 DATAPINO8 DATACLKO9 DATAPINI10 DATACLKI11121314 LATCHENB15 DIR1617181920

P0P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15

BASIC STAMP 2 CARRIER BOARD

21 VDD23 GND22 RES L

1 TX2 RX3 ATN4 GND

BASIC STAMP 2

SERIALCOMPORT

GNDDTRTXRX

4 2 3 DSR 6 7 RTS5

BS2PROGRAMMING

CABLE

PC

ISP

16-BIT SREG

DO0 ... DO15

DIO ... DI15

AO ....... A15

16-BIT SREG

16-BIT SREG

DI0

D015

LE

CPLD (LATTICE ISPMACH 4128V)

SA[15:0]

EMULATED-PROCESSORBUS HEADER

D0.....D15

DATA

IOR

IOW

BALE

ENDIR

VOL_REG 3.3V

5V

DB9

S1

F igure 1

Simple emulator speeds testingNavdhish Gupta, Chicago, IL

A simple emulator uses a Basic Stamp microcontroller and a small CPLD.

Simple emulator speeds testing ................67

Software snippet provides improved subset-sum algorithm................68

IC removes nonlinear temperature effects........................................70

Motor controller uses fleapower................................................72



ideasdesign

CPLD uses shift registers to interface theserial address and data into and out ofthe Basic Stamp to the emulated 16-bitparallel address- and data-bus signals.The CPLD also “conditions” the controlsignals from the Basic Stamp to the em-ulator header by performing logic-threshold conversion through CPLD I/Obuffers. Listing 2, also avail-able from the Web version ofthis Design Idea at www.edn.com, showsthe Verilog code for the CPLD. Note that,although the control signals IOW, IOR,BALE, and ENDIR come from the basiccode firmware and the Basic Stamp pinsand are conditioned through the CPLD;they could come directly from a simplefinite-state machine in the CPLD if yourdesign requires more realistic bus timing.The Lattice (www.latticesemi.com) isp-MACH 4128V CPLD is a 5V-tolerant de-vice whose inputs you can safely drivewith voltages as high as 5.5V. It also sup-ports as many as 64 I/O lines and is in-system-programmable through theIEEE-standard 1532 interface. These fea-tures make the CPLD a good choice foruse in the hardware implementation ofthe logic needed in the emulator.

ADDCLK

ADDPIN SERIAL ADD SHIFTED INTO ADD-SHIFT REG

SERIAL ADD-SHIFTED INTO ADD-SHIFT REG

SERIAL DAT SHIFTED INTO DAT-SHIFT REGHI-Z

PARALLEL SYSTEM ADD VALID

PARALLEL SYSTEM ADD VALID

RDATA SERIALLY SHIFTED INTO STAMP

LATCHED IN SR

DATA VALID

DATACLKO

DATAPINO

SA[15:0]

WRDATA[15:0]

BALE

IOW

DIR

ENDIR

(a)

LATCHENB

ADDCLK

ADDPIN

BALE

ENDIR

SA[15:0]

IOR

DATACLKI

WRDATA[15:0]

DIR

DATAPINI

(b)

LATCHENB

F igure 2

The simple emulator uses Basic Stamp signals for write-cycle timing (a) and read-cycle timing (b).

The subset-sum problem is one of the most frequently occurring NP (nondeterministic, polynomial-

time)-complete) problems. It askswhether a subset of numbers in a set ofpositive integers adds up exactly to a giv-en value. A relaxed version of the prob-lem tries to identify a subset of numbersthat adds up to a maximum value nogreater than a given value. This problemarises in transportation, network design,scheduling, logistics systems, robotics,and many other areas. The problem per-mits you to develop and illustrate thepower of different algorithmic tools. Theproblem is as follows:

Given a set of positive integer valuesW[1], W[2], ...W[m] and an integer n.0,

does a subset of the values add up to ex-actly n?

A well-known pseudo-polynomial al-gorithm (Reference 1) defines a table:T[ij], 1im and 1jn, to beT[ij]true if and only if a subset ofW[1],...W[i] sums to exactly j. The algo-rithm uses O(mn) time to fill in a tablethat uses O(mn) space. Table 1 withn13 shows the true entries and leavesthe false ones blank. This Design Ideaproposes an improved algorithm thatuses O(mn) time to fill in an array thatuses only O(n) space:

SubsetSum(W, m, n)1. Define a bit array A[j], 1 j n.2. Initialize the array to zeros.3. A[0]:1.

4. for i:1 to m do.5. for j:n to 0 do.6. if A[j]1 then A[j1W[i]]:1.7. return A[n].You can easily prove that the returned

value is 1 if and only if a subset of theweights adds up to exactly n. The proof isanalogous to the one of the originalO(mn)-space algorithm. The followingroutine implements the above algorithmin C++. It just shifts a bit map m times byW[j] bits and applies a bitwise OR oper-ation with the bit map from the previousstep.

int SubsetSum(int W[], int m, int n)bit_vector x1;for(i1; i <m; i++) x |x<<W[i];

Software snippet provides improved subset-sum algorithmIvan Basov, Brandeis University, Waltham, MA


ideasdesign

return (x>>n) &1;The bit_vector class overloads bitwise

operators and behaves as an (n+1) bitsinteger (with bits ranging from 0 to n).Now, consider a low-density subset-sumproblem, the case in which the above al-gorithms produce a bunch of zeros andonly a few ones in the bit array. You use adynamically growing linked list andwaste no space for “empty” elements:

SubsetSumLD(W, m, n)1. Define, a linked list with only one el-

ement with value 0 and with theHead being equal to the Tail.

2. for i:1 to m do.3. for Element :Head to Tail do.4. if Element.value+W[i] n.5. Insert(Element.value+W[i]).6. if Head.valuen.

7. return 1.8. else.9. return 0.The function Insert(value) inserts the

value into the list in descending sortedorder. The function does nothing if an el-ement with the same value already exists.The disadvantage of the subset-sum al-gorithm is that it solves only a decision—a yes-or-no problem—and doesn’t allowrestoring the partition itself. To overcomethis disadvantage, you can use an array ofintegers instead of an array of bits and

store the number of ones in the corre-sponding element. This solution requiresO(n log(m)) space, and the array repre-sents the sum of the rows of the tableT[ij] of the original O(mn)-space algo-rithm.

Reference1. Garey, Michael R and Johnson,

David S, A Guide to the Theory of NPCompleteness, Freeman, San Francisco,CA, 1979.

TABLE 1—SUBSET-SUM ARRAYi/j 0 1 2 3 4 5 6 7 8 9 10 11 12 13W[1]=1 T TW[2]=9 T T T TW[3]=5 T T T T T TW[4]=3 T T T T T T T T T T TW[5]=8 T T T T T T T T T T T T

Acommon technique for removingnonlinear temperature-related ef-fects from a dc voltage is to incor-

porate a temperature sensor that a mi-croprocessor samples via an A/D con-verter. The processor determines—bymathematical calculation or a tempera-ture-indexed look-up table—theamount of adjustment is necessaryat a given temperature and delivers theresulting value via a D/A converter.Though effective, that approach incursdesign effort, cost, and multiple ICs. Analternative technique uses a single IC inan unorthodox fashion (Figure 1). Thechip, intended as a low-cost interface toa Wheatstone bridge, normally providesprecision analog-signal processing alongwith digitally programmable compensa-tion of gain, offset, and temperature ef-fects. Much of its capability remains un-used in this application, but its size andpre-engineered internal circuitry canreadily add nonlinear temperature com-pensation to a design.

IC1

contains a bandgap temperaturesensor whose output is digitized by an 8-bit A/D converter, producing a digitalrepresentation of die temperature with1.45/bit resolution. An internal 768-byte

EEPROM, read/write accessible via theone-wire asynchronous DIO pin, pro-vides the user with two independent tem-perature-indexed look-up tables. (Thisdesign uses only one.) For the table inuse, an 8-bit temperature register index-es which of 176 16-bit stored values is applied to an internal 16-bit D/A con-verter. Because the temperature-indexing

boundaries of 69 to 184C are out-side the IC’s operating range of 40 to125C, the IC can compensate for brieftemperature excursions outside its nor-mal operating range.

The Figure 1 circuit removes temper-ature-variable nonlinear offsets from theanalog voltage, V

1IN. First, you program

IC1

for its minimum gain, 39V/V, so the

IC1MAX1452

11

10

2 V1OUT

TO ONE-WIRE I/O

OUT

UNLOCK

DIO

VSS

BDR

ISRC

UNUSED SECONDTEMPERATURE-COMPENSATED V

1

5

4 INM

VDDF VDD

5V

9 7

R110k

R2383k

V1IN

6

R35k

INP

3

F igure 1

IC removes nonlinear temperature effectsKevin Schemansky, Maxim Integrated Products, Howell, MI

IC1 introduces nonlinear temperature compensation to the analog voltage, V1.


ideasdesign

R1/R

2attenuation provides an overall

gain of unity. (The internal PGA providesa gain range of 39 to 264V/V.) Next, pro-gram the internal coarse-offset DAC with0000 binary and the offset-TC DAC with0000hex, to ensure that they have no ef-

fect on the V1

input voltage. To generatea compensated output (Pin 2), the out-put stage adds in the temperature-in-dexed value of a third DAC (the offsetDAC), whose 16-bit resolution achievesadjustments as fine as 74 V. After cal-

culating coefficients for the offset DAC,you program them into the IC via theDIO pin. The equation for output voltage is V

1OUT39(V

1IN/39)

VDD

(offset-DAC value/65,536)(offset-DAC sign).

Asimple, permanent-magnet dc mo-tor is an essential element in a vari-ety of products, such as toys, servo

mechanisms, valve actuators, robots, andautomotive electronics. In many of theseapplications, the motor must rotate in agiven direction until the mechanismreaches the end of travel, at which pointthe motor must automatically stop. Al-though you can use microswitches tostop the motor at the end of travel, theirsize, weight, and cost can be prohibitive,particularly in low-cost, portable items.The circuit in Figure 1 implements a low-cost, micropower, latching motor con-troller that uses current sensing ratherthan switches to stop the motor. The de-sign is optimized for a supply voltage of

3 to 9V, making it well-suited to battery-powered applications. To understandhow the circuit works, assume that cross-coupled flip-flops IC

1Aand IC

1Bare both

in a reset state, such that the D input ofeach one is high. Because both Q outputsare low, the H-bridge transistors, Q

1to

Q4, are all off, and the motor is idle.A momentary closure of the Forward

switch latches the Q output of IC1A

highand turns on MOSFET Q

2. This action,

in turn, provides bias for Q3, causing the

motor to run in the forward direction.The circuit is now latched, and, becauseIC

1B’s D input is now low, any closure of

the Reverse pushbutton has no effect onthe H-bridge, and the motor continuesrunning in the clockwise direction. IC

2

contains a comparator and a bandgapreference-voltage (nominally 1.182V)output at the Reference terminal (Pin 6).The motor’s armature current generatesa sense voltage, V

SENSE, across current-

sense resistor RSENSE

. The comparatorcompares V

SENSEat the IN input to a

reference voltage, which R5

and R6

set, atthe IN pin. Under normal runningconditions, V

SENSEis lower than the volt-

age at the IN input, and the compara-tor’s output at Pin 8 is low. However,when the mechanism hits an end stop atthe limit of travel, the motor’s armaturecurrent increases rapidly, causing a cor-responding rise in V

SENSE. The compara-

tor detects this increase, and the com-parator’s output goes high, thus resetting

_

+IN+

IN–

HYSTREF

GNDV–

V+

1.18V NOMINAL

OUT 8

12

3

4

56

R7100k

R4100k

IC2MAX931 OR

LTC1440

R1100k R8

100k

R3150R2

150

TO VDD(PIN 14) IC1

TO VSS(PIN 7) IC1

CF100 nF

C1100 nF

C2100 nFRF

100k

R5

D5

VSENSE

RSENSE

R6

D2

D1

MOTOR

D4

D3

Q3Q1

Q4Q2

+

7 RESET

SETQ D

QRESET

SETD Q

Q

8

9

11

13

12

10

1

2

6

4

5

3

REVERSEFORWARD

ON/OFF

BATTERYSUPPLY

VB

OV

+

IC1A4013B IC1B

F igure 1

Motor controller uses fleapowerAnthony Smith, Scitech, Biddenham, Bedfordshire, UK

This latching motor controller uses current sensing, rather than switches, to stop the motor.


ideasdesign

flip-flop IC1A

. Transistors Q2

and Q3

nowturn off, and the motor stops running.

Because IC1B

’s D input is now high,closing the Reverse switch latches IC

1B’s

Q output high. This action turns on Q4

and Q1

in the opposite arm of the H-bridge, such that the motor now runs inthe counterclockwise, reverse direction.IC

1A’s D input is now low, thereby dis-

abling the Forward pushbutton, and themotor continues to run in the reverse di-rection until the mechanism hits the op-posite end stop. Once again, the com-parator detects the increase in armaturecurrent, and the comparator resets IC

1B

and turns off the motor. The motor’s cut-off threshold is a function of R

SENSE, R

5,

and R6, and the bandgap voltage at the

REF pin. RSENSE

should be in the region ofa few ohms to ensure that V

SENSEis also

small when the motor is running undernormal loading conditions. KeepingV

SENSElow makes practically all of the

supply voltage available to the motor andensures that the gate-source voltage of Q

2

and Q4

is as large as possible. You shouldchoose values greater than 300 k for R

5

and R6

to minimize the loading on theREF pin. In noisy environments, it maybe necessary to decouple the IN pin.

Filter components RF

and CF

serve adual purpose. They are necessary tosmooth the relatively “lumpy”voltage ap-pearing across R

SENSEand are also essen-

tial to prevent the motor’s in-rush cur-

rent at turn-on from tripping the com-parator. Values of 100 k and 100 nFshould be adequate, but some experi-mentation may be necessary to deter-mine the best time constant for your ap-plication. Reset components C

2, D

5, and

R7ensure that the comparator’s output is

high at power-up. You should select alltransistors in the H-bridge to produceminimal saturation voltage when the de-vices conduct the maximum motor cur-rent. Choose low-V

CE(SAT)devices for Q

1

and Q3, and make sure that MOSFETs Q

2

and Q4

can receive full enhancement atthe minimum operating voltage. De-pending on the type of MOSFETs youuse, you may need to add a resistor in se-ries with each gate to prevent spuriousoscillation.

You should select resistors R2and R

3to

provide adequate base drive for Q1

andQ

3at the lowest supply voltage. Depend-

ing on the application, it may be possi-ble to replace Q

1and Q

3with p-channel

MOSFETs, in which case R2and R

3can be

fairly large. Freewheeling diodes D1

to D4

are necessary to commutate the currentsgenerated by the motor’s back-EMF atturn-off.You may require capacitor C

1to

suppress any noise that the motor’sbrushes produce. The circuit’s quiescent,motor-idle current drain is extremelylow, making it ideally suited to battery-powered applications. Measurements ona breadboard circuit operating from a 9V

supply voltage reveal a quiescent currentof just 9.5 A. You can adapt the circuitto produce a nonlatching version inwhich the motor runs in the forward orthe reverse direction only while the asso-ciated switch is closed. However, this ap-proach is not simply a matter of gatingthe comparator’s output with eachswitch; that action merely causes the mo-tor to hiccup at the cutoff point. Instead,you must again latch the comparator’soutput and add some extra logic in theform of a quad NOR gate. Figure 2 showsthe arrangement, in which NOR gatesIC

3Band IC

3Dcontrol the H-bridge, and

the comparator controls the flip-flop’s re-set pins as in Figure 1.

The motor runs in the forward direc-tion only while you depress the Forwardbutton; releasing the pushbutton stopsthe motor.While the switch is closed, IC

3A

holds IC1B

’s D input low, thereby ensur-ing that the Reverse switch can have noeffect on the motor while the Forwardswitch is closed. Once you release the For-ward switch, you can use the Reverseswitch to reverse the motor’s rotation.Again, the motor runs only while you de-press the pushbutton. You can see fromthe symmetry of the circuit that closingthe Reverse switch locks out any opera-tion of the Forward switch. When themechanism hits an end stop in either di-rection, the comparator resets the rele-vant flip-flop and shuts off the motor.

FORWARD

ON/OFF

RESET

SETQ D

Q

REVERSE

RESET

SETD Q

Q

TO Q2GATE

IC1A4013B

4001B

R8100k

R1100k

TO Q4GATE

1

1

5

5

3

3

2

2

6

6

4

4 1112 10

13IC3D

IC3C

IC1B

IC3B

8

9

9

8

10

1113

12

FROM COMPARATOROUTPUT, PIN 8, IC2

TO VDD(PIN 14) IC1

TO VSS(PIN 7) IC3

TO VDD(PIN 14) IC3

TO VSS(PIN 7) IC1

BATTERYSUPPLY

VB

+

0V

0V 0V

IC3A

F igure 2

This addition to the circuit in Figure 1 yields a nonlatching controller, in which the motor runs only when the associated switch is closed.

www.edn.com October 2, 2003 | edn 85


Pulse-width modu-lation is a simpleway to modulate,

or change, a square wave.In its basic form, theduty cycle of the squarewave changes accordingto some input. The dutycycle is the ratio of highand low times in thesquare wave. A wave-form with a 50% dutycycle would behigh for 50% ofthe time and low for 50%of the time, and a wave-form with a 10% dutycycle would be high for10% and low for 90%.Many applications existfor PWM, including motor control, ser-vo control, light dimming, switchingpower supplies, and even some audioamplifiers. In applications such as MEMS(micro-electromechanical-system) mir-ror-actuator control, a feedback systemneeds to regulate the PWM. A circuitmonitors and controls the PWM outputand varies the duty cycle according to therequirements of the application. The out-put frequency tunes the actuator, and theduty cycle sets the actuator’s speed. Thefeedback loop controls the threshold lev-el. This Design Idea describes a high-fre-quency, high-resolution PWM with feed-back control. First, it might be useful todiscuss some PWM theory.

ALTERNATIVE ARCHITECTURES

Traditional PWMs use two op amps togenerate a sawtooth waveform, a poten-tiometer to generate a dc reference, anda comparator to generate the PWM out-put. The advantage of this type of designis that the circuit is practical and inex-pensive. Unfortunately, you cannot easi-

ly program the frequency without chang-ing component values, and fine-frequen-cy tuning is difficult. Another problemwith this method is that accurate controlof the duty cycle is difficult.You could usea digital potentiometer in place of themechanical one, but this replacement re-sults in a more costly design. A secondmethod for generating PWM waveformsuses an ADC824 MicroConverter. Inaddition to providing two PWM outputs,it also integrates ADCs, DACs, an 8052-compatible microcontroller, and flashmemory. You can configure the PWMwith resolution as high as 16 bits. How-ever, the programmed frequency affectsthe resolution of the PWM. The fre-quency and resolution of the PWM are asfollows: F

PWM16.777 MHz/N, where N

is the resolution in bits.An internal PLL derives the 16.77-

MHz reference clock from a 32-kHz crys-tal. This reference clock samples the out-put of the PWM. As stated, N, thenumber of bits, is the resolution of thePWM. For 16-bit resolution the maxi-

mum frequency is 266 Hz. The resolutionat 200 kHz drops to approximately 6 bits.Thus, the ADC832 is the ideal low-costapproach for low-frequency, high-reso-lution applications but not for a high-frequency, high-resolution application.

DDS IMPLEMENTATION

Applications requiring high-resolutionfrequency tuning and pulse-width-mod-ulation tuning in real time can use a DDS(direct digital synthesizer) to provide ahigh-accuracy sawtooth waveform withfine-frequency resolution across a largebandwidth. You can then use this signalas the input to a comparator in either

AD9833DDS

MCLK

SCLKSDATAFSYNC

VDD

VDD

RL

LOWPASSFILTER

R1

R2

AD8611

3V

ACTUATOR

OPTICALFIBERSDAC

ADC

ADC824

8052

F igure 1

DDS circuit generates precise PWM waveformsColm Slattery, Analog Devices, Limerick, Ireland

A DDS circuit combines with a compara-tor and a microcontroller with an inter-nal DAC and ADC to generate high-reso-lution PWM outputs.

DDS circuit generatesprecise PWM waveforms ............................85

High-CMRR instrumentation amp works with low supply voltages ............................88

Use a DAC to vary LVDT excitation ..........92


86 edn | October 2, 2003 www.edn.com

ideasdesign

open- or closed-loop applications. Fig-ure 1 shows an easy method of generat-ing programmable square waves withprogrammable duty cycles. The AD9833DDS drives a programmable triangularwave into one input of the AD8611 com-parator and controls the frequency of theoutput waveform. The feedback loopfrom the actuator controls the thresholdlevel of the comparator. TheAD8611 is a single 4-nsec compara-tor with a latch function and comple-mentary output. The input signal fromthe DDS connects directly to the invert-ing input of the comparator. The outputfeeds back to the noninverting inputthrough R

1and R

2. The ratio of R

1to

R1R

2establishes the width of the hys-

teresis window with VDAC

setting the cen-ter of the window or the average switch-ing voltage. The output switches lowwhen the input voltage is greater than V

HI

and does not switch high again until theinput voltage is lower than V

LO,

as the following expressionsshow: V

HI(V+1.5 VV

DAC)

(R1/(R

1R

2))V

DAC, and V

LO

VDAC

(R2/(R

1R

2)), where V is

the positive supply voltage tothe comparator and V

DACis the

level that the DAC sets. TheAD8611 can accept a 100-MHzsignal with 400-mV p-p levelsand can also accept input sig-nals in the tens of millivolts.The AD9833 can provide sinu-soidal- and triangular-waveoutputs using the DDS archi-tecture. It includes a numeri-cal-controlled oscillator em-ploying a 28-bit phase accumu-lator, a sine ROM, and a 10-bitD/A converter on a single chip(Figure 2).

You typically think of sinewaves in terms of their magni-tude expression: a(t)=sin(vt).However, these waveforms arenonlinear and are difficult togenerate. On the other hand,the angular information is lin-ear in nature. That is, the phaseangle rotates through a fixedangle for each unit in time.Knowing that the phase ofa sine wave is linear and

given a reference interval (clock period),you can determine the phase rotation forthat period:

Phasesdt;Phase/dt;f(Phasef

MCLK)/2,

where dt is the reciprocal of fMCLK

, themaster clock. You can generate outputfrequencies using this formula, knowing

the phase and master-clock frequency.The phase accumulator provides the 28-bit linear phase. The sine ROM stores theamplitude coefficients of the output sinewave in digital format. The DAC convertsthe sine wave to its analog domain. If youbypass the sine ROM, the part deliverstriangular waveforms instead of sinu-soidal waveforms. You program the de-

vice by writing to the fre-quency registers. Theanalog output from thepart is then f

OUT(f

MCLK/

228)(frequency-registerword).

The DDS outputs have28-bit resolution, so effec-tive frequency steps on the order of 0.1 Hz are pos-sible to a maximum of ap-proximately 10 MHz. Twophase registers provide 12-bit phase resolution. Theseregisters phase-shift the sig-nal by P

SHIFT(2/4096)

(phase-register word). A25-MHz crystal oscillatorprovides the master refer-ence clock for the DDS. Theoutput stage of the DDS is avoltage-output DAC with atypical swing of 0.7V p-pinto an internal 200 resis-tor. Adding load resistor R

L

reduces the peak-to-peakoutput voltage, thus allow-ing you to tune the peak-to-peak output of the DDS tothe input range of the com-parator.A filter stage gener-ally appears on the output

Applying different thresholds to the comparatorin the circuit of Figure 1 has these effects.

OUTPUT SQUAREWAVE RESPONDSTO THRESHOLDCHANGES.

SAWTOOTH CONTROLSPERIOD OF OUTPUTSQUARE WAVE; OUTPUTS AT 1 MHz.

PHASE ACCUMULATOR AMPLITUDE/SINE-CONVERSION ALGORITHM

D/ACONVERTER

TUNING WORD SPECIFIESOUTPUT FREQUENCY AS A FRACTION OF REFERENCE-

CLOCK FREQUENCY.

DIGITAL DOMAIN

F igure 2

A DDS circuit includes a numerical-controlled oscillator employing a 28-bit phase accumulator, asine ROM, and a 10-bit D/A converter on a single chip.

F igure 3

(a)

(b)

(c)


ideasdesign

of the DDS. The purpose of this stage isto filter feedthrough from the referenceclock, images, and higher frequencies andto bandlimit the signals under consider-ation.

Figure 3 shows typical output plotsfrom the AD8611 comparator in Figure1. The input signal from the DDS is a tri-angle wave set to 1 MHz. Each plot shows

the PWM output for various thresholdvoltages. In the closed-loop circuit of Fig-ure 1, you can tune the output of thePWM to 12-bit accuracy.You have accessto many possible ways of providingpulse-width modulation; the approachdepends on the application. For low-res-olution applications, traditional methodsusing op amps and potentiometers are

acceptable and inexpensive. For low-fre-quency, high-resolution applications, theADC832 provides a one-chip approachwith added features for free. For high-res-olution, high-frequency applications re-quiring fine-frequency tuning, you cancombine a DDS and a comparator to gen-erate precise, high-frequency PWMwaveforms.

Modern battery-cell voltages of 3to 3.6V require circuits that offerefficient low-voltage operation.

This Design Idea proposes an ac-coupledinstrumentation-amplifier design thatfeatures high CMRR (common-mode-rejection ratio), wide dc input-voltagetolerance, and a first-order highpasscharacteristic. Most of these features stemfrom a high-gain first-stage design. Thecircuit uses popular-value and -tolerancecomponents. Figure 1a shows the sim-

plified amplifier circuit. The generalprinciple is that the capacitor, C, and theR

3resistors buffer and ac-couple the in-

put signal. The second stage comprisestwo differential amplifiers, A

D. Each of

them amplifies half the differential inputsignal. A summing operation yields thefollowing expression for V

OUT:

In Figure 1a, VA, V

B, V

C, and V

Dare the

two differential amplifiers’ inputs, and AD

is the gain. The time constant 2R3C de-

fines the highpass cutoff frequency. Fig-ure 1b shows the detailed circuit. The in-put stage comprises op amps A

1, A

2, A

3,

and A4.A

1 and A

2are the main gain stages.

Because their inverting and noninvertinginputs are at the same potential, the in-put voltages supply the R

3resistors. The

buffers A3

and A4, along with the R

2re-

sistors, produce an amplification factor,1R

3/R

2, for the cur-

rent in R3, because R

2

and R3

connect to equalpotentials. This circuitstructure is the heart ofthe design. The voltageon capacitor C has no accomponent, and A

1and

A2

each amplifies one-half of the differential-input ac signal. C filtersthe input dc compo-nent, which appears atthe A

3and A

4outputs.

The second stage is aunity-gain, four-inputadder-subtracter stage.It implements the aboveequation, where A

Dis

1R1/(R

2||R

1). Assum-

ing R3R

2, A

D1

R1/R

2.

Another possible im-plementation for thesecond stage could usetwo differential-chan-nel ADCs, producing a

A2

_

+

A4

_

+

A3_

+

A1_

+

A5

_

+

AD_

+

+

AD_

+

R4

R4

R4

R4

VOUTVOUT

VIN ()

VIN ()

VIN ()

VIN ()

R4

R4

R1

R2

R3

R3

R3

R3

C

(a) (b)

C

R2

1

1

R1

VB

VC

VC

VB

VA

VD

VD

VA

F igure 1

High-CMRR instrumentation amp works with low supply voltagesDobromir Dobrev, Jet Electronics, Sofia, Bulgaria

Capacitor C ac-decouples the simplified amplifier circuit (a); the detailed circuit (b) uses gain stages and an adder-sub-tracter stage.

(a)

(b)

V A V V V V

As

OUT D A B C D

D2

= + =( )

RR C

sR C3

31 2+

.


ideasdesign

digitized VOUT

, ready for microcomput-er processing. If a 5V supply is avail-able, it is possible to obtain V

OUTby us-

ing two difference amplifiers on onechip, such as the INA2134. You can cal-culate the minimum CMRR as:

where AD(1-4)

is the differential gain ofamplifiers A

1through A

4, A

CM(1-4)is the

common-mode gain of these amplifiers,A

D5is the differential gain of amplifier

A5, and A

CM5is the common-mode gain

of A5. is the tolerance of the R

4resis-

tors in the circuit. A very important pa-rameter is the op amps’ input offset volt-age, especially for A

3and A

4. The A

1and

A2

offsets do not contribute to error, be-cause they add to the input signal’s dccomponent, which capacitor C cancels.The maximum output-voltage error at-tributable to op-amp offset voltage is:

where VIOMAX

are the maximum offsetvoltages of the corresponding op amps.In selecting op amps, you should note thefollowing: A

3, A

4, and A

5should be low-

offset and high-CMRR types, and A1

andA

2should have high open-loop gain,

CMRR, and gain-bandwidth products.Figure 2 shows a practical amplifier cir-cuit. The power supply is one 3V lithiumbattery. You can use several op-amptypes, such as MCP607s or OPA2336s.Because of the input common-modevoltage range, you set the signal groundto one-third of the supply voltage. The D

1

diodes prevent the circuit from latchingup. The R

7-C

4networks provide RF-noise

filtering at the inputs.You derive the net-work’s values from the following consid-eration: With R

7C

4(R

1||R

2||R

3)C

2

R2C

2, the high-frequency zero in the am-

plifier’s transfer function cancels:

The circuit has the following advan-tages:

The first stage ensures the overallgain, thus providing high CMRRwithout the use of high-precisionresistors in the second stage.

By connecting the low-frequency-determining RC network to the in-verting inputs of the op-amp pairthat amplifies the input signal, thecircuit needs no additional inputbuffers.

The circuit delivers a standard, first-order highpass characteristic, usingpassive components with popularvalues and tolerances.

The differential-input range is ashigh as 2V, using a 3V supply.

The circuit consumes low supplycurrent and power: approximately120 A, 0.4 mW.

C26.8 nF

C26.8 nF

C4680 pF

C4680 pF

C31 µF

C110 µF

VOUT

R1200k

R21k

R4100k

R710k

R710k

VIN (+)

VIN ()

REFERENCE

D1BAV99

D1BAV99

R4100k

3V

R4100k

R4100k

R1200k

R21k

R31.6M

R31.6M

R4100k

R4100k

R52M

R81M

_

+

IC2BMCP607

_

+IC3A

MCP607

_

+

IC1BMCP607

IC3BMCP607

_

+IC1A

MCP607

_

+IC2A

MCP607

_

+

F igure 2

This high-CMRR instrumentation amplifier operates from extremely low supply voltages.

CMRRA A

A

A

D D

CM

1 4

1 4

5

5

= × =ACM(

( )

)

DD D

R R

A

4 1 2

1 5

44 4∆ ∆/( / )

.,

+=

MAX IOA MAX IOA MAXV V V 13 4= +( ) ++

+

≈

R

R

V A VIOA MAX D IOA MAX

1

2

5 343 2 ,

=A sV

VDOUT

IN

( )(( ) ( )(

(

+=

+ +×

+

×+

V

sC R

sC R sC R

R

R R

sC RIN

2

1 1 2

11

3 3

4 4 3 3

1

2 3

2

11 2

2 11

R R

sC R+

.


ideasdesign

LVDTs (linear variable differentialtransformers) are electromechanicalmeasuring devices that convert the

position of a magnetic core into electri-cal signals. You generate these signals viaexcitation on the primary side. The re-sults on the secondary side—typically,two secondary windings—depend on theposition of the core (Figure 1). The ex-citation typically ranges in ampli-tude from 1 to 10V and in fre-quency from 1 to 10 kHz, depending onthe type of LVDT you employ. Tradi-tionally, for one circuit to provide suchvariability in frequency and amplitude,you can use either an LC tank with ad-justable components or a sine-wave gen-erator under microcontroller control. Itcan be difficult to achieve precision overtime and temperature with the LC-tankcircuit because of variations in passivecomponents. You also must manuallyperform calibration. You can more easi-ly obtain precision over time and tem-perature through the use of a microcon-troller-controlled sine-wave-generatorchip, and calibration can be automatic,but the method incurs a greater expense

than the LC-tank circuit. The circuit inFigure 2 presents an alternative.

Rather than using a sinusoidal signal toexcite the LVDT, a triangular wave comesfrom the integration of a square-waveoutput provided by a microcontrollertimer. With the use of a current-outputDAC, such as the AD7564 from AnalogDevices (www.analog.com), you can cre-ate a circuit that provides an alternative ata lower cost than that of a sine-wave-gen-erator chip and with greater ease of mod-

ification than with an LC-tank circuit. Be-ginning with the microcontroller, the fre-quency of the excitation wave depends onthe configuration of the microcontroller’stimer. You can configure a free-runningtimer, for example, to toggle the outputbased on the comparison match of a pre-set count. You base the count on the de-sired frequency output and the timer’s in-ternal clock rate. You then adjust theoutput of the microcontroller’s timer toremove offset. You need to eliminate asmuch offset in the signal as possible be-cause such offset adversely affects thetransformation process.You can use an opamp to remove the offset because the off-set is constant—in this case, half the volt-age that powers the microcontroller. Ingeneral, you should choose an op ampwith low offset and low bias, not only forthe difference stage, but also later.

Once you center it about common, thesignal becomes a triangular wave. The in-tegrator you use is basically a single-pole,lowpass filter with a configurable (via theDAC) corner frequency. The corner fre-quency you choose guarantees that inte-gration of the excitation signal occurs. To

accommodate variability infrequency and amplitude,the DAC provides an easyinterface. With two chan-nels of the AD7564, the cir-cuit can emulate variableresistors for the feed-for-ward and the feedback ofthe integrating op amp.(The other two channelscould serve for the demod-ulation gain of each LVDTsecondary.) You can usethese “resistors” to form thecorner frequency for the“lossy” integrator and to es-tablish the gain through thecircuit, ensuring that thesignal is integrated and thatthe amplitude of the excita-tion signal is appropriatefor the LVDT.

You need to make sever-al calculations in advanceto determine the configura-

1

2

3

4

5

6

PRIMARY SECONDARY

F igure 1

Use a DAC to vary LVDT excitationAnthony Di Tommaso and Ljubisa Milojevic, ABB Inc, Natrona Heights, PA

An LVDT is an electromechanical measuringdevice that converts the position of a magneticcore into electrical signals.

SDIN

CLKIN

CLR

LDAC

FSIN

SDOUT

RFBA

RFBB

RFBCRFBDIOUT2CIOUT2D

VREFC

A0A1

VDD/REFA

IOUT1A

IOUT2A

VREFB

IOUT1B

IOUT2B

NC

VREFD

IOUT1C

IOUT1D

IC1AD7564

DGND

AGND

3VVCC

15

16

12

13

14

11

SDIN

CLK

RESET

GAIN_DAC_LD

FSIN

SDOUT1

20

24

5927

6

1817R4

10k

R211k

R111k

7

R3 10k

Vcc

TIMER OUT

3

VCC

VDD

VDD

–VDD

VDD

19

21

22

23

25

28

26

10

4

8

IC2AAD712

2

3

4

8Q2MMBT2907

Q1MMBT2222A

LVDT PRIMARY

INPUT

C1470 pF

1 27

1

6

5

3

IC2BAD712

F igure 2

This circuit uses a triangular wave from a DACto excite an LVDT.


ideasdesign

tion of the DAC and the establishmentof the resistances. According to the datasheet, the resistance of the R-2R ladder inthe Analog Devices AD7564 DAC is typ-ically 9.5 k. You can calculate the feed-back resistance using the following for-mula: R

FB1/(2f

DC), where f

Dis the

desired corner frequency of the integra-tor and C is the value of the capacitor youuse.You can then assemble the data wordfor that effective resistance accord-ingly: N

FB(40969500)/R

FB, where

NFB

is the digital word loaded into theDAC. The feed-forward resistance of theintegrator circuit is then R

IR

FB/(gain

factor), where the gain factor depends onthe desired output amplitude. The dataword for that effective resistance becomesN

I(R

FB/R

I)N

FBor N

I(gain factor)

NFB

. In most cases, you may need to useadditional drive current from the outputof the “lossy” integrator to drive the pri-mary coil of the LVDT. This approachmay entail the addition of transistors and

other components.You have some flexibility in the type of

excitation signal the circuit uses becauseit is common practice to calibrate anLVDT. Figure 3 illustrates the output ofthe excitation circuit and the results onthe secondary side of the LVDT. Al-though what appears on the secondaryside differs from the excitation signal, itis sufficient because of the inherent fil-tering properties of the LVDT. The out-

put of each secondary side generallytransforms into a constant root-mean-square or mean-absolute-deviation val-ue. In the situation of two secondarycoils, a comparison between those valuesoccurs. As long as you excite both coilsin the same manner—which is guaran-teed because only one primary coil ex-ists—and the output signal is of sufficientresolution, then a triangular wave can ex-cite such an LVDT.

F igure 3Although what appears on the secondary side differs from the excitation signal,it is sufficient because of the inherent filtering properties of the LVDT.

TIMER OUTPUT

PRIMARY INPUT

SECONDARY 1OUTPUT

SECONDARY 2OUTPUT


ideasdesign


Ideal triangle waves involve infinited2V/dt2, so high-fidelity triangle wavesentail very high bandwidths. Micro-

power circuits have fairly low bandwidth,so generating good triangle waves withsuch circuitry becomes problematic. Thecircuits of Figure 1 show two methods ofgenerating triangle waves. The solitary-comparator circuit uses a relaxation-os-cillator approach with the triangle ap-proximation assuming an RC (expo-nential) nature (Figure 1a). When youneed better linearity, adding an integra-tor improves the triangle approxi-mation (Figure 1b). Both circuits

include a hysteretic-feedback path, as wellas an RC or integrator feedback pathcomprising R

3 and C

1. The hysteretic-

feedback path keeps changing the direc-tion of the RC integrator and setting thenew target voltage, and the RC integratorsets the rate of change toward the newtarget. These circuits are robust and findwide usage.

The problem arises when you simul-taneously require ultralow power con-sumption and relatively high-frequencyoperation. This scenario makes phenom-enal demands on the micropower opamp. Consider that, every time the com-parator reverses direction, it slams an in-stantaneous current into or out of the opamp’s output through the two feedbackpaths. This situation would be acceptable,except that the amount of current itslams is greater than the op amp’s totalsupply current. The result is a disastrous-looking waveform with enormous glitch-es stemming from the fact that the opamp cannot provide the instantaneousoutput-switch current demands.You can

gain some improvement by increasingthe resistor values and reducing the ca-pacitor values. However, the improve-ments are only incremental, and the cir-cuit becomes noisier and moresusceptible to interference.

COMPARATOR

COMPARATOR

R2

R3

R1

C1

C1

TRIANGLE SQUARE(a)

TRIANGLEOP AMP

_

+

_

+

R3

R1R2

R1

SQUARE(b)

100k

1.5V

–1.5V

10 nF

1M

_

+

F igure 1

High-fidelity triangle-wave generator consumes only 6 AGlen Brisebois, Linear Technology Corp, Milpitas, CA

These popular methods of generating triangle waves have drawbacks, especially when your designrequires low-power operation.

OP AMP

R31M

R4536k

TC7S14F

R21M

R1100k

COMPARATOR

1.5V

10 nF

1.5V

1.5V

1.5V

LTC1542

F igure 2

A simple CMOS inverter provides high-band-width current assist, improving the waveformdrastically with minimal impact on supply cur-rent.

High-fidelity triangle-wave generator consumes only 6 A..................81

High-current driver serves home-power-line modems ............82

Circuit forms fast, portable light pulser ......................................................84

3V supply delivers 12V p-p to piezo speaker..............................86

Code provides adjustable differential drive for robots ..........................88

Microcontroller produces analog output ................................................88

Single transistor provides short-circuit protection ..................................90



ideasdesign

But take heart; a simple and inexpen-sive solution is at hand. Why not let aCMOS inverter provide the instanta-neous current and let the op amp simplyprovide the precision linearizing current?

Figure 2 shows the method. The circuitis identical to that of Figure 1b, exceptthat the op amp need not provide the in-stantaneous switch current. Instead ofthe drastic change in output-current po-

larity at the triangle peaks, the op amp’soutput current slowly crosses zero atmidsupply. In the improved waveform,the total supply current at 280-Hz oper-ating frequency is 6.2 A.

Home-based power-linenetworking signals aresimilar to xDSL (digital-

subscriber-line) signals in thatthey both typically employ aform of OFDM (orthogonalfrequency-division multiplex-ing). Both applications re-quire high output current,wide bandwidth, and goodlinearity. This Design Idea de-scribes a simple line-drivercircuit, designed with anxDSL driver, to drive high-speed data over a home pow-er line. Figure 1 shows theAD8391 current-feedbackamplifier connected in a neg-ative-feedback circuit to drivewideband, discrete multitone-based signals throughhome power lines.The advantage of currentfeedback is that it allows youthe flexibility of increasing thegain beyond unity without be-ing limited by the gain-band-width product. The AD8391has 60-MHz bandwidth,600V/sec slew rate and 250-mA output-drive-current ca-pability, making it ideal fordriving home power lines.

The circuit in Figure 1 op-erates with a 5V supply, has a voltage gainof 2(R

F/R

G), and drives a 33 load.

The 33 load emulates the worst-caseimpedance of a home power-line net-work, which can vary greatly from hometo home. The driver is transformer-cou-pled to the power line. The amplitude ofthe output signal is 2.8V p-p into the dif-ferential power line (hot and neutral)

with a peak-to-average ratio of 4V/V. Thefeedback resistor, R

F, and the gain resis-

tor, RG, maximize circuit bandwidth and

stability. For this circuit, an acceptablebandwidth is approximately 30 MHz.The following equation shows the rela-tionship between closed-loop bandwidth(f

CL), R

G, and R

Ffor current-feedback am-

plifiers.

CP, the internal capacitance, sets the

corner frequency of the open-loop tran-simpedance function, and R

INis the in-

put impedance of the inverting terminalof each amplifier. (Figure 1 does not

AD8391FROM DAC/MODEM

49.9 0.1 F

RG205

RF412

PD

10 F 0.1 F

0.1 F

5V

33POWERLINE

49.9

0.1 FRG

205RF

412 0.1 F

IN28 7 6

VMID VS

VS

OUT2

OUT1

5

43

PWDN

2

_

+

_

+

INI

1

F igure 1

High-current driver serves home-power-line modemsRyan Metivier, Analog Devices, Wilmington, MA

An xDSL driver uses current-feedback technology to make an efficient home-power-line driver.

f

C RR

R

R

R

CL

P FIN

F

IN

G

1

2 1

=+ +

− −π.


ideasdesign

show CP

and RIN

.) It is important to notethat R

Fdominates the expression, thus

controlling the closed-loop bandwidth.The 49.9 resistors on the inputs of thecircuit terminate the signal source. Youshould adjust these values based on eachapplication. The four 0.1-F capacitors

provide ac coupling on the input andoutput lines. The test signal is a compos-ite waveform constructed from the sumof 75 sinusoids of pseudorandom phase.Each tone in the test waveform may haveone of four phases to emulate QPSK(quadrature phase-shift keying). The si-

nusoids are orthogonally spaced from 4to 21 MHz, leaving the amateur-radiobands empty. Figure 2 shows that theworst-case empty-tone distortion is 35dBc. This figure is adequate for mostpractical power-line applications. Figure3 shows the output in the time domain.

F igure 2

AMPLITUDE(10 dB/DIV)

START 3 MHZ 1.9 MHZ

FREQUENCY

STOP 22 MHZ F igure 3

This plot represents the time-domain characteristic of thepower-line driver.

100 nSEC

The output spectrum of the power-line driver in Figure 1 shows that theworst-case empty-tone distortion is 35 dBc.

The absence of afast one-shot mul-tivibrator in the

entire TTL family, aswell as thelow-voltageswing and unwieldysupply requirementsof ECL, drove us to ex-ploit the fast transitiontimes and low propa-gation delays of F-se-ries gates. The applica-tion called for theimplementation of acompact, portable, fastlight pulser for fieldtesting fast photomultipliers in gamma-ray astronomy work. The use of only twoICs helped to minimize the size andpower consumption (Figure 1). Thenormally high pulses at the output gate,G4, in IC

2have rise and fall times of ap-

proximately 2.5 nsec and a duration of

less than 10 nsec, corresponding to threegate delays. These pulses are ideally suit-ed to pull low the cathode of a fast, blueHLMP-CB-15-type LED with the anodeclamped at 5V. The gate forces almostthe entire 5V supply voltage across theLED. This high swing ensures optimum

brightness of the LED, which is solderedto the edge of a small pc-board strip.Rechargeable batteries are clamped ontothe other side of the pc board. Using aCMOS version of the timer, IC

1, the cir-

cuit has a current drain of less than 4mA.

8 7

5

62

3

4

1

0.1 F

0.1 F

IC17555

G1

56k 22k

5V

G2 G3

G4

74F00

IC2HLMP-CB-15

5V

F igure 1

Circuit forms fast, portable light pulserSK Kaul and IK Kaul, Bhabha Atomic Research Centre, Trombay, Mumbai, India

This circuit provides fast light pulses in a blue LED.

1V


ideasdesign

Low-profile piezoelectric speak-ers can provide quality sound forportable electronic devices, but they

require voltage swings greater than 8V p-p across the speaker element. Yet, mostportable devices include only a low-volt-age power source, and conventional am-plifiers operating from batteries cannotprovide enough voltage swing to drive apiezoelectric speaker. One approach tothis problem is to use IC

1in Figure 1,

which you can configure to drive a piezo-electric speaker with as much as12V p-p and operate from a single3V supply. IC

1, a MAX4410, combines a

stereo-headphone driver with an invert-ing charge pump that derives a negative

3V supply from the positive 3V supply.Thus, providing the drive amplifiers withan internal 3V supply allows each out-put of IC

1to swing 6V p-p. Configuring

IC1

as a BTL (bridge-tied load) driveragain doubles the maximum swing at theload to 12V p-p. In the BTL configura-tion, IC

1’s right channel serves as the

master amplifier. It sets the gain of thedevice, drives one side of the speaker, andprovides a signal to the left channel. Ifyou configure IC

1as a unity-gain follow-

er, the left channel inverts the output ofthe right channel and drives the other leg

of the speaker. To ensure low distortionand good matching,you should set theleft-channel gain us-ing precision resis-tors.

We tested the cir-cuit with a Panasonic(www.panasonic .com) WM-R57A pi-ezoelectric speaker,yielding the THDN (total-harmonic-distortion-plus noise)curves (figures 2 and3). Note thatTHDN in-creases as frequencyincreases in bothgraphs. Because the

speaker appears to the amplifier as a ca-pacitor, the speaker’s impedance decreas-es as frequency increases, resulting in alarger current draw from the amplifier.IC

1remains stable with the speaker, but a

speaker with different characteristicsmight cause instability (Figure 4),. In thatcase, you can isolate the speaker’s capaci-tance from the amplifier by adding a sim-ple inductor/resistor network in serieswith the speaker (within the dotted lineson Figure 1). The network maintains sta-bility by maintaining a minimum high-frequency load of approximately 10 atthe IC’s output.

10k

13

INR

10k

AUDIOINPUT

1 FOUTR

11

INL10

OUTL8

IC1MAX4410

_

+

_

+

10k

10k

10

100 H

OPTIONALRL NETWORK

F igure 1

3V supply delivers 12V p-p to piezo speakerRoyce Higashi and Tony Doy, Maxim Integrated Products, Sunnyvale, CA

This bridge-tied-loadconfiguration multipliesthe amplifiers’ voltage-swing capability.

Testing the circuit yields thisTHDN versus frequency for the Figure 1 circuit.

Testing the circuit yields thisTHDN versus output voltage

for the Figure 1 circuit.

THD+N (%)

f=10 kHz

f=1 kHz

100

10

1

0.1

0.01

0.001

0.0001f=100 kHz

VOUT=2VCC

0 2 4 6 8 10 12 14

F igure 2

Step response at the OUTR output of IC1 in Figure 1, which drivesa WM-R57A piezoelectric speaker, shows that IC1 remains stablewith the speaker.

F igure 4

OUTPUT VOLTAGE(VPP)

THD+N (%)

1

0.1

0.01

0.001

FREQUENCY (Hz)

10 100 1000 10000 100000

F igure 3

2V/DIVOUTR

20 SEC/DIV


ideasdesign

Intelligently modify-ing the motor-drivecommands to a robot

can give you control finesseduring competitions. Mov-ing a joystick hard right, forexample, might have differ-ent effects, depending onthe robot’s speed and di-rection. Software runningon an inexpensive micro-controller (in this case, anNEC (www.nec.com) PD78F9814) manages this con-trol by calculatingseparate drive andadjust vectors and thencombining the vectors andcalculating the appropriatepower ratio for two treadmotors (Figure 1). Thisdemonstration system usesa simple treaded toy vehicleto show how the ratio-driveconcept works and requiresno sensors in the vehicle. The microcon-troller controls the tread motors with sim-ple forward/reverse signals based on thecalculated motor speeds and directions.

Listing 1, which you can downloadfrom the Web version of this Design Ideaat www.edn.com, shows the main routinefor this application. It begins by initial-izing all the signals and then calibratingthem with the joystick at the idle position(MID) and each extreme (LO and HI).The code uses several sets of variables.Drive variables (DriveRaw, DriveHI,DriveMID, DriveLO, and Drive) specify

the combined drive speed for the motors.Ratio variables (RatioRaw, RatioHI, Ra-tioMID, RatioLO, and Ratio) specify theratio of right-to-left motor balance. Ad-just variables (AdjustRaw, AdjustHI, Ad-justLO, and Adjust) specify the adjust-ment value to the ratio value. Theadjustment reduces the ratio value to better control left/right balance at par-ticular speeds. Range-conversion vari-ables (RangedUpper, RangedLower, andRanged) rerange the ADC inputs to thedesired 0 to 100% values for the motorspeed and direction. After the code cal-

culates the Left and Right motor vectors,another routine uses these vectors todrive the motors. If Right is greater than1, for example, the drive routine enablesa RightForward PWM signal and disablesthe reverse signal. For experimentationpurposes, you can use a 1A quad half-Hbridge to route the speed and directionsignals to the motors. In actual competi-tions, you need a heavier duty motor con-troller because the motor-stall currentscan exceed 1A.

@ DRIVE

@ RATIO

* CALIBRATE

~ LEFT SPEED

# LEFT DIRECTION (2)

~ RIGHT SPEED

ADJUSTMENT-VECTOR

CALCULATION

DRIVE VECTOR

ADJUST VECTOR

MOTOR-RATIO

CALCULATION

*ENGAGE

@ADJUST

# RIGHT DIRECTION (2)

*=INTERRUPT.NOTES:@=ADC INPUT.#=DIGITAL INPUT OR OUTPUT.~=PWM OUTPUT.&=COMMUNICATION DATA.$=DATA-TABLE VALUES.(0 TO 9)=NUMBER OF CONNECTIONS.

DRIVE-VECTOR

CALCULATION

COMBINEDVECTOR

CALCULATION

COMBINED VECTOR

Code provides adjustable differential drive for robotsAlton Harkcom, EGO North America, Newnan, GA

An NEC microcontroller calculates the appropriate power ratios for two tread motors in a robot.

F igure 1

Abrushless dc motor needs severalvoltage levels to control its speed: 0Vto stop the motor, 5V to run it at max-

imum speed, and some voltages betweenthese extremes to run it slower. When youuse such a motor in a system under mi-crocontroller supervision, the microcon-troller should generate all these voltages.

But a microcontroller is a digital device,and it usually has no analog output. Sev-eral methods are available to overcomethis deficiency. For example, you could usea DAC, a digitally programmable poten-tiometer, or some analog switches con-nected to resistor dividers. However, whenyou need only a few intermediate voltage

levels, it would be more attractive to finda method that uses microcontroller soft-ware. This Design Idea exploits the factthat you can program a microcontroller’sI/O pins as either input or output. Whenyou program a pin as output, you set itsvoltage level to high (5V) or low (0V).When you program a pin as input, it has

Microcontroller produces analog outputAbel Raynus, Armatron International, Melrose, MA


ideasdesign

no effect on output voltage. Figure 1shows a circuit example.

The circuit needs no external compo-nents, except for a few resistors. You canset the output-voltage levels during themain program execution or by an exter-nal interrupt. For testing purposes, usingan external interrupt is preferable (seeListing 1 at www.edn.com). A pushbut-ton-mode switch triggers the external in-terrupt, the service routine of which con-sequently sets all the predeterminedvoltages. This design uses 0, 1.25, 2.5,3.33, and 5V levels. Resistors R

1to R

4de-

termine the intermediate levels. The cir-cuit uses the inexpensive, 8-bit MC-68HRC908JK1 flash microcontrollerfrom Motorola (www.motorola.com),but this method applies to almost anykind of microcontroller. You can down-load the microcontroller software fromthe Web version of this Design Idea atwww.ednmag.com.

MODE

C110 pF

VO

VOUT (V)

0

1.25

2.5

3.33

5

R520k

R4100k

R1300k

R2100k

R349.9k

5V

MC68HRC908JK1

OSCPB3

OUT 1

PB4OUT 2

PB5OUT 3

PB6OUT 4

IRQ

F igure 1

A microcontroller can generate analog outputs for motor-control purposes.

In certain dc/dc-converter applica-tions, on-chip, cycle-

by-cycle current limitmay be insufficient pro-tection to prevent a fail-ure during a short cir-cuit. A nonsynchronousboost converter pro-vides a direct path fromthe input to the shortcircuit through the in-ductor and the catchdiode. Regardless ofcurrent-limit protec-tion in the IC, when ashort circuit exists inthe load, extremelyhigh currents that flowthrough the load pathcan damage thecatch diode, the in-ductor, and the IC. In aSEPIC (single-ended,primary-inductance-converter) circuit,the coupling capacitor breaks this path.Thus, when a short circuit exists in the

load, no direct path exists for current toflow from input to output. However, ifthe required minimum on-time is less

than the application-specific duty cycle,the inductor and, thus, the switch cur-rent can rapidly increase, causing IC fail-

VIN

LT1961EMS8E

SHDN

SYNC

GND GND

VC

FB

VSW

2.2 FX5R

25V CERAMIC

CIN

VIN

L1CDRH5D28-150

1 FX5R

25V CERAMIC

CCOUP

CATCHDIODE

UPS140

VOUT

COUT

10 FX5R

16V CERAMIC

10k

90.9k

RSENSE0.80

FMMT3904

6.8 nF

100pF

6.8k

L2CDRH5D28-150

4 TO 18V 12V

CFF47 pF

F igure 1

Single transistor provides short-circuit protectionKeith Szolusha, Linear Technology Corp, Milpitas, CA

This 4 to 18V-input, 12V-output SEPIC has short-circuit protection.


ideasdesign

ure, input-supply overload, or both.Even in certain buck-regulator applica-tions, duty-cycle limitations sometimeskeep the switch on too long to maintaincontrol during an output short-circuitcondition, especially at very high input

voltage with extremely high-frequencyICs. A single-transistor approach pro-tects the SEPIC circuit from short-cir-cuit fault conditions by pulling downthe V

Cpin (the output of the error am-

plifier) when the inductor current startsto run away during an overload or shortcircuit in the load (Figure 1).

Pulling the VC

pin low forces the IC tostop switching, skipping minimum on-time switch cycles, and allowing the cur-rent in each inductor to ramp down.During a short circuit, the peak cur-rent in L

1, which decreases because

of the limited number of switch cycles,and the peak current in L

2sum up to

equal the peak current in the switch,which is less than the 1.5A limit of theLT1961EMS8E. Figure 2 shows theshort-circuit input and output currentsat different input voltages. Figure 3shows the maximum load current versusinput voltage. The average current in L

2

is equal to the load current and is a max-imum of 600 mA under all load condi-tions. If the sense resistor sees 800 mA, itknows that an overload condition has oc-curred and tells the transistor to protectthe circuit.

900

800

700

600

500

400

300

200

100

064 8 10 12 14 16

VIN (V)

SHORT-CIRCUITCURRENT

(mA) INPUTOUTPUT

F igure 2

The short-circuit input and output currentfor the circuit of Figure 1 differ at differentvoltages.

1200

1000

800

600

400

200

00 2 4 6 8 10 12 14 16 18 20

INPUT VOLTAGE (V)

CURRENT(mA)

MAXIMUM LOAD CURRENTIL1 PEAK CURRENTIL2 PEAK CURRENT

F igure 3

These curves show the maximum load currentunder normal load conditions.



Modern microprocessor- or FP-GA-based circuits require separateand independent power-supply

voltages for the core and the I/O circuits.Some devices require stringent control ofthe turn-on characteristics and sequenc-ing of these multiple power supplies toavoid internal parasitic current flows andconsequent latch-ups. Although regula-tors exist with specific soft-start andshutdown inputs, it may be more cost-ef-fective to use regulators that do not in-herently provide these features and toadd these features with external discretedevices. This Design Idea shows how touse an inexpensive Linear Technology(www.linear.com) LTC3701 dual switch-ing regulator to provide a sequenced, and

standby-controlled, power supply for anEquator Technologies (www.equator.com) broadband-signal processor. Youcan also adjust the circuit for FPGA orgeneric microprocessor applications. Thefeatures of the circuit in Figure 1 increasethe regulator’s stability beyond what youcan achieve with the standard LinearTechnology application-note circuit.

The LTC3701 switching regulator, IC1,

provides two independently adjustableoutput voltages with very high voltage ac-curacy at a cost compatible with con-sumer-type applications. Because of costconstraints, it does not provide the soft-start or shutdown features present in oth-er switching regulators. This design addsthree discrete transistors to the conven-

tional regulator circuitry to provide botharbitrary power-on-sequencing controland a simultaneous-shutdown feature.Q

3, Q

4, and Q

5are inexpensive discrete

R475k

08050.1%

R1 = 37.4k = 1.20V VCORE.R1 = 47.5k = 1.30V VCORE.R1 = 66k = 1.50V VCORE.R1 = 93.1k = 1.80V VCORE.R1 = 160k = 2.50V VCORE.

VCORE

VCORE

KELVIN SENSING

161514

12347

11568

SENSE 1ITH/RUNVFB1SGNDPLLLPFPGOODVFB2ITH/RUN2SENSE 2

SENSE 1+VIN

PGATE1

SENSE 2+EXTCLK/MODE

PGNDPGATE2

1312109

KELVIN SENSING

LTC3701EGN

5VVIN

VIN5V

5

62

2

1

13

4

5VVIN

D2ONMBRS130T3

D1ONMBRS320T3

+

+

C10220 µF6.3V

C3220 µF6.3V

C1580 pF0603

C422 µF 10V

1210

C922 µF10V

1210

C8580 pF0603

IC1C2

47 pF0603

C6060347 pF

C7580 pF0603

C5580 pF0603

L2

2.2 µH2.3A IRMS

COILCRAFTDO1608C-222

COILCRAFTDO3316P-332

L13.3 µH

5.4A IRMS

562

4

3

1

1

2

1%R8

232k0805

1%R1

37.4k0805

R70.015

R933k

R510k

PACK4

R610k

R310k

Q2FAIRCHILDFDC638P

Q42N3904-

SMD1

3

SLEEP

SLEEP

8 7 6 5

1 2 3 4

2

3

2

Q5BSN20

Q3BSN20

Q1FAIRCHILDFDC638P

0.1%R1075k

0805

R20.015

3.3V1

F igure 1

Scheme adds sequencing and shutdown control to regulatorSaid Jackson, Equator Technologies Inc, Campbell, CA

Adding a few transistors to a switching regulator adds power-sequencing and shutdown control to a power supply.

Scheme adds sequencing and shutdown control to regulator ....................89

MathCAD functions perform log interpolation ............................................90

Scheme improves on ow-cost keyboard ..........................................94

ADC interface conditions high-level signals............................................96

Two op amps provide averaged absolute value..............................98



ideasdesign

devices that control the voltageon the regulator’s I

TH/Run pins.

The ITH

/Run pins of IC1

pro-vide an external compensationto the internal feedback loops;they can also serve to shutdown the device when you pullthem to ground. A micro-processor’s TTL/CMOS-com-patible input signal (Sleep)controls the power state of thecircuit. You can put the circuitinto shutdown mode by eitherletting the Sleep pin float highor pulling it higher than ap-proximately 1.5V. Q

3 then con-

nects the ITH

/Run1 pin toground, which causes theV

COREcore-voltage supply to

shut off. The VCORE

voltage thendrops toward ground, and Q

4

stops conducting when VCORE

falls belowapproximately 0.8V. The gate of Q

5pulls

to the 5V unregulated input voltage, andQ

5shorts the I

TH/Run2 pin to ground,

which turns off the 3.3V regulator. Thecircuit is now in standby mode, and bothpower supplies are off.

Pulling the Sleep pin lower than ap-proximately 0.8V turns on the powersupply and sequences the voltages in thefollowing manner: Q

3stops conducting,

and the voltage on the ITH

/Run1 pin canrise, thanks to internal current sources inIC

1. The V

COREvoltage regulator then

starts to operate, and VCORE

rises to its setvoltage, 1.2V by default. Q

4starts con-

ducting as soon as VCORE

rises above ap-

proximately 0.8V. This action turns off Q5

and allows the ITH

/Run2 pin voltage tostart rising. The 3.3V power supply thusturns on. The combined effect of drivingQ

4and Q

5from the V

COREvoltage is that

the 3.3V I/O voltage always turns on onlyafter the V

COREvoltage attains an estab-

lished level. The end result is to sequencethe power supplies over a period of 4msec (Figure 2).

The circuit is symmetric, and changingthe base drive of Q

4and interchanging

the drain signals of Q3and Q

5reverses the

sequencing order of the power suppliesfor chips that require the I/O voltage torise before the core voltage. You can ad-just the value of R

1to generate any core

voltage above approxi-mately 1V. You may needto adjust the value of R

9if

your design requires corevoltages below approxi-mately 1V.You can replaceQ

3and Q

5by potentially

cheaper industry-stan-dard 2N2007 devices atthe expense of slightlyhigher capacitive loadingon the I

TH/Run pins of

IC1. C

2and C

6are com-

pensation capacitors thatthe Linear Technology lit-erature does not mentionbut that are highly effec-tive in preventing subhar-monic oscillation arisingfrom dynamic currentloading on the outputs.

(See the Linear Technology Web site forinformation on subharmonic oscilla-tion.)

The gate-drain-source capacitance ofQ

3and Q

5also add to the stability of the

loop filter. Note that sequencing the turn-on ramps of the power supplies also hasthe benefit of reducing the inrush currentinto the power supply by staggering thiscurrent and preventing simultaneouscurrent loading of the primary bypass ca-pacitors by both power supplies. The se-lected component values allow for morethan 2A of current on the 3.3V line andmore than 3.5A of current on the V

CORE

line.

F igure 2

The 3.3V supply turns on several milliseconds after VCORE attains an estab-lished level.

1 500 mV/DIV 1.49V3 1V/DIV 75 mV 1 (1)=800 mV

2 (3)=5.880V=6.680V

349.96 SEC3.88004 mSEC4.23000 mSEC236.406 Hz1/X=

Y X

ACQUISITION IS STOPPED100k SAMPLES/SEC

MathCAD provides a number ofinterpolation and curve-fittingfunctions, so that, given a set of X-

Y data points, you can estimate the Y val-ue for any given X coordinate. Unfortu-nately, these functions work poorly withdata that is to be displayed in a nonlinear(logarithmic) manner. Examples of thesefunctions are:

Log-Lin: phase/magnitude-versus-frequency (Bode plots);

Log-Log: impedance-versus-fre-quency (reactance plots); and

Lin-Log: impedance-versus-tem-F igure 1

MathCAD functions perform log interpolationJames Bach, Delphi Delco Electronics Systems, Kokomo, IN

At X coordinates between data points, MathCAD’s linterp function creates abulging effect.


perature (thermistor data).Using the built-in “linterp” function,

MathCAD estimates and plots the data(Figure 1). As you can see, at X coordi-nates between the original data points,the “linterp” function creates a “bulging”effect. The following trio of simple in-terpolation functions allows the correctinterpolation of nonlinear data on its ap-propriate scale. These routines functionby prewarping the incoming-data matri-ces before feeding them into the ex-isting “linterp”function; for logarith-mic Y-axis functions, you raise 10 tothe result of the “linterp” function to re-store the values to the proper decade:

Using the newly created LogLogInterpfunction, the straight-line data is displayed(Figure 2).


ideasdesign

F igure 2 Using the LogLogInterp function, the bulges in Figure 1 disappear.

You can easily im-prove on a previousDesign Idea to pro-

duce a slightly simpler re-sistor arrangement withbetter timing balance be-tween switches, using asingle resistor value(Reference 1, Figure 1).The use of a single resistorvalue, R

S, in a series chain

for the switch resistorsgives the timing parameters a simplerformat and should reduce bill-of-mate-

rials cost. The timing balance betweenswitches should now also be more even.

The improved balance easesextending the keyboard foradding key inputs. The addi-tional benefit of this arrange-ment is to make the circuit eas-ier to adapt for faster or slowermicroprocessors, because youcan easily adapt the circuit bychanging the single switch re-sistor or capacitor values to al-ter the charge-discharge char-acteristics (Figure 2). It canalso make building the circuitinto a keypad housing easier,especially if you use mem-brane keys. The entire circuit is

an SMD assembly with just two compo-nent types: switch and resistor. In theoriginal idea, in cases of multiple keysbeing pressed, the timing is some oddmultiple of parallel resistors and couldaccidentally represent a key that was notselected. With the arrangement of Fig-ure 1, the lowest order key dominates;hence, the keypad has hard-wired pri-ority setting and always results in a se-lected key timing, and no intermediatetiming period should occur.

Reference1. Thevenin, Jean-Jacques,“Novel idea

implements low-cost keyboard,” EDN,April 3, 2003, pg 69.

SX

1k1k 1k1k1kR11k

R2 R3 R4 R5 RX

S1 S2 S3 S4 S5

C147 nF

RC

100MICROCONTROLLER

F igure 1

Scheme improves on low-cost keyboardMartin O’Hara, Telematica Systems Ltd, Cranfield, Bedfordshire, UK

This simple keypad arrangement uses a single resistor value to select the switches.

A 400-kHz square wave from themicroprocessor shows no key, key 1,

and key 5 pressed.

F igure 2


ideasdesign

Designers who buildequipment for theindustrial market

share a widespread prob-lem. At one extreme,they must build equip-ment that supports10V bipolar voltages,often riding on a highcommon-mode level, arequirement enforced by30 years of legacy indus-trial equipment. At theother extreme, the ana-log signal needs condi-tioning to match the full-scale range of a low-voltage, single-supplyADC. Designers need toscale and level-shift sig-nal levels throughouttheir system toaccommodatethe high voltage levelsthat sensor manufactur-ers dictate and the lowvoltage levels that theADC dictates. Operating from asingle 5V supply, the circuit inthis Design Idea provides an in-terface of large bipolar inputs toa single-supply, low-voltage, dif-ferential-input ADC. The circuitin Figure 1 comprises two dif-ference amplifiers, connected inantiphase. The differential out-put,V

1V

2, is an attenuated ver-

sion of the input signal:V

1V

2(V

AV

B)/5.

The difference ampli-fiers reject the common-mode voltage on inputs V

Aand

VB. The reference voltage, V

R,

which the AD780 develops andthe ADC and the amplifiershare, sets the output common-mode voltage. A single capaci-tor, C, placed arcros the C

FILT

pins, lowpass-filters the differ-ence signal, V

1V

2. The 3-dB pole fre-

quency is: fP1/(40,000C). A

2am-

plifies the difference signal by 1.5. Thus,the total gain of this circuit is 3/10. Figure

2 shows a 10V input signal(top), the signals at the out-put of each AD628 (mid-dle), and the differentialoutput (bottom). The ben-efits of this configuration gobeyond simply interfacingwith the ADC. The circuitimproves specifications suchas common-mode-rejectionratio, offset voltage, drift,and noise by a factor of 2because the errors of eachAD628 are not correlated.

The output demonstrates85-dB SNR (Figure 3). Thetwo AD628s interface withan AD7450 12-bit, differen-tial-input ADC. The AD-7450 easily rejects residualcommon-mode signals atthe output of the difference

amplifiers. Figure 4 shows the common-mode error at the output of the AD628.

_

_

_

+

A2+

A1

V1

V2

+

A2

_

+

A1

R4100k

R310k

RGCFILT

CFILT

C

RG

R310k

R2100k

R110k

+IN

IN

+IN

-IN

R110k

10k

10k

VR

VR

VS

AD628

AD628

AD628

AD7540

AD780

5V

3.32k13.3k

3.32k

5V

5V

VS

5V

2.5V

REFERENCE

PRECISIONREFERENCE

OUT

OUT

AD628

VB

VA

VREF VS

VSVREF

R2100k

R4100k

5

7

5

7

2 643

2 643

8

8

1

1

F igure 1

ADC interface conditions high-level signalsMoshe Gerstenhaber and Stephen Lee, Analog Devices, Wilmington, MA

This circuit attenuates and level-shifts a 10V differential signal while operating from a single 5V supply.

F igure 2

The waveforms show a 10V input signal (top), the signals at the outputof each AD628 (middle), and the differential output (bottom).

50k SAMPLES/SEC HI RES

10.0V2V

CH3

2V 1.00 mSEC

2.00V M1 mSEC CH1 2.4V


ideasdesign

The common mode input (top) measures 20V p-p. The common-modeerror of the differential output (middle) is 200 V p-p. The error of thecommon-mode output (bottom) is 80 V p-p.

The topmost waveform is a 10V, com-mon-mode input signal. The middlewaveform, measuring 150 V, is the

common-mode error measured, differ-entially, from the output of the twoAD628s. The bottom waveform, meas-

uring 80 V, is the resultant common-mode error.

F igure 3

The circuit in Figure 1 has an 85-dBV SNR.

INPUT20V p-p

COMMON-MODEERROR OF DIFFERENTIALOUTPUT

COMMON-MODEERROR OF COMMON-MODEOUTPUTF igure 4

The circuit in Figure 1 is usefulwhen you need amplitude demodu-lation or an averaged absolute-val-

ue conversion. The circuit comprises twostages, the first of which, IC

1A, is a dif-

ferential-output absolute-value convert-er. The second stage, IC

1B, is a tradition-

al differential amplifier. Thecombination of the two stages performssingle-ended absolute-value conversionbut only if R

3R

2. The C

1capacitors

integrate the current flow and yield av-eraged voltages V

Aand V

B. In addition,

the capacitors ensure low ac-impedancepoints at nodes V

Aand V

Bwhen the out-

put diodes are reverse-biased.The additional C

2capacitors in

parallel with R4

resistors impart a sec-ond-order-lowpass-filter characteristicto the circuit and remove the remainingac signal. From a practical point of view,you can choose R

3to be five to 10 times

higher than R2. The gain of the circuit is

(R2||R

3/R

1)(R

4/R

3). In most applications,

you would choose the filter time con-

stants 1R

2||R

3C

1 and

2R

4C

2to be

equal. The circuit in Figure 1 is simple,symmetrical, and cost-effective. It alsomakes it easy to calculate and adjust thegain using one resistor, R

1. Other advan-

tages are that the circuit has equal delayfor positive- and negative-going signalsand that it doesn’t need matcheddiodes.

IC1ATL082

IC1BTL082

C1470 nF

VIN

VOUT

R222k

R120k

R3220k

VA

VB

R4220k

R222k

R3220k

R4220k

C247 nF

C1470 nF

C247 nF

D1BAV99

+

__

+

Two op amps provide averaged absolute valueDobromir Dobrev, Jet Electronics, Sofia, Bulgaria

This single-ended, averaged absolute-value converter is useful for amplitude demodulation.

F igure 1

www.edn.com November 13, 2003 | edn 101


Instrumentation amplifiers servein a variety of applications that needto extract a weak differential signal

from large common-mode noise or in-terference. However, designers oftenoverlook the potential problem of RFrectification inside the instrumentationamplifier. The amplifier’s common-mode rejection normally greatly reducescommon-mode signals at an instrumen-tation amplifier’s input. Unfortunately,RF rectification still occurs, because eventhe best instrumentation amplifiers havevirtually no common-mode rejection atfrequencies higher than 20 kHz. The am-plifier’s input stage may rectify a strongRF signal and then appear as a dc-offset error. Once the input stagerectifies the signal, no amount of low-pass-filtering at the instrumentationamplifier’s output can remove the error.Finally, if the RF interference is intermit-tent, measurement errors may go unde-tected. The best practical solution to thisproblem is to provide RF attenuationahead of the instrumentation amplifierby using a differential lowpass filter. The

filter needs to remove as much RF ener-gy as possible from the input lines, pre-serve the ac signal’s “balance” betweeneach line and ground (common), andmaintain a high enough input impedanceover the measurement bandwidth toavoid loading the signal source. Figure 1provides a basic building block for a widerange of differential RFI filters.

The component values are typical ofthose for the latest generation of instru-mentation amplifiers, such as the AD-8221, which has a typical 3-dB band-width of 1 MHz and a typical voltagenoise level of 7 nV/Hz. In addition toRFI suppression, the filter also providesadditional input-overload protection; re-sistors R

1Aand R

1Bhelp isolate the in-

strumentation amplifier’s input circuitryfrom the external signal source. Figure 2shows a simplified version of the RFI cir-cuit. It reveals that the filter forms abridge circuit whose output appearsacross the instrumentation amplifier’s in-put pins. Because of this connection, any

mismatch between the time constants ofC

1A/R

1Aand C

1B/R

1Bunbalance the bridge

and reduce high-frequency common-mode rejection. Therefore, resistors R

1A

and R1B

and capacitors C1A

and C1B

should always be equal. C2

connectsacross the “bridge output”so that C

2is ef-

fectively in parallel with the series com-bination of C

1Aand C

1B. Thus connect-

ed, C2

effectively reduces any ac com-mon-mode-rejection errors from mis-matching. For example, making C

210

times larger than C1

provides a 20-timesreduction in common-mode-rejectionerrors arising from C

1A/C

1Bmismatch.

Note that the filter does not affect dccommon-mode rejection.

The RFI filter has differential and com-mon-mode bandwidths. The differentialbandwidth defines the frequency re-sponse of the filter with a differential in-put signal applied between the circuit’stwo inputs, IN and IN. The sum ofthe two equal-value input resistors, R

1A

and R1B

, and the differential capacitance,

_

+

AD8221 VOUT7

6 REFERENCE

RG

VS

VS

C1B

C1A

2

1

3

45

+IN

IN

R1A4.02k

R1B4.02k

1000 pF

1000 pF

C20.01 F

0.33 F

0.33 F

0.01 F

0.01 F

RFI FILTER

8G=1+49.4k

RG

F igure 1

Input filter prevents instrumentation-amp RF-rectification errorsCharles Kitchin, Lew Counts, and Moshe Gerstenhaber, Analog Devices, Wilmington, MA

This lowpass-filter circuit prevents RF-rectification errors in instrumentation amplifiers.

Input filter prevents instrumentation-ampRF-rectification errors ..................................101

White-LED driver backlights LCD and keypad ..........................................102

Microcontroller or DSP circuit controls on/off function..............................104

Simple power supply fits into small spaces ........................................108

Amplifier and current source emulate instrumentation amplifier ..........................110

Hardware histogram speeds ADC test..........................................................112


102 edn | November 13, 2003 www.edn.com

ideasdesign

which is C2

in parallel with the seriescombination of C

1Aand C

1B, establish this

RC time constant. The 3-dB differen-tial bandwidth of this filter is equal to BW

DIFF[1/(2R(2C

2C

1))]. The com-

mon-mode bandwidth defineswhat a common-mode RF sig-nal “sees”between the two inputs tied to-gether and ground. C

2 does not affect the

bandwidth of the common-mode RF sig-nal, because this capacitor connects be-tween the two inputs, helping to keepthem at the same RF-signal level. There-fore, the parallel impedance of the two RCnetworks (R

1A/C

1Aand R

1B/C

1B) to ground

sets common-mode bandwidth. The 3-dB common-mode bandwidth is equal toBW

CM1/(2R

1C

1).

Using the circuit of Figure 1, with a C2

value of 0.01 F, the 3-dB differential-signal bandwidth is approximately 1900Hz.When operating at a gain of 5, the cir-cuit has measured dc-offset shift over afrequency range of 10 Hz to 20 MHz ofless than 6 V referred to the input. Atunity gain, there is no measurable dc-off-set shift. Some instrumentation ampli-fiers are more prone to RF rectificationthan others and may need a more robustfilter. A micropower instrumentation

amplifier, such as the AD627, with itslow-input-stage operating current, is agood example. The simple expedient ofincreasing the value of the two input re-sistors, R

1A/R

1B, that of capacitor C

2, or

both can provide further RF attenuationat the expense of reduced signal band-width. Some steps for selecting RFI-fil-ter component values follow:

1. Decide on the value of the two se-ries resistors and ensure that the previouscircuitry can adequately drive this im-pedance. With typical values of 2 to 10k, these resistors should not contributemore noise than that of the instrumen-tation amplifier itself. Using a pair of 2-k resistors adds Johnson noise of 8nV/Hz. This figure increases to 11nV/Hz with 4-k resistors and 18

nV/Hz with 10-k resistors.2. Select an appropriate value for ca-

pacitor C2, which sets the filter’s differ-

ential (signal) bandwidth. Set this valueas low as possible without attenuating theinput signal. A differential bandwidth of10 times the highest signal frequency isusually adequate.

3. Select values for capacitors C1A

andC

1B, which set the common-mode band-

width. For decent ac common-mode re-jection, these capacitors should have val-ues 10% or lower of the value of C

2. The

common-mode bandwidth should alwaysbe less than 10% of the instrumentationamplifier’s bandwidth at unity gain.

You should build the RFI filter using apc board with a ground plane on bothsides. All component leads should be asshort as possible. Resistors R

1and R

2 can

be common 1% metal-film units. How-ever, all three capacitors need to be rea-sonably high-Q, low-loss components.Capacitors C

1Aand C

1Bneed to be 5%-

tolerance devices to avoid degrading thecircuit’s common-mode rejection. Goodchoices are the traditional 5% silver mi-cas, miniature micas, or the new Pana-sonic 2% PPS film capacitors (Digi-keypart number PS1H102G-ND).

+IN

–INC2

R1A C1A

VO

C1BR1B

INSTRUMENTATIONAMPLIFIER

F igure 2

Capacitor C2 shunts C1A/C1B and reduces ac com-mon-mode-rejection errors arising from com-ponent mismatch.

Designers widely use white LEDsto backlight color LCDs and key-pads in handheld devices, such as

cell phones, MP3 players, GPS naviga-tors, and PDAs. Their spectrumand brightness represent near-ideal light sources. One possible config-uration for a phone or a phone/PDAcombination is to have a group of threeLEDs to light the display and six LEDs forthe keypad. Figure 1 shows a method fordriving all the LEDs with a single driverIC from Catalyst Semiconductor (www.catsemi.com), the CAT32. Power comesfrom a single lithium-ion battery cell. AFET switch can independently turn offthe group of six LEDs. The shutdown in-put, SHDN, on the CAT32 turns off allthe LEDs. LED brightness is a directfunction of the current running through

VIN

RSET LED

SHDN

SW

GND

R11.5k

RS75

C14.7 F CAT32

+

6.8 H

SUMIDACLQ4D106R8

IIN

VIN3.4V

ZETEXZHCS400

RS75

RS75

DISPLAY KEYPAD

WHITELEDs

15 mA15 mA

OFF ON

N-FET

F igure 1

White-LED driver backlights LCD and keypadFabien Franc, Catalyst Semiconductor, Sunnyvale, CA

A single IC boosts the battery voltage to drive a total of nine LEDs.


ideasdesign

the LED, and typical values are 10to 20 mA for white LEDs.The CAT32 regulates aconstant current through theLED pin. Resistor R

1connected to

the RSET pin adjusts the LEDcurrent.

The driver is a step-up con-verter using an inductor to boostthe voltage, such as that from alithium-ion battery, and biasmultiple LEDs in series. The R

S

resistors in series with the LEDsbalance out the current betweenthe groups of LEDs. The LED for-ward voltage, typically around 3.5V, ex-periences some variation from one LEDto the other for a given bias current, andthe series resistors also compensate forthat situation. By using series resistorswith values of 75, a current of approx-imately 15 mA flows in all LEDs. The dis-play uses Nichia (www.nichia.com)NSCW335 side-view LEDs, and top-viewNichia NSCW100 LEDs backlight the

keypad. You define efficiency as the ratioof the power dissipated in the LEDs, in-cluding the power in the series resistorsbut not including the loss in the Schottkydiode, to the total input power. Figure 2shows the efficiency of the circuit for aload of 15-mA current in the LEDs andfor supply voltage ranging from 3 and4.2V, corresponding to the charge-dis-charge cycle of lithium-ion batteries. The

expression for efficiency is asfollows:

where VLED

is the voltage acrossthe LED, I

LEDis the LED current,

RS

is the series resistor, and IIN

isthe current from the input sup-ply. The efficiency is approxi-mately 84% for a 3.6V supply. Ifyou now consider only the pow-

er the LEDs dissipate, excluding all theother losses, the following formula givesthe net efficiency (approximately 75%with a 3.6V supply):

3 3.2 3.4

90

85

80

75

70

65

603.6

INPUT VOLTAGE (V)

EFFICIENCY (%)

3.8 4 4.2

F igure 2

This curve shows the efficiency of the circuit in Figure 1 for 15-mA LED current and 3 to 4.2V battery voltage.

In many applications, a single on/offbutton switches the power supply onor off. Usually, the system switches off

regardless of the processing function orworkload the microcontroller or DSP cir-cuit is currently handling. The small cir-cuit in Figure 1 is intended to make themicrocontroller or DSP circuit the mas-ter over this on/off function. The circuitallows the microcontroller or DSP circuitto take ownership over the on/off func-tion. Thus, the system can do whateverhas to be done, such as processing data,storing data, and so forth, before it issuesthe command to shut down the supply.Figure 2 shows the timing diagram. Theswitch connects directly to the dc supplyor battery, though the end application isdisconnected from the supply. Thus, allthe capacitors discharge. The most diffi-cult task is to get the two D flip-flops inFigure 1 into the desired “off” configu-ration.

The inverter, IC1B

, in Figure 1 resets theD flip-flop, IC

2B, via the diode, D

4. The

RC network comprising R10

, R11

, and C4,

connected to the input of the inverter,IC

1B, generates a delay time of approxi-

mately 4.7 msec. This interval ensuresthat this D flip-flop is released from re-set after a delay time of approximately 4.7msec.When the delay time has passed, re-set-input pin R of IC

2Bchanges from high

to low potential because R7

connects toground. At the same time, output Q ofIC

2Bswitches to low level, and Q switch-

es to high level. The D input node of IC2B

changes as well from high to low poten-tial because it connects to the output pin,Q. The RC network comprising R

1and

C3, in conjunction with the inverter, IC

1A,

generates a delay of approximately 47msec. This delayed output connects tothe set pin of the D flip-flop, IC

2A. The

set pin holds high for 47 msec before itgoes low. The RC network, comprisingR

1and C

3, along with the inverter, IC

1A,

generate a 47-msec delay. The delayedoutput connects to the set pin of the Dflip-flop, IC

2A. The set pin holds high for

47 msec before it goes low.After the set pin falls to a low level, the

D flip-flop, IC2A,

changes its output lev-els at Q to high and Q to low, and feed-back from Q connects to the D input. Thehigh level at Q (SHTDN), connected tothe enable pin of the dc/dc converter orlow-dropout regulator, keeps the systemoff. The D flip-flop, IC

2A, is now in an off

condition. From this point on, both Dflip-flops are in a known state. The DSPI/O pin is low during this initialization,because the DSP circuit receives no pow-er. R

15ensures a low level during the pow-

er-up sequence at the DSP I/O pin. TheSHTDN, after its initialization phase, as-sumes an active-high level. If you connectit to the enable pin of the system dc/dcconverter or low-dropout regulator, itkeeps the system in an off condition.IC

1B’s input changes its level from high to

low when you press the pushbutton, be-cause the switch shorts the pullup resis-tor at the pushbutton node to ground.IC

1B’s output changes its level according-

Microcontroller or DSP circuit controls on/off functionDirk Gehrke, Texas Instruments, Freising, Germany, and Frans Ravn, ChemoMetec A/S, Alleroed, Denmark


ideasdesign

ly from low to high for that period.The CLK input of D flip-flop IC

2A trig-

gers via R14

and D1, and output Q changes

its status from low to high. This state en-ables the low-dropout regulator or dc/dcconverter to start operation. The 3.3 or5V connected to R

2 supplies transistor Q

1

to change the logic level at the CLK inputof D flip-flop IC

2A. This action ensures

that the system disregards glitches whenyou press the on/off pushbutton. TheDSP I/O pin of the circuit connects toone of the DSP circuit’s or microcon-troller’s I/O pins. You should configurethe I/O pin of the DSP circuit or micro-controller as an input pin after power-upand reset release. As long as you press theon/off pushbutton, transistor Q

2 remains

on, driving the DSP circuit’s I/O pin low.You should program the DSP circuit ormicrocontroller such that the DSP circuitstops executing code before you releasethe button, and the DSP I/O pin changesits level from low to high. D flip-flop IC

2B

again resets via D4, but this reset

does not alter the output becausethe application is running.

When you again press the on/off push-

button, the DSP I/O pin assumes a lowlevel. The DSP circuit or microcontrollershould now detect this input change andgenerate an interrupt. This interruptshould initiate a shutdown procedure. D

flip-flop IC2B

changes, via D4, to reset

mode, so that the toggle signal valid atCLK has no impact on the output status.You now release the on/off pushbutton.D flip-flop IC

2Breleases from reset after

IC1C

IC1B

IC2BCD4013B

IC1A

IC2A

IC1F

IC1E

IC1D

R9100

VDD

VDD

VDD

VDD

R3470k

R11470k

R10100k

R12100k

R610k R5

10k

R1610k

R4100k

R15470k

R1470k

R81M

R210k

R14100k

R7100k

D4

D2

D1

D3

13

5 6

12

89

1011

Q

Q S

R

S

CD40106B

CD40106B

CD40106B

CD40106B

CD40106BCD4013B

D

>CLKR

Q

Q

1

43

5

6

2

4 3

9

11

8

10

1213

CLKD

C5100 nF

C410 nF

C610 nF

C3100 nF

Q3BC547

Q1BC547

Q4BC547 Q2

BC547

SHTDN

ON/OFFPUSHBUTTON

DSPI/O

R1310k

1 2

1N4148

1N4148

1N4148

1N4148

3.3 OR 5V3.3V

F igure 1

This circuit generates a delay between the DSP circuit’s or microcontroller’s “off” command and systemshutdown.

CONTROLLER ACKNOWLEDGMENT:

USER WANTS TO POWER DOWN APPLICATION.

CONTROLLER HAS TIMETO STOP ALL TASKS BEFORE POWERING DOWN THE SUPPLY.

CONTROLLER CONFIGURES THE I/O PIN AS THE OUTPUT PIN AND DRIVES THE

PIN LOW.

PRESSED BUTTON

I/O PIN CONFIGURES AS OUTPUT PIN.

I/O PIN CONFIGURES

AS INPUT PIN.

PUSH_BUTTON

5V3.3V

I/O PIN3.3V

t

t

t

t

6 TO 15VVDD

F igure 2

This timing diagram shows that the DSP circuit or microcontroller takes ownership over the sys-tem’s on/off function to allow time for performing crucial tasks.


ideasdesign

approximately 4.7 msec, and Q2

and Q4

change levels and maintain a low signalat the CLK pin before the reset delay timepasses. The microcontroller or DSP cir-cuit sees a high signal at the I/O pin afterthis time-out and can start the shutdownprocedure.

The DSP circuit or microcontroller

now has the time to store any criticaldata. You must program the microcon-troller’s or DSP circuit’s I/O pin as anoutput pin set low. Q

4loses its drive volt-

age, and the CLK pin of D flip-flop IC2B

changes its status from low to high. Dflip-flop IC

2Achanges its output status via

the output, Q, and D3. Q and Q change

the status of the SHTDN pin to low lev-el, and the system shuts down. At thesame time, D flip-flop IC

2Bresets via Q

3

and the comparator IC1C

. This resetbrings D flip-flop IC

2Bto the initial state

described above before you first pressedthe on/off pushbutton.

The demand for negative-voltagepower supplies is increasing with the popularity of applications for

portable devices. It can be expensive andrelatively complicated to generate a neg-ative supply from a positive input source,especially when the design requires bothpositive and negative outputs. Fig-ure 1 shows a simple and cost-ef-fective solution that combines a voltageinverter and a voltage doubler in a sin-gle charge-pump circuit. It produces aregulated 5V output and an unregu-lated 10V output from a 5 to 6V input.The circuit requires only five small, ce-

ramic, surface-mount capacitors and twodiodes in addition to the charge-pumpIC in an SOT-23 package.

From a 6V input, the inductorlessdc/dc inverter can deliver 100 mA at aregulated 5V (5%), and the voltagedoubler can provide 50 mA at 10.5V with7% variation. The inverter’s output-voltage regulation follows the rela-tionship (V

IN5)(I

OUTR

OUT);

you can determine the values of ROUT

andI

OUTfor V

IN5V from the graph in Fig-

ure 2. (The ROUT

and IOUT

values for oth-er V

INvalues are available in the LTC-

1983’s data sheet.) If the variables don’tmeet this inequality condition, the partruns in open-loop mode and acts as alow-output-impedance inverter in whichthe output voltage is V

OUT1

[VIN

(IOUT

ROUT

)].You can define theoutput voltage of the voltage doubler as

VOUT2

2VIN

2VD, where V

Dis the for-

ward voltage drop across the diodes. Fig-ure 3 shows the efficiency of the circuit,which exceeds 81% and peaks at approx-imately 85%. Figure 4 shows the invert-er’s output-voltage regulation versus in-verter output current. The IC includesshort-circuit and thermal protection.

VIN

SHDN

C C

GND

VOUTLTC1983ES6-5

VOUT15VIOUT100 mA MAXIMUM

VOUT22VINIOUT250 mA

ON

OFF

11

6

3

CIN10 F

VIN2

5

4

NOTES: CIN, COUT1

, COUT2

: TAIYO YUDEN JMK316BJ106ML.C

FLY: TAIYO YUDEN LMK212BJ225MG.

CBOOST

: TAIYO YUDEN EMK316BJ225ML.

D1 D2

CBOOST2.2 F

CFLY2.2 F

1

1

COUT210 F

COUT110 F

4.5 TO 6V

F igure 1

Simple power supply fits into small spacesRaymond Zheng, Linear Technology, Milpitas, CA

This circuit combines a regulated inverter and a voltage doubler.

IOUT (mA)

ROUT()

12

10

86

4

20

0 50 100

VIN5V

F igure 2

This graphic shows ROUT versus IOUT for the cir-cuit in Figure 1.

IOUT1 OR IOUT2(mA)

EFFICIENCY(%)

5030.210.5

86

84

82

80

78

F igure 3

This curve shows efficiency versus either out-put current.

IOUT1 (mA)

VOUT1(V)

0 10080604020

4.5

4.64.7

4.84.9

5

5.1

IOUT250 mAVIN6V

F igure 4

This curve shows output-voltage regulationversus output current.


ideasdesign

The classic three- ortwo-op-amp instru-mentation-amplifi-

er circuits are standardways to amplify a small-amplitude differentialsignal contaminatedwith high common-mode noise. In some ap-plications, the signalsource is floating withhigh-series-output im-pedance and thusrequires an appro-priate high-input-im-pedance amplifier. ThisDesign Idea proposes analternative approach us-ing a simplified amplifi-er circuit (Figure 1). The basic principleis to sense the current in the amplifier in-put B (I

B) and inject a current of the same

value in the amplifier input A (IA),by com-

bining a virtual-ground transimpedanceamplifier (A

1) with a voltage-controlled

current source (G1). Thus, G

1balances the

common- mode interference currents. In

addition, the voltage at input B is at vir-tual-ground potential.

A practical circuit is a two-electrodebiosignal amplifier for electrocardiogram

signals (Figure 2). IC2B

is the transimpedanceamplifier. The feed-back capacitor, C

FB,

ensures circuit stabili-ty. The INA134 differ-ence amplifier, IC

1, and

the op amp, IC2A

, makeup a high-quality, bidi-rectional voltage-con-trolled current source.You could use manysimilar ICs, such asINA132, 133, 152, 154,105, or AMP03, for IC

1.

The remaining part ofthe circuit comprisestwo conventional non-inverting stages. Theproposed circuit can beuseful in many two-wire or two-electrodeapplications, in whichyou need to maintainhigh amplifier input-impedance values.

OUTA

BZFB

A1

A2

TWISTEDPAIR

ZG/2

ZG/2

VG

IA

G1

IB

edn030724di3288fig1Heather

+

+

F igure 1

Amplifier and current source emulate instrumentation amplifierDobromir Dobrev, Jet Electronics, Sofia, Bulgaria

A voltage-controlled current source andan inverting amplifier emulate an instru-mentation amplifier.

_

25k 25k

25k

300k

300k

24k

15 nF

15 nF

2 µF

10 nF

OUT

33 pF

IN (+)

IN ()

25k

39k1.5M

1k

24k

1k

_

+

TL072

_

+

TL072

_

+

_

+

TL072

+TL072

IC1

CFB

IC2A

IC2B

IC3B

IC3A

INA134

F igure 2

This biosignal amplifier has the high input impedance that medical applications require.


ideasdesign

Accumulating enough samples toeffectively and accurately measure lin-earity errors in pipeline converters at

production test and minimizing test timeare difficult enough. Add to that multiplesites, multiple channels, and the expenseof multiple custom-instrument resourcesduring periods of low capital expenditure,and engineers mustthink creatively to in-crease throughput with-out sacrificing yield.Many test approaches arebeginning to rely moreon FPGAs. These ICs’high speeds and flexibleusage lend them well toATE (automated-test-equipment) shortfallworkarounds and paredown final test time,which could add up tothousands of dollars insavings, depending ontime saved and volume.But development ofFPGA designs can betime-consuming and ex-pensive; outsourced de-signs can cost more than$100,000, depending oncomplexity. Also, thehardware-histogram ca-pability of many ATEsystems is expensive, andyou must multiplex it tomultiple sites, which re-duces its time-saving effectiveness. ThisDesign Idea pres-ents a simple, discretehardware-histogram cir-cuit module (Figure 1), which uses off-the-shelf components, requires no soft-ware, is easy to debug, and is easy tomultiply to many sites and channels.

The circuit of Figure 1 shows how youcan configure a FIFO memory, a staticSRAM, and a bus register to generate fasthardware histograms for linearity testsand still allow straight data acquisitionfor other tests. The main purpose of the

FIFO memory is to collect data at thespeed of the DUT (device under test), be-cause, with all the data-swapping that oc-curs during the histogram routine, thecycle is slower than the DUT. But it alsoreduces switching noise in the test circuitby keeping the outputs and the other de-vices “quiet” during the initial acquisi-

tion.And, because many high-speed con-verters require low-jitter sources, the useof the FIFO memory eliminates the needto synchronize the test head with exter-nal sources by using the system clock torun the rest of the circuit.

The SRAM stores each bin count inthe address whose value is equal to thecode being accumulated. The memoryis generally underused, because part of

the memory holds a look-up table of allpractical bin counts. Rather than use anadder or a counter to implement thebin-count function, which would re-quire an extra IC, this circuit imple-ments data1 by storing each look-upentry in the address whose value is oneless than the value stored at that loca-

tion, not including bit 16. Address-bit16 keeps the bin counts and look-uptable in different columns. When eachsample routes from the FIFO memoryto the address bits, the FIFO memory’soutput becomes disabled as the bincount for that code appears on the bus.The bus register’s “bus-hold” functionconveniently holds the current bincount on the address lines while the

2468

10121416182022242628303234363840

D[0]D[1]D[2]D[3]D[4]D[5]D[6]D[7]D[8]D[9]

D[10]D[11]D[12]D[13]D[14]D[15]WCLK

GNDVDDGND

P1BCONNECTORQSE-020-01-L-D-A

P1ACONNECTORQSE-020-01-L-D-A

P2ACONNECTORQSE-020-01-L-D-A

P2BCONNECTORQSE-020-01-L-D-A

13579

111315171921232527293133353739

B[0]B[1]B[2]B[3]B[4]B[5]B[6]B[7]B[8]B[9]B[10]B[11]B[12]D[13]B[14]B[15]VDDGNDVDDGND

2468

10121416182022242628303234363840

B[16]LEBAOEBAOEABLEARGNDVDDGNDVDDGNDVDDGNDVDDGNDVDDGNDVDDGNDVDDGND

A[16]13579

111315171921232527293133353739

MRSFF

RCLKREN

OEOE_RWE_RGNDVDDGNDVDDGNDVDDGNDVDDGNDVDDGNDVDDGND

MRS78

FF75

RCLK62

REN61

OE59

LEAB2/27

WCLK 80

OEAB1/28

OEBA29/56

LEBA30/55

A[0-15]D[0-17]

IC1FIFO

SN74V293

IC2SRAM

CYC1011CV33

IC3REG RECEIVER

SN74LVTH16543

D[0-15] Q[0-15] A[0-15]

D[0-15]

B[0-15]Q[0-17] B[0-15]

A[0-15]

OE 41WE 17

D[0-15]

A[0-16]

Hardware histogram speeds ADC testTony Zizzo Jr, Texas Instruments, Tucson, AZ

A hardware-based histogram system for testing ADCs uses off-the-shelf components.

F igure 1


ideasdesign

SRAM’s address-bit 16 is toggled to ac-cess the count look-up table, and thebin count1 appears on the bus. Thebus register latches in the new bincount while the FIFO memory re-asserts the sample data.

The SRAM then accesses the bin count(address-bit 16 reset) in write modewhen the bus register reasserts the newbin count with the FIFO memory dis-abled. This cycle plays out until the his-togram is complete and the data is readthrough the bus register to the test head.Figure 2 shows the timing scheme. Al-though the FIFO memory has a depth ofonly 64 kbytes, note that the FIFO mem-ory can be filled multiple times and thehistogram can be updated multiple timesuntil the SRAM is cleared. You en-counter no overflow, regardless ofbus width, as long as no bin count ex-ceeds 16,383. The look-up table can bewritten before any device is tested, and thebin counts can be reset between tests

when the handler is binning. This circuitis particularly useful when your applica-tion requires multiple sites or multiple

channels, because you can simply plug theinexpensive module into other sites orchannels and operate it in parallel.

OE

WE

OEBA

LEAB

LEBA

0 nSEC 10 nSEC 20 nSEC 30 nSEC 40 nSEC 50 nSEC 60 nSEC 70 nSEC

OE

RCLK

QN

AN/DN

A16

N N N+1

SAMPLE SAMPLE SAMPLE

N+1 N+1 N N

F igure 2 This graphic shows the histogram cycle timing for the circuit in Figure 1.

www.edn.com November 27, 2003 | edn 87


At its invention roughly two dec-ades ago, STM (scanning tunnelingmicroscopy) created a sensation be-

cause it was the first technology to makeatomic-scale-resolution imaging a rou-tine procedure. An essential requirementfor the practical application of STM issome means for the reproducible fabri-cation of supersharp, atomic-scale needletips. One way to make the tips is to etchthem from short pieces of platinum wirein a calcium-chloride electrolyte bath.Applying an ac voltage between the elec-trolyte and the wire generates a chemicalreaction accompanied by vigorous fizzingat the surface of the liquid. This reactionetches the platinum, causing the wire toneck down and eventually break into two

pieces. If the etching current turns offwithin milliseconds of the wire’s break-ing, then the point of separation remainssupersharp. This sharp point is suitablefor use as a high-quality STM tip. Swiftinterruption of the current, however, isessential to tip sharpness, because onlya few milliseconds of overetch suffice todull and ruin the tip. The circuit in Fig-ure 1 achieves precision etch-termina-tion by using relay-actuated etch turn-off based on the sudden drop in etchcurrent that occurs when the wire parts.Precision sensing and full-wave rectifi-cation of the etch current is critical tocircuit operation; the circuit achieves thisprecision by using an unusual differen-tial-input rectifier.

Precision, full-wave rectification oflow-level ac signals to a dc format is acommon signal-processing function;many classic rectifier topologies accom-

+

+

+

D1

D2

Q12N3906

~40 mA

Q22N3906

Q32N4401

C147 µF10V

ETCHCURRENT

0.35WR1

R2

C2

START

OUT/IN

FULL-WAVEPRECISION RECTIFIER

1N914

1N914

1N914

8

14

1

5 6

7

11

42

3

9

10

13

12

12V

3k

100k* 0.22 µF

0.39µF

10k

453*

100 µF6V

100k

390k

5.6k

820

10k

10k*

THRESHOLDSET: 0 TO 100

10-TURN+ DIAL

NOTES:ALL OP-AMPS ARE LM324s. * = 1% METAL FILM.

FILTER

COMPARATOR

RUN

STOP

RELAY: RS275-248 15V12V AC 120V AC

4 1N4004

470 µF25V

60 Hz AC FROM VARIAC

IC1A

IC1B

IC1C

IC1D

7812

I

O

G

+

+

+

+

12V

14

F igure 1

Circuit controls microneedle etchingStephen Woodward, Marine Sciences, Chapel Hill, NC

This etch-control circuit produces supersharp microneedles by terminating the etching process at precisely the right time.

Circuit controls microneedle etching......................................87

Circuit removes relay-contact bounce ....................................88

Log-ratio amplifier has six-decade dynamic range ..........................90

VCXO makes inexpensive dual-clock reference ......................................92


The best ofdesign ideas Check it out at:

www.edn.com


ideasdesign

plish this function. But the accuracy oftypical precision rectifiers depends on theprecise matching of resistor ratios. More-over, op-amp input-offset voltages limitthe accuracy of these standard circuits.The offset error generally limits sensitiv-ity to input spans no smaller than somehundreds of millivolts. The converter inthis design avoids these faults and adds anumber of new and useful features. Thedifferential ac signal to be rectified goesto the noninverting inputs of op ampsIC

1Aand IC

1B (Figure 1). Rectification

proceeds as follows: Consider a signal ex-cursion,V

IN, that drives IC

1A’s input more

positive than IC1B

’s. Amplifier IC1A

re-sponds by driving diode D

1 into conduc-

tion, thereby forcing R2

to track the in-

put. Amplifier IC1B

responds with a neg-ative output excursion, forcing transistorQ

2to conduct sufficiently to cause the in-

verting input of IC1A

and the bottom endof R

1to track. Q

2’s emitter current, and,

therefore, collector current is then IV

IN/R

2V

R1/R

2; Q

2is a high-alpha tran-

sistor.The respective roles of the amplifiers

reverse for input excursions of the oppo-site polarity, with D

2 and Q

2 conducting.

The match of Q1

and Q2

alpha values,which is typically 0.3% or better, is theonly limit on rectification symmetry.This precision rectifier is thereforeunique in that neither rectification sym-metry nor common-mode rejection,which exceeds 60 dB, depends on resistor

matching. Meanwhile, C2

affords ac cou-pling, which eliminates offset-voltage-re-lated errors. Operation of the rest of theetch controller is straightforward. IC

1C

implements a unity-gain, two-pole But-terworth lowpass filter for good ripple at-tenuation without excessive time delay.Etching begins when you push the Startpushbutton. The etch-current compara-tor, IC

1D, then drives Q

3 to keep the relay

energized until the etch current drops be-low the level set by the Threshold Set po-tentiometer. IC

1D’s output then drops

low, turning Q3off, opening the relay, and

terminating the etch. The result is a serv-iceable, atomically sharp scan tip almostevery time.

Advances in semiconductor tech-nology have allowed ICs to replacemany mechanical relays, but relays

still dominate in high-current circuitsthat must stand off high voltages of ar-bitrary polarity. Contact bounce in those

relays, however, can prove troublesome todownstream circuitry. One approach tocontact bounce combines a relay with ahot-swap controller. Such controllers areincreasingly popular as the means forswitching system components withoutshutting down the system power. In Fig-ure 1, a relay contact replaces the pin ofa mechanical connector. The drive circuit

drives the relay closed, and that relay clo-sure connects the input of the hot-swapcircuitry to the power supply: 28V, in thiscase. The hot-swap controller, IC

1, keeps

the p-channel MOSFET, Q1, off for a

minimum of 150 msec after the inputsupply reaches a valid level.That delay allows ample timefor contact bounce in the re-lay to subside. After the 150-msec delay, IC

1drives

the MOSFET gate suchthat the output voltage slewsat 9V/msec. This controlledramp rate minimizes the in-rush current, thereby reduc-ing stress on the power sup-ply, the relay, and capacitorsdownstream from the hot-swap controller.

An example of relay con-tact bounce shows threebounces with an inrush-cur-rent peak of almost 30A

(Figure 2). The top trace is output volt-age at 10V/division, the lower trace is in-put current at 5A/division, and theoutput load is 54 in parallel with100 F. Use of the Figure 1 circuit underthese conditions yields a better picture(Figure 3). The delayed rise in outputvoltage is clearly visible, with no hiccupsarising from contact bounce. The input

current shows much less variation, peak-ing under 1.5A before settling to a steady-state value of 500 mA.

GND GND

28VOUT

TO SYSTEMPOWER LOAD

FROMPOWER SUPPLY

DRIVECIRCUIT

6

45

1

VS GATE

ON

GNDPGOOD

DRAIN2 3

2

13

4

R1100k

Q1MTD20P06K1

IC1MAX5902F igure 1

Circuit removes relay-contact bounceJohn Guy, Maxim Integrated Products, Sunnyvale, CA

A hot-swap controller IC and external MOSFET removes con-tact bounce from relay K1.

The mechanical relay, K1, byitself exhibits contact bounce

on closure as shown.

The Figure 1 circuit removesrelay-contact bounce and

reduces inrush current.

F igure 2

10V/DIV

500 mA/DIV1 mSEC/DIV

10V/DIV

5A/DIV100 SEC/DIV

F igure 3


ideasdesign

You need optical-power monitor-ing to guarantee overall system per-formance in fiber-optic communi-

cation systems. Logarithmic-signal pro-cessing can maintain precise measure-ments over a wide dynamic range. Thewide-dynamic-range signal undergoescompression, and the use of a lower res-olution measurement system then savescost. As an example of this technique,consider a photodiode with responsivityof 0.5A/W that converts light energy to acurrent of 100 nA to 1 mA. With a four-decade dynamic range and 1% error, therequired measurement resolution is0.01104, or 1 ppm. This measurementrequires a 20-bit ADC. Instead, you cancompress this input to a 0 to 4V range us-ing a log-ratio amplifier and then use a10-bit ADC, substantially reducing thesystem cost. Programming the referencecurrent allows shifting the output voltageto the desired level. You can customizeand use the circuit in Figure 1 in appli-cations involving unusual combinationsof dynamic range; input signal, such as

voltage or current; polarity; and scaling;or operations such as log products andratios. Log-ratio amplifiers find applica-tions in wide-dynamic-range ratiometricmeasurements, which measure an un-known signal against a variable-currentreference. The transfer function of thecircuit in Figure 1 is:

where K is the output scale factor, IIN

isthe current that the photodiode gener-ates,V

Tis a temperature-dependent term

(typically, 26 mV at 25C and propor-tional to absolute temperature), and I

REF

is the reference current. VOUT

0 whenI

INI

REF. For proper operation, I

IN/I

REF

should always be greater than 0. The out-put of the log-ratio circuit can be posi-tive, negative, or bipolar, depending onthe ratio of I

IN/I

REF. The 4V full-scale in-

put range of the ADC sets the 4-mA full-scale input-current range. ProgrammingI

REFto a value of 40 to 600 A places the

output in the middle of the measurementrange.

The components give an output-scalefactor of 1. This circuit has an outputdefined over a range of 4.5 decades ofsignal current, I

IN, and 1.5 decades of ref-

erence current, IREF

(limited by the load-driving capability of the reference for atotal six-decade range. For most applica-tions, you would use only a portion of theentire six-decade range. By determiningthe range of the expected input signalsand computing their ratios, you can usethe equations to predict the expected out-put-voltage range.You can assign I

REF and

IIN

to match device performance to thecurrent range, but you should observepolarity.

A log amplifier generally depends onthe nonlinear transfer function of a tran-sistor. The general transfer function of alog amplifier is related to I

S and V

T, which

both depend on temperature. IS

is the

+

+

VCC

IREF

VCC

IIN

2

1/2 AD8626

1/2 AD8626

10 µF 1 µF

BAND-WIRESERIAL

INTERFACE

3

V

V+

1

330 pF

3 2

1

3

6 B

2

4REF1912.048V

REFERENCE

330 pF

VEE5V

5VVCC

V+

V

VIN SCL

DOU

VRE VD

VIN

AGN CONV

AD7810MICRO-

PROCESSOR

LARGE-AREAPHOTODIODE

R32.2k

R215.7kR1(T)

1k

TEMPERATURECOMPENSATED

1 C1

B1

E1

C2

B2

E2

2

3

7

6

5

MAT02/AD

SHDN

VS

GND

CS SDI

3600A

AD5201

50-k 33-TURN DIGITAL AD5201 POTENTIOMETERDIGITAL TRIM FROM 3600 TO 50,000

W

CLK

SLEEP OUT

F igure 1

Log-ratio amplifier has six-decade dynamic rangeReza Moghimi, Analog Devices, San Jose, CA

This circuit is a programmable, temperature-compensated log-ratio amplifier.


ideasdesign

This Design Idea describes an inex-pensive circuit to generate two ex-tremely high-quality, crystal-clock-

reference-signals, one of which is aPWM-controlled VCXO (voltage-con-trolled crystal oscillator) clock signal(Figure 1). The design also includes cir-cuitry to statically switch and hold theVCXO at its nominal fixed frequency ofoperation (equivalent to 50% PWM)without requiring any external PWMstimulus. Most digital audio/video mi-croprocessor-based systems today requireseveral independent clocks with low jit-ter and the potential adjustability aVCXO provides. The described circuit re-places two expensive monolithic VCXOand crystal oscillators at a fraction oftheir cost and provides much higherquality output signals than the mono-lithic solutions can generate, especially atthe control limits of the VCXO (100%deviation). The circuit generates signalswith higher stability, much lower jitter,lower operating voltage (3.3 versus 5V)

and a wider VCXO pull range than com-parable monolithic approaches at lessthan one-third of their cost.

You can use the circuit in a wide vari-ety of applications; the indicated com-ponent values make it a perfect fit for adigital audio/video system, such as a dig-ital video recorder, digital camera, or set-top box. The circuit is well-suited to sin-gle-chip, media-processing applicationsthat require adjustability, low cost, andlow-jitter performance, such as systemsbased on Equator’s (www.equator.com)broadband-signal processors. Thesetypes of systems generally require a fixedfrequency, such as 25 or 33 MHz, for theprocessor subsystem (Ethernet, PCI bus,for example) and an adjustable 27-MHzreference clock for the audio/video refer-ence subsystem. A PLL system generallycontrols the 27-MHz reference clock.(This PLL is usually implemented in soft-ware with PWM outputs from the mi-croprocessor controlling the 27-MHzclock’s deviation.) This approach guar-

antees a correct synchronization of theaudio and the video data streams to eachother and the broadcast source. The clockrequires 50-ppm adjustability, and thecircuit in Figure 1 provides more than70 ppm. The circuit suits high-volumemanufacturing, the highest quality signal(lowest jitter), and the lowest productioncost.

The design incorporates several novelcircuit features, such as both overtone-and harmonic-crystal operation, use ofinexpensive voltage-controlled capacitors(varactor diodes), a single 3.3V power-supply operating voltage, and a selectable50%-duty-cycle, 27-MHz-operation,fixed-frequency mode. The fixed-fre-quency mode allows operation at 27MHz without the PLL-PWM circuit’shaving to provide a 50% duty cycle, po-tentially freeing up hardware and soft-ware resources in the microprocessor thatusually generates the PWM signal. Thismode is usually invoked when the au-dio/video signals are generated internal-

VCXO makes inexpensive dual-clock referenceSaid Jackson, Equator Technologies Inc, Campbell, CA

transistor’s collector saturation current,and V

Tis the transistor’s “thermal volt-

age.” To overcome this temperature de-pendency, this design uses a matched pairof MAT02 transistors to cancel the I

S

temperature drift and a temperature-sensitive resistive voltage divider to com-pensate for the temperature coefficient ofV

T. The heart of the I

REFgenerator is a

REF191. You adjust its output with anAD5201 digital potentiometer. Thismodification allows you to program the

reference current in 33 steps, from 40 to600 A.

The combination of the REF191 andthe AD5201 provides a current sourcethat is stable with respect to time andtemperature. For higher resolution, youcan use the 1024-position AD5231. TheAD8626 is a dual precision-JFET-inputamplifier with true single-supply opera-tion to 26V, low power consumption, andrail-to-rail output swing, allowing a widedynamic range. Its output is stable with

capacitive loads in excess of 500 pF. Fig-ures 2 and 3 show the transfer functionof the log-ratio amplifier at the input ofthe ADC. The output is limited to 0 to 4Vto match the unipolar input-voltagerange of the AD7810 ADC.

Reference1. Sheingold, Dan, Editor, Nonlinear

Circuits Handbook, Analog Devices,ISBN: 0-916550-01-X.

IREF=570 A, IIN=100 nA TO 4 mA.

4V

3V

2V

1V–10 –30 –100 –300 –1k –3k –10k

V (V65:OUT) I (R86)/ I (V43)

F igure 2

VOUT has IREF programmed to full scale of 570 A.

IREF=40 A; IIN=100 nA TO 4 mA.

3V

2V

1V

0V–1 –3 –10 –30 –100k –300k –1k

V (V65:OUT) I (R86)/ I (V43)

F igure 3

VOUT has IREF programmed to zero scale of 40 A.


ideasdesign

ly to the system, such as when playingback from a hard drive, and audio/videosynchronization to an external source isunnecessary.

The circuit includes IC1, a 32-MHz,

PCI-based fixed-frequency referenceclock; IC

2, a PWM multiplexer; and IC

3,

a 27-MHz VCXO clock. A Fox (www.foxonline.com) 32-MHz, third-overtonecrystal serves to generate both the PCIreference clock and the 50%-duty-cyclereference for the fixed-frequency mode.A third-overtone, 32-MHz part is less ex-pensive and more mechanically robustthan a 33-MHz, fundamental-modecrystal at the expense of running the PCIclock slightly slower. The tank circuitaround inductor L

1and capacitors C

1and

C3

prevent the crystal from oscillating atits fundamental mode of approximately11 MHz. This tank circuit works by cre-ating an LC series-resonant circuit be-tween L

1and C

3that has natural reso-

nance at approximately 24 MHz, whichis approximately 75% of the desired 32-MHz frequency. Note that C

1is large

enough to have no effect on this tank cir-cuit’s resonance frequency; it merely actsas a dc blocker for inductor L

1. One thing

to avoid is to connect this tank circuit to

the input side of inverter IC1A

. Connect-ing it to the input side of IC

1Acould po-

tentially create a resonant RC circuit withresistor R

1and capacitor C

1acting as the

RC components. This circuit could os-cillate at less than 1 kHz, a frequency atwhich L

1would effectively be a short cir-

cuit, and crystal Y1

would be an open cir-cuit. Placing C

1and L

1on the output side

of IC1A

prevents this spurious-oscillationmode.

By tuning L1and C

3, you can adjust the

circuit to oscillate at a frequency higherthan the third overtone. Oscillation at thefifth, seventh, or even ninth overtone ispossible and is limited only by the per-formance of IC

1Aand the parasitic ca-

pacitance. The 32-MHz PCI reference-clock output also serves as a 50%-duty-cycle reference for the VCXO whenthe VCXO is operating in its fixed-fre-quency, 27-MHz mode. Multiplexer IC

2

selects either this 32-MHz, 50% PWMclock signal or the PWM clock signalfrom a PLL phase comparator (usuallyimplemented in the microprocessor andnot shown in the schematic) to set theVCXO to its fixed-frequency mode. Theadvantage of using the PCI clock for thisfeature is that traditional circuits would

have to generate an analog one-half-VDD

voltage and use an analog multiplexer toset the VCXO at its nominal frequency.Thus, this design avoids the necessity ofusing accurate and expensive analog cir-cuitry and also generates a reference sig-nal with much higher immunity to tem-perature, for example, than analogapproaches could provide.

Digital multiplexer IC2

forwards oneof two PWM signals to the VCXO basedon the state of the fixed-versus-VCXO se-lected input signal. The PWM-input sig-nal serves as the PWM reference input tothe VCXO if the select pin is high, and thedesign uses the 50%-duty-cycle PWMsignal from the PCI clock circuit if the se-lect pin is low. The design uses a 74LVC00chip as a multiplexer because of its readyavailability and low cost. IC

2Cbuffers the

PWM signal, and the cascaded RC filtercomprising R

8, R

9, C

8, and C

9 then low-

pass-filters the signal. The analog-voltagestability of the VCXO control voltage atthe output of this RC filter depends onthe quality of the V

DDsupply to IC

2C. IC

2

receives its 3.3V power through an RC fil-ter: R

4with C

4and C

5. IC

2with R

8, R

9, C

8,

and C9

thus form a highly accurate D/Aconverter.

IC1A74LVC04

IC2A

IC2C

IC2B

IC2D

IC1B74LVC04

21

1 2

C210 pF

R11M

R3560

R43.3

R83.3k

R93.3k

R7560

R656

R51M

R1047k

R1147k

C310 pF

C50.1 F

C80.01 F

C422 F10V

C11000 pF

L147 H

32-MHz,THIRD-OVERTONE

FOXSD/320-20Y1

3

2

1 EPCOS B82494-A1472-K

4 REF_32 MHz

23

165

4

14 14

914

10

1411

12

13

32 MHz

FIXED_VS_VCXO_SELECT

PWM_INPUT

PWM FROMPLL PHASE

COMPARATOR

TSSOP1474LVC00APWDH

TSSOP1474LVC00APWDH

TSSOP1474LVC00APWDHTSSOP14

74LVC00APWDH

PWM MULTIPLEXER

8

3.3V

PWM SIGNAL

C91 F

C110.01 F

C70.01 F

Y2

C103.3 pF

C60.01 F

CONTROLVOLTAGE

D1BB133

PHILIPS

D2BB133

PHILIPS

1 2

20-PPM, 18 pF-LOAD,27-MHz CRYSTAL SMD

CITIZENHCM49-27.000MDDUT

IC3A74LVC04

IC3B74LVC04

2

3 4

1

REF_27 MHz

AUDIO/VIDEO VCXO

F igure 1

This circuit, ideal for A/V applications, generates two high-quality clock-reference signals.


ideasdesign

The VCXO’s lowpass filter uses a cas-caded design, because stray 32-MHznoise could pass across the small para-sitic capacitance inherent in R

8into the

analog VCXO-control voltage. Cascad-ing also has the advantage of filteringnoise with 12 dB of attenuation per oc-tave for frequencies greater than 5 kHz,thus creating a noise-free VCXO controlvoltage. The 27-MHz audio/video VCXOcircuit uses a fundamental-mode crys-tal that varactor diodes D

1and D

2 load

with adjustable capacitance. These back-biased diodes’ junction capacitance de-pends highly on the bias voltage. Larg-er bias voltages lower their capacitance,thus lowering the load across the crystaland increasing its oscillation frequency.Diodes D

1and D

2find use in many

tuners and are widely available. Capaci-tors C

6and C

7again function as dc

blockers.The adjustment range of the VCXO is

approximately 27 MHz2 kHz, whichcalculates to approximately 74 ppm.The circuit is stable with very low jitterthroughout its entire 0 to 100% VCXO-adjustment range.You can use the VCXOsubcircuit by itself to generate a spread-spectrum clock for EMI compliance.Youdrive the VCXO voltage or PWM duty cy-cle from 0V (0%) to 3.3V (100%) with atriangular-shaped drive signal. The fre-quency of the triangular wave must bebelow the PWM RC filter’s cutoff fre-quency of 24 Hz to be effective. The os-cillator circuit’s jitter depends on thepower-supply quality of IC

1, IC

2, and IC

3

and on the noise inside these chips. Toavoid crosstalk between 32 MHz and 27MHz, the design uses two chips. Imple-menting buffers IC

1B and IC

3Bwith sepa-

rate chips, thus separating the power-supply loading from the sensitive buffers,IC

1Aand IC

3A, could further reduce jitter.

With independent clock buffers and a

low-noise power supply, this circuit hasexhibited a maximum cycle-to-cycle jit-ter of less than the 60-psec limitation ofthe HP54720D oscilloscope that meas-ures it. This figure betters the jitter char-acteristics of popular crystal oscillatorsand VCXO chips available for consumerapplications. It also does not suffer fromunstable operation at its adjustmentmargins (operating at 100% devia-tion), as designers commonly encounterwith monolithic components. Anotheradded benefit is that it achieves its 74-ppm adjustment range with only a single3.3V power supply, whereas monolithicapproaches usually require a 5V powersupply and control voltage. Finally, it of-fers all this performance at a total priceof less than $1.40 in large quantities byusing only commonly available, off-the-shelf components. This figure comparesto $3 to $6 parts cost with monolithic ap-proaches.

www.edn.com December 11, 2003 | edn 83


This Design Idea de-scribes a high-intensity,rechargeable flashlight

system that you can buildfrom a 6V lantern-typeflashlight. The rechargeablebattery comprises four 2V,2.5-Ahr (ampere-hour) SLA(sealed lead-acid) cells, sim-ilar in size to a stan-dard D-sized bat-tery. SLA cells are especiallywell-suited to poweringflashlights because of theirlow self-discharge rate.NiCd (nickel-cadmium) orNiMH (nickel-metal-hydride) cells canlose as much as 1% of their charge perday, compared with less than 0.2% perday for SLA cells. SLA cells are also easyto charge and can withstand abuse. Theflashlight in this design uses a kryptonhigh-intensity lamp. Maglite (www.maglite.com) makes this lamp as a re-placement lamp for its line of flashlights.The lamps are extremely bright; have astandard miniature-flange-base, built-inlens; and are available in five- or six-cellversions. (Manufacturers typically rateflashlight lamps by the number of alka-

line cells the flashlight uses.) The lamp’soperating voltage is approximately 1.25Vper cell, which makes the lamp voltage ofa six-cell lamp equal to 7.5V. This designuses a six-cell lamp for this flashlight, al-though you could also use a five-cell,6.25V lamp. A five-cell lamp provides ap-proximately 30% more light output buthas a shorter lamp life. To increase lamplife, this flashlight includes the soft-startcircuit in Figure 1.

Incandescent lamps inherently drawlarge start-up currents because of the fil-ament’s relatively low resistance when it

is cold. A tungsten fila-ment’s resistance is typi-cally 10 times lower whencold than it is when atnormal operating temper-ature. When the full bat-tery voltage suddenly hitsa cold filament, the inrushcurrent is typically 10times the normal operat-ing current, and this in-stant is when a lamp islikely to fail.Adding a soft-start circuit nearly elimi-nates this large inrush cur-rent, allowing for a higherpower lamp and reducing

the probability of thelamp’s failure at turn-on.The soft-start circuitconsists of an n-channelMOSFET in series withthe lamp, which rampsthe lamp voltage up at acontrolled rate to reducethe inrush current. Agate-to-source capacitorcontrols the ramp speed.The lamp turns on in ap-proximately 2 sec. Figure2 shows the dramatic re-duction in lamp inrushcurrent when you use

the soft-start circuit.The charger is a 200-kHz step-down

switching regulator using current-limit-ed constant voltage to charge the battery(Figure 3). When a discharged batteryconnects to the charger, the charge cyclestarts in a 1A constant-current mode. Asthe battery accepts charge, the battery volt-age increases until it reaches the pro-grammed charge voltage of 2.5V/cell (10Vtotal).At this point, the charge cycle entersconstant-voltage mode. During constant-voltage mode, the charge current drops ex-ponentially. When the charge currentreaches approximately 10% (100 mA) ofthe programmed current, the charge volt-age drops to a float voltage of 2.35V/cell

+

FIVE- OR SIX-CELLMAGLITE

KRYPTON LAMP

IRLR024IRFR024

TOCHARGER +

ON

OFF

10k

680k

4.7 F

FOUR SEALED-LEAD-ACIDCELLS 2V, 2.5 AHR EACH

F igure 1

Rechargeable flashlight obsoletes lantern batteryFran Huffart, Linear Technology, Milpitas, CA

This soft-start circuit reduces inrush current, thereby prolonging lamp life.

F igure 2

Using the soft-start circuit in Figure 1 provides a dramaticdecrease in inrush current.

LAMPINRUSH

CURRENT(A)

10

8

6

4

2

0

LAMP CURRENT FIVE-CELL LAMP800 mA AT 8V=6.4W

NO SOFT START 1 mSEC/DIV

WITHSOFT START

100 mSEC/DIV

LAMP TURN-ON TIME (1 OR 100 mSEC/DIV)

Rechargeable flashlight obsoletes lantern battery ................................................83

Single cell flashes white LED ......................84

Hot-swap controller handles dual polarity ....................................................88

Temperature monitor measures three thermal zones ......................................90


84 edn | December 11, 2003 www.edn.com

ideasdesign

(9.4V total). This dual-voltage approachprovides a faster charge and also providesan LED indication when the battery isnearly fully charged.The charger keeps thebattery at this float voltage, thus keepingthe battery in a fully charged condition.You can leave the charger indefinitely con-nected to the battery without damage tothe battery, although battery damage canresult if it is fully discharged—when thebattery voltage is less than 1.8V/cell—ei-ther through use or self-discharge. TheFLAG pin is an open-collector output that

indicates when the charge current hasdropped to approximately 10% of the fullprogrammed charge current.

A wall adapter with an output from13V, 1A to 26V, 0.5A provides power tothe charger. This design uses all surface-mount components to reduce the over-all size of the charger. The pc-board lay-out should include wide ground tracesthat expand to larger copper areas tominimize the possibility of overheatingthe IC. The flashlight housing features a3- to 4-in. reflector and has a handle on

top; it is readily available from RadioShack (www.radioshack.com) and otherelectronics outlets. The light is designedfor a 6V lantern battery, but this designreplaces the lantern battery with four D-sized, SLA cells. The cells leave enoughroom for the soft-start circuitry. Othermodifications include replacing theswitch with a high-quality SPDT switchand soldering all the connections for in-creased reliability. A dc power jack con-nects the flashlight to the charger.

D1

VBAT IS 10V FOR CHARGECURRENTS GREATER THAN100 mA AND 9.4V FORCHARGE CURRENTS LESSTHAN 100 mA.

Q2Q1

D2

VCC

VCC

VC

PROG

CAP

FLAG

BOOST

SENSE

BAT

SW

VFB

VIN FROM AC WALL

ADAPTER13 TO 24V

28-PIN SSOP

LT1571-1

23

24

21

20

22

7

5

4

10

19

9 232k1%

976k1%

100k

LED

STATUS INDICATORLED BRIGHT: CHARGELED DIM: FLOATLED FLASHING: NO BATTERYLED OUT: NO INPUT POWER

PROGRAM CHARGECURRENT (5k FOR 1A)

82010k

12k

82k

3k

4.99k

300

FLASHLIGHT

FOUR CELLS8V LEAD-ACID

82.5k1%

NOTES:GROUND PINS 1, 2, 3, 11, 12, 13, 14, 15, 16, 17, 18, 25, 26, 27, AND 28 TO GENEROUSAMOUNTS OF PC-BOARD COPPER FOR BEST THERMAL AND ELECTRICAL PERFORMANCE.Q1 AND Q2 ARE VN2222s, OR 2N7002s.

D1 AND D2 ARE 1A ,30V SCHOTTKY DIODES.

0.68 µF

22 µF

0.022 µF

10 µF

1 µF

0.33 µF

15 µH1N4148

+

+

(SEE NOTE)

VBAT

F igure 3

This battery charger uses current-limited constant voltage to charge the lead-acid cells in the flashlight.

Many portable appliances and oth-er products that must operate froma single cell are restricted to work-

ing at very low voltages. It is thus difficultto drive white LEDs that typically have aforward voltage of 3 to 5V. The ability toflash the LED with a supply voltage as lowas 1V presents additional complications.The circuit in the Figure 1 provides a dis-

crete approach to these problems and al-lows a white LED to flash at a rate set byan RC time constant. Components Q

1,

Q2, R

3, R

4, and R

5form a simple Schmitt

trigger that, together with R1, R

2, and C

1,

controls the flashing of the LED. Q4, Q

5,

L1, and associated components form a

voltage booster that steps up the single-cell voltage, V

S, to a level high enough to

drive the LED. Transistor Q3

functions asa switch that gates the booster on and offat a rate determined by the Schmitt-trig-ger section.

To understand how the booster sectionworks, assume that Q

3is fully on, such

that Q4’s emitter is roughly at the battery-

supply voltage,VS. Q

4and R

8provide bias

for Q5, which turns on and sinks current,

Single cell flashes white LEDAnthony Smith, Scitech, Biddenham, Bedfordshire, UK


ideasdesign

IL, through inductor L

1. The inductor

current ramps up at a rate determinedmainly by V

Sand the value of L

1; during

this time, LED1and series diode D

1are re-

verse-biased. The current continues toramp up until it reaches a peak value,I

LPEAK. Q

5 can sustain no further increase,

and the voltage across the inductor at thispoint reverses polarity. The resulting “fly-back” voltage raises LED

1’s anode to a

positive voltage higher than VS, sufficient

to forward-bias LED1

and signal diode D1.

The flyback voltage isalso coupled throughC

3and R

10to Q

4’s base,

thus causing Q4

and,hence, Q

5to turn off

rapidly.The inductor cur-

rent now circulatesaround L

1, LED

1, and

D1, and, as the energy

stored in L1

decays, thecurrent ramps down tozero. At this point, theinductor voltage againreverses polarity andthe negative-goingchange is coupledthrough C

3, rapidly

turning on Q4

and, inturn, Q

5. Current again

begins to ramp up inL

1, and the process re-

peats. The booster section oscillates at arate determined by several factors. Theimportant factors determining the rate ofoscillation include the values of V

S, L

1,

and R8; the forward-current gain of Q

5;

and the forward voltage of LED1. With

the component values in the figure, theoscillation frequency is typically 50 to 200kHz. On each cycle, a pulse of currentwith a peak value equal to I

LPEAKflows

through LED1

and, because this scenariooccurs thousands of times every second,LED

1appears to be continuously on.

The low-frequency oscillator formedaround the Schmitt trigger turns thebooster section on and off at a low rate.To understand how this works, assumethat Q

1is off and Q

2is on. Provided that

Q2

has reasonably large forward-currentgain, you can ignore the effects of its basecurrent and say that V

Sand the R

3-R

5

voltage divider set Q2’s base voltage, V

B2.

With the values of R3

and R5

in Figure 1,V

B2 is approximately 800 to 900 mV when

VS1V. This voltage produces approxi-

mately 300 to 400 mV across R4, resulting

in a collector current of at least 15 A inQ

2with R

420 k. Q

2’s collector current

provides base drive for Q3, which satu-

rates, turning on the booster section andilluminating LED

1. When LED

1is for-

ward-biased, C4charges to a positive volt-

age,VP, roughly one diode drop above V

S.

Timing capacitor C1

now charges via R1

at a rate determined mainly by the val-ues of V

P, R

1, R

2, and C

1. Provided that

you carefully choose the ratio of R1 to R

2,

Q1’s base voltage, V

B1, eventually exceeds

the quiescent level of VB2

(roughly equalto the Schmitt trigger’s upper thresholdvoltage, V

TU), causing Q

1to turn on and

Q2

to turn off. At this point, Q3

also turnsoff, thereby disabling the booster sectionand turning off LED

1.

With LED1

off, VP

rapidly decays, andC

1begins to discharge at a rate deter-

mined mainly by the values of R2

and C1

and by Q1’s base current. The LED re-

mains off until VB2

has fallen below theSchmitt trigger’s lower threshold voltage,V

TL, at which point Q

1turns off, Q

2turns

on, and the booster section again acti-vates, illuminating LED

1. Provided that

R1, R

2, and C

1are large enough, LED

1can

flash at a low rate. For example, if R1

and

R2

have values of approximately 1 Meach and C

1 has a value of 1 F or greater,

a rate of less than one flash per second ispossible. Remember, however, that R

1 and

R2

form a voltage divider that sets Q1’s

base voltage, VB1

; therefore, R2

must besufficiently larger than R

1to ensure that

VB1

can cross the Schmitt trigger’s upperthreshold voltage as C

1charges. With this

fact in mind, you can with some trial anderror fairly easily find the optimum val-

ues of R1, R

2, and C

1necessary for a giv-

en flash rate.The value of V

Psignificantly influences

the charging and discharging of C1, and

VP’s value hence varies according to the

prevailing battery supply voltage, VS.

However, changes in VB2

, which alsovaries with V

S, somewhat balances this

dependence. Nevertheless, the flash rateand duty cycle do vary somewhat as thebattery voltage falls. For example, withR

12.2 M, R

210 M, and C

11 F,

the test circuit’s flash rate at VS1.5V is

approximately 0.52 Hz with a duty cycleof 66%. With a V

Sof 1V, the flash rate in-

creases to approximately 0.75 Hz butwith a lower duty cycle of 44%. TheSchmitt-trigger thresholds, V

LTand V

TU,

are typically approximately 0.7V and1.2V at V

S1.5V, falling to approximate-

ly 0.6V and 0.8V when VS

is 1V.The LED’s intensity is proportional to

Q3

Q4

Q1

R1

VS

VP

R420k

R3100k

R61M

R5750k

C3100 pF

R7100k

R101k

R910k

R8510

C410 nF

C21 nF

R2

VB1 VB2

C1

Q2

+

+

0V

SINGLE CELL1.5V NOMINAL

Q5

L1220 H

ILLED1

WHITELED

D11N4148

F igure 1

This circuit provides boosted voltage and flashes a white LED from a single cell.


ideasdesign

its average forward current and is thus de-termined by the peak inductor current, I

L-

PEAK, and by the duration of the current

pulse through the LED. Provided that L1

is properly rated such that it does not sat-urate, the peak current depends largely onthe maximum collector current that Q

5

can sustain. For a given supply voltage,this figure depends primarily on Q

5’s for-

ward-current gain, and on the value of R8

that you can select to give optimum LEDbrightness at the lowest supply voltage.Experiment with different values of R

8to

get the best intensity for a given LED type.Take care, however, that the peak currentdoes not exceed the LED’s maximum cur-rent rating when V

Sis at a maximum. The

actual value of L1

is not critical, but val-ues in the range 100 to 330 H shouldprovide good performance and reason-able efficiency. The transistor types in thecircuit are not critical; the test circuitworks well with general-purpose, small-signal devices having medium to high

current gain. If possible, select low-satu-ration types for Q

3, Q

4, and Q

5. C

2is not

essential to circuit operation but helps todecouple any switching noise at Q

2’s base.

C4

acts as a charge reservoir and en-sures that R

1can charge C

1from a stable

voltage source (VP) when LED

1is on. Be-

cause the charging current is likely to below, C

4can be fairly small; a value of 10

nF should be adequate. Note that C4must

connect to the junction of D1 and LED

1 as

shown, rather than being charged, via arectifying diode, from the flyback voltageat Q

5’s collector. The reasons for this

caveat are, first, that this approach en-sures that V

Pis only a diode drop above

VS, thereby minimizing the value of R

1

necessary for a given C1charging current.

Also, and more important, this approachplaces the forward voltage of the LED inthe path from V

Sthrough L

1and R

1to

Q1’s base. Because the forward voltage of

a white LED is usually at least 3V, thisconnection prevents Q

1from being

turned on via this route, which couldotherwise cause the circuit to lock in the“off” state.

At first sight, it might appear that youcan turn the booster section on and offby gating current to Q

4’s base, thus obvi-

ating the need for Q3. However, under

certain conditions, once you activate thebooster section, the feedback to Q

4’s base

via C3and R

10is sufficient to maintain os-

cillation without feeding any dc bias toQ

4’s base. Therefore, the only reliable way

to gate the booster on and off is via Q3,

as shown. The test circuit starts up andoperates with V

S as low as 0.9V, although

the LED is dim at this voltage. The LED’sintensity is good at V

S1.5V (equivalent

to a fully charged alkaline cell) and re-mains acceptable with V

S as low as 1V.

The circuit should find applications intoys, security devices, miniature beacons,and any other products that must providea flashing visual indication while oper-ating from a single cell.

Some applications require a hot-swap controller, a circuit-breakerfunction, or both for dual-polarity,

dc-input power-supply rails. In somehot-swap cases, the requirement is basedonly on inrush-current considerations.Control of the inrush current is neces-sary to eliminate connector stress andglitching of the power-supply rails. Oth-er applications may have issues when oneof the supplies fails for some reason. Agood example is a bias supply for a galli-um-arsenide FET amplifier. If you re-move the negative gate bias, then youmust also remove the positive drain sup-ply; otherwise, the device may destroy it-self because of the resulting highdrain current. You can meet boththese requirements by using a single-channel, hot-swap controller.

The circuit in Figure 1 uses a TPS2331,IC

1, in a floating arrangement. The cir-

cuit references the IC’s ground to thenegative input voltage. If the voltage onthe positive rail is too low or the voltage

C51 µF10V

C6CBULK

C11 µF10V

Q22N3906

Q1BSi4936DY

Q1ASi4936DY

Q32N3906

R510.7k1%

R42k1%

R2910k R3

10k

C2CBULK

1

2

3

4

5

6

7

14

13

12

11

10

9

8

GATE

DGND

TIMER

VREG

VSENSE

AGND

ISENSE

DISCH

ENABLE

PWRGD

FAULT

ISET

AGND

IN

IC1TPS2331ID

C3100 pFR1

28.7k1%

R61M

C4, 0.1 µF

5VIN

5VIN

5VIN

5VIN

5VOUT

5VOUT

187

56

3

F igure 1

Hot-swap controller handles dual polarityDan Meeks, Texas Instruments, Manchester, NH

This circuit is a dual-polarity voltage sequencer for low-voltage applications.


ideasdesign

on the negative rail is too high, the cir-cuit cannot attain the 1.225V thresholdat the V

SENSEpin, and the IC turns off. The

VSENSE

pin incorporates approximately 30mV of hysteresis to ensure a clean turn-on with no chatter.

When both supplies are beyond theirrespective thresholds, IC

1turns on, pro-

viding a controlled-slew-rate ramp-upof the two FETs. Note that the circuituses only n-channel FETs, which havelower on-resistance for a given size andcost than p-channel devices. To turn onQ

1Aon, the TPS2331 has a built-in

charge pump that generates a voltageabove the positive rail, thus enhancingthe FET. As the gate voltage builds, Q

3

acts as a linear level translator, sothat Q

1Balso ramps on. The turn-

on speed is a function of the TPS2331’s14-A output current and the value ofC

3. The design uses the FETs based on

the maximum resistance allowed in thedc path and the FETs’ power-dissipationfigures. You can use virtually any sizeFET, depending on the current you wantto control. Take care that the total volt-age span across the TPS2331 does notexceed the maximum rating of 15V. IfIC

1does not float between the input

rails, the negative input may be larger.

Figure 2 shows such an application, inwhich 5V and 12V are the input sup-plies. The main requirement is that thelevel-shifting transistor, Q

3, be able to

handle the higher voltage. This circuitalso allows you to use a positive inputvoltage as high as IC

1’s maximum rat-

ing of 15V.

C51 µF10V

C6CBULK

C2CBULK

C11 µF10V

Q1BSi4936DY

Q1ASi4936DY

Q22N3906

R4

R2910k R3

10k1

2

3

4

5

6

7

14

13

12

11

10

9

8

GATE

DGND

TIMER

VREG

VSENSE

AGND

ISENSE

DISCH

ENABLE

PWRGD

FAULT

ISET

AGND

IN

IC1TPS2331ID

C3100 pF

R1

R61M

NOTE: SELECT R1 AND R4 TO SET THRESHOLD.

C4

0.1 µF

12V IN

5V IN

5V IN

5V IN

5V OUT

12V OUT

187

56

3

F igure 2

This variation on Figure 1’s circuit can handle higher voltages.

You can use an ADT7461 single-channel temperature monitor; anADG708 low-voltage, low-leakage

CMOS 8-to-1 multiplexer; and threestandard 2N3906 pnp transistors tomeasure the temperature of three sepa-rate remote thermal zones (Figure 1).Multiplexers have resistance, R

ON, asso-

ciated with them; the channel matchingand flatness of this resistance normallyresult in a varying temperature offset.This system uses the ADT7461temperature monitor, whichcan automatically cancel resistances inseries with the external temperature sen-sors, allowing its use as a multichanneltemperature monitor. The resistance au-tomatically cancels out, so R

ONflatness

and channel-to-channel variations have

no effect. Resistance associated with thepc-board tracks and connectors also can-cels out, allowing you to place the re-mote-temperature sensors some distance

from the ADT7461. The design requiresno user calibration, so the ADT7461 canconnect directly to the multiplexer. TheADT7461 digital temperature monitor

2N3906 2N3906 2N3906TO HOSTD+ ALERT

VCC

ADT7461

DSDA

SCLTO HOST

ADG708

A2 A1 A0

S1S2

S3S4

D

MULTIPLEXER CONTROLF igure 1

Temperature monitor measures three thermal zonesSusan Pratt, Analog Devices, Limerick, Ireland

This system measures the temperature of three remote thermal zones.


ideasdesign

can measure the temperature of an ex-ternal sensor with 1C accuracy. Theremote sensor can be a monolithic or adiscrete transistor and normally connectsto the D and D pins on theADT7461. In addition to the remote-sen-sor-measurement channel, the ADT7561has an on-chip sensor.

The diode-connected transistors haveemitters that connect andthen connect to the D in-put of the ADT7461, and each of thebase-collector junctions connects to aseparate multiplexer input (S1 to S3).Youconnect the selected remote transistor tothe D input on the ADT7461 by ad-dressing the multiplexer, which addressbits A2, A1, and A0 digitally control. TheADT7461 then measures the tempera-ture of whichever transistor is connectedthrough the multiplexer. The ADT7461measures the temperature of the selectedsensor without interference from theother transistors. Figure 2 shows the re-

sults of measuring the temperature ofthree remote temperature sensors. Thesensor at address 000 is at room temper-ature, the sensor at address 001 is at a lowtemperature, and the sensor at address010 is at a high temperature. When youselect no external sensor, the “open-cir-cuit” flag in the ADT7461 register acti-vates, and the Alert interrupt output as-

serts. You can expand the system to in-clude as many external temperature sen-sors as your design requires. The limitingfactor on the number of external sensorsis the time available to measure all tem-perature sensors. If your design requirestwo-wire serial control of the multiplex-er, you can use an ADG728 in place of theADG708.

TEMPERATURE(˚C)

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

1 18 35 52 69 86 103 120 137 154 171 188 205 222 239 256 273 290

ADDRESS=000

ADDRESS=001

ADDRESS=010

ADDRESS CHANGED HERE

200

150

100

50

0

–50

–100 REMOTE TEMPERATURE LOCAL TEMPERATUREF igure 2

The system in Figure 1 measures ambient (address 000), cold (address 001), and hot (address 010)temperatures.

www.edn.com December 25, 2003 | edn 57

ideasdesign


Many communications systems,including RFID systems and cablemodems, use AM (amplitude

modulation). This Design Idea showshow two DDS (direct-digital-synthesis) devices can imple-ment AM and ASK (amplitude-shift key-ing) over a range of frequencies. TheAD9834 complete 50-MHz DDS IC (Fig-ure 1) has a current output, so you caneasily sum the outputs of two or more ofthem by connecting them to a commontermination resistor. Each AD9834 hastwo internal phase registers, P

0and P

1,

and two internal frequency registers, F0

and F1

(not shown). With each AD9834generating a sine wave at the same fre-quency, the amplitude of the summedsignal depends on the phase of each sig-nal. You can achieve four preset ampli-tude levels—or any on-the-fly level—bysumming the outputs of two AD9834s.

Table 1 shows two AD9834s, IC1

andIC

2, configured to give four output lev-

els. P0A

is phase register 0 for IC1, P

1Ais

phase register 1 for IC1, and so on. You

can select the desired output level witheither the PSEL pins or with the PSELbits in the control register. Figure 2shows the waveforms at the R

TERMsum-

ming junction for the phases used inTable 1. You can achieve any signal levelfrom 0V to a full-scale voltage of ap-proximately 600 mV by programmingthe phase registers with the appropriate

values. Both devices use the same MCLK(master clock), and you need to syn-chronize them to get the correct signallevels at the R

TERMoutput. You achieve

synchronization by simultaneously ap-plying a Reset signal to both parts afterprogramming both parts with the cor-rect phase and frequency. You can ac-complish the synchronization by apply-ing a positive pulse to the Reset pins, oryou can implement a software synchro-nization by setting the reset bit in thecontrol register to one, stopping MCLK,setting the reset bit in the control regis-ter to zero, and then starting MCLK. Ei-

ther method ensures that both parts si-multaneously exit the reset state.

You can easily implement 100% AMwith a single AD9834 by toggling the Re-set pin or the reset bit in the control reg-ister. When the part is in reset, the DAC’soutput is at midscale. The predeterminedsine wave is available at I

OUTwhen the

DDS exits reset. To calculate the magni-tude of the sum of the two signals fromthe AD9834s, represent each signal as arotating vector (Figure 3). You can easi-ly calculate the magnitude and phase ofthe resulting summed vector as follows:If the length of each vector is 1, then:

FSYNC

SCLK

SDATA

MCLK

PSEL FSEL

RESET

IC1AD9834

IOUTA

IOUTB

6.8k RSETFSADJUST

100

FSYNC

SCLK

SDATA

MCLK

PSEL FSEL

RESET

IC2AD9834

IOUTA

IOUTB

6.8k RSETFSADJUST

100

SUM OF SIGNALSFROM BOTH

AD9834s

RTERM100

F igure 1

Two DDS ICs implement amplitude-shift keyingNoel McNamara, Analog Devices, Limerick, Ireland

You can use two DDS chips to implement amplitude modulation and amplitude-shift keying.

Two DDS ICs implement amplitude-shift keying ..................................57

VCO produces positive and negative output frequencies........................58

16-bit adjustable reference uses 8-bit digital potentiometers ........................62



ideasdesign

x1 Cos(45)0.707: y1Sin(45)0.707;

x2Cos(180)1.00: y2Sin(180)0;

x3x1x20.293: y3y1y20.707;

Magnitude of resulting vector:(x3)2(y3)20.765;

Phase of summed vector: 112.5(180Tan1(y3/x3)).

The maximum output-voltage levelthat any one AD9834 can develop acrossthe 100 termination resistor withR

SET6.8 k is 320 mV p-p. Therefore,

the voltage level this example achieves is320 mV0.765244.8 mV. This exam-ple shows that the phase of the resultingsummed vector depends on the phase oftwo input vectors and may result in aphase discontinuity as the phases of the

input vector change. To avoid phase dis-continuity at the transition, you can setthe resultant phase, P3, to a fixed angle,say 180p2360p1.

Sin(2fp1)Sin(2fp2)2Cos(0.5(p1p2))Sin(2f(p1p2)/2).

Desired amplitude: A2Cos [0.5(p1p2)]; p1p2 2Cos1(A/2).

Resultant phase: P3(p2p2)/2.Therefore, p1180Cos1(A/2), and

p2180Cos1(A/2) gives amplitude Awith no phase shift at the transition.

TABLE 1—THE PHASE-REGISTER CONTENTS YIELD FOUR OUTPUT LEVELS FROM THE CIRCUIT IN FIGURE 1Device Phase-register Normalized level Output level with RTERMnumber values () of summed signal 100 and RSET6.8 k (mV)

P0 A 45 P0AP0B(45180) 0.765 223P1 A 95 P0AP1B(45210) 0.426 128P0 B 180 P1AP0B(95180) 1.47 435P1 B 210 P1AP1B(95210) 1.191 350

F igure 2

The waveforms at the RTERM summing junction use the phases in Table 1.

233 mV 350 mV

45+180º 45+210º

95+80º95+210º

300 mV

GND

BSIN(2f180)

0.765SIN(2f105)(SUM OF VECTORS A AND B)

ASIN(2f45)

x2 x1

y2y3

x3

y1

F igure 3

You can calculate the magnitude of the summedsignals from the DDS chips by representingeach signal as a rotating vector.

The circuit in Figure 1 is a quadra-ture-output VCO that provides bothpositive and negative output fre-

quencies, depending on the polarity ofthe control-voltage input. The circuitprovides a function that designers tradi-tionally implement in analog music-ef-fects units, such as Bode/Moog frequen-cy shifters. Bode/Moog shifters usefixed-beat-frequency oscillators at 20kHz and variable sine oscillators that gohigher and lower than 20 kHz. Both os-cillators feed into mixers. The circuit inthis design reduces the number of oscil-

lators to one and uses no mixers (Figure1). As a result, the output has fewer spu-rious harmonics and unharmonically re-lated frequency products, resulting in acleaner output overall.

The two lower transconductance am-plifiers, IC

4Aand IC

4B, form a standard,

double-integrator bandpass/lowpass fil-ter. The lower amplifiers are active forpositive control voltages, and the upperamplifiers, IC

3Aand IC

3B, are effectively

turned off for lack of bias current. Theupper amplifiers thus play no part in thecircuit when the control voltage is posi-

tive. The TL072 op amps, IC2A

and IC2B

,are merely buffers to enable an easierchoice of resistor values for IC

4B’s input

and to avoid excessive loading of the in-tegrator capacitors. The resistor values setthe Q (quality factor) to exceed unity.Positive feedback from the bandpass out-put to the noninverting input makes thefilter oscillate. Adjusting the R

3trimmer

allows you to adjust the output amplitudeand lets you set the drive to the diodes ata level that ensures oscillation but mini-mizes distortion. This fairly standardconfiguration yields quadrature outputs

VCO produces positive and negative output frequenciesHenry Walmsley, Farnborough, UK


ideasdesign

+

+

+

+

CV 3

2

1

7

515V

15V

15V47 pF

47 pF

15V

1N4148 1N4148

3.3k

6

IC1AOPA2277

IC1BOPA2277 IC2A

TL072IC2B

TL072

10k

10k

10k 22k

O

BO

5

8

15V

15V

1k

V+

V+

V

V

22k

100k

22k

100k

22k8.2 nF

OUTPUT90 0

OUTPUT0 90

ABCIN+DIINBI

13247

O

BO

6

11

6

11

6

11

5 3

2 4

8

4

878

15V

15V

15V

15V

15V

15V

1

ABCIN+DIINBI

13247

O

BO

6

1k 11

12 5

6

9

15V

15V

ABCIN+DIINBI

1614151310

O

BO

12

9

15V

15V

1k

ABCIN+DIINBI

1614151310

1k1k

1N4148

1N4148

1N4148

1N4148

1k1k 1k8.2 nF

1k

22k

GND GND

1k1k

BC559

BC559

10k

1k

10k 22k

R2100k

R3100k

NOTES:CONTROL-VOLTAGE INPUT: 10V TO +10VFOR APPROXIMATELY 10 TO +10-kHz OUTPUT,DEPENDING ON CAPACITOR VALUES C1 AND C2.SET CV INPUT TO 1V AND ADJUST R3 FOR2VPP OUTPUT.SET CV INPUT TO 1V AND ADJUST R2 FOR2VPP OUTPUT.ADJUST R1 SO THAT THE OUTPUT FREQUENCY IS THE SAME FOR EQUAL-MAGNITUDE POSITIVE ANDNEGATIVE CONTROL VOLTAGES.

R15k

10k

IC4BLM13700

IC4ALM13700

IC3ALM13700

IC3BLM13700

8

4

1

8

4

V+

V

V+

V

C2C1

F igure 1

This quadrature-output VCO produces both positive and negative output frequencies.

from the two buffers with the highest dis-tortion product approximately 40 dBdown from the fundamental.

For negative control voltages, the up-per transconductance amplifiers, IC

3A

and IC3B

, receive bias current, and thelower amplifiers shut off. The upperamplifiers work in exactly the same wayas the lower ones, but they cross-con-nect to the inputs and integrator ca-pacitors. In this way, the in-phase andquadrature outputs are reversed fornegative control voltages, thus creatinga smooth transition to what you canconsider a “negative frequency.” In op-eration, when viewing the outputs onan X-Y trace, the circular rotation of the

dot becomes slower as you adjust thecontrol voltage near zero and then per-fectly reverses direction as the controlvoltage goes negative. This transitionoccurs without any unwanted crossingof the circle or drifting off beyond thecircle.

The two current sources, IC1A

and IC1B

,are fairly self-explanatory; the uppersource operates for negative control volt-ages and vice versa. The R

1gain trimmer

on the upper source allows you to adjustthe oscillator such that a given negativecontrol voltage yields the same frequen-cy as does the equal-magnitude positivecontrol voltage. This trim compensatesfor differences in transconductance of

the two separate dual-amplifier packages.The diodes across the current-source opamps avoid heavy saturation when therespective source turns off. You trim theR

2potentiometer to obtain equal ampli-

tudes from the upper and the lower sec-tions. The circuit in Figure 1 uses stan-dard, inexpensive, multiple-sourcedcomponents. It requires only minimal(and easy) trimming, with no interactingtrims. A 0V control input results in aguaranteed 0-Hz output, dependent onlyon well-controlled op-amp offsets. Withthe Bode/Moog system, you must makea front-panel adjustment to zero-beattwo oscillators running at 20 kHz.


ideasdesign

It may be easy to find a precision volt-age reference for your application;however, a programmable precision

reference is another matter. The circuit inFigure 1 yields a precision reference withan LSB of 62.5 V. The circuit is a 16-bitDAC using three 8-bit digital poten-tiometers and three CMOS op amps.Each digital potentiometer operates as an8-bit multiplying DAC. On the left side ofFigure 1, two digital potentiometers, IC

3A

and IC3B

, span across VREF

to ground, andthe wiper outputs are connected to thenoninverting inputs of two amplifiers,IC

4Aand IC

4B. In this configuration, the

inputs to the amplifiers have high im-pedance levels, thus isolatingthe digital potentiometers fromthe rest of the circuit. The microcon-troller, IC

1, programs digital poten-

tiometers IC3A

and IC3B

through its SPIport. If V

REFis equal to 4.096V, the LSB

at the outputs of IC4A

and IC4B

is 16 mV.To make this circuit perform as a 16-

bit DAC, a third digital potentiometer,IC

2A, spans across the outputs of the two

amplifiers, IC4A

and IC4B

. The pro-grammed setting of IC

3Aand IC

3Bsets

the voltage across this third digital po-

tentiometer. If VREF

is 4.096V, you canprogram IC

3Aand IC

3Bsuch that the out-

put difference of op amps IC4A

and IC4B

is 16 mV. You can achieve high accuracywith this circuit by using a dual digitalpotentiometer for IC

3Aand IC

3B. With

the dual structure, the resistances ofthese two devices match typically with-

in 0.2%. Given the size of the voltageacross the third digital potentiometer,the LSB of the complete circuit from leftto right is 62.5 V (V

REF/216). Table 1

shows the critical device specificationsto obtain optimum performance withthis circuit.

IC4A

_

+

IC5A

_

+

RA IC3A

IC2A

VREF=4.096V

RB

IC4B

_

+RA IC3B

IC1

SPI

VREF

RB

RA

V1

V2

V3

IC1=PIC16F876.

IC3=IC2=MCP42010.DUAL DIGITAL 10-k POTENTIOMETERS.

IC4=IC5=MCP6022.DUAL 10-MHz, SINGLE-SUPPLY OP AMPS.

VREF=MCP1541, 4.096V PRECISIONVOLTAGE REFERENCE.

V4

RB

STAGE ONE

STAGE TWO

3SPI

3

V3=V4= [(V1)(R2B)+(V2)(R2A)]

(R2A+R2B) .

V1 AND V2= VREF (RXB)

(RXA+RXB)

NOTES:

F igure 1

16-bit adjustable reference uses 8-bit digital potentiometersBonnie Baker, Tucson, AZ

You can design a precision 16-bit DAC by using three digital potentiometers and three op amps.

TABLE 1—DEVICE SPECIFICATIONS FOR OPTIMUM PERFORMANCEDevice Specification PurposeDigital potentiometers Number of bits 8 bits Determines the overall LSB and resolution of the circuit.(IC2, IC3) (MCP42010) Nominal resistance 10 k (typical) Achieve better noise performance by using lower resistance

(potentiometer element) potentiometers. The trade-off for low-noise potentiometers is higher current consumption.

Differential nonlinearity 1 LSB (maximum) Good differential linearity ensures that the circuit exhibits no missing codes.

Voltage-noise density 9 nV/Hz at 1 kHz (typical) If the noise contribution of these devices is too high, it reduces(for half the resistive element) the possibility of achieving 16-bit, noise-free performance.

Selecting lower resistance elements can reduce the potentiometer noise.

Operational amplifiers Input bias current (IB) 1 pA at 25C (maximum) Higher input bias current causes a dc error across the (IC4, IC5) (MCP6022) potentiometer. CMOS amplifiers are, therefore, good choices.

Input offset voltage 500 V (maximum) A difference in amplifier offset error between IC4A and IC4B

could compromise the differential linearity to the overall system; 50 V is considerably lower than 1 LSB in Stage 1 of the circuit.

Voltage-noise density 8.7 nV/Hz at 10 kHz (typical) If the noise contribution of these devices is too high, it reduces the possibility of achieving 16-bit, noise-free performance. Selecting lower noise amplifiers can reduce overall system noise.

EDN Design Ideas 2003

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