The CMOS RC delay model -...

The CMOS RC delay model

The CMOS Inverter‐ Dynamic PropertiesLecture 3b

2014

Definitions of rise and fall delays

September, 2014 Integrated Circuit Design 2

• fall delay tpdf• rise delay tpdr

Definitions of rise and fall delays


• fall time tf• rise time tr

Step‐respons model


VDD

VSS

CL

VIN VOUT

Square wave approximation

ON

OFF

OFF

ON

Step‐respons rise‐delay model


VOUT

VDDIDSAT,P

Equivalent circuit

Load capacitance is charged through

p‐MOSFET

1. VIN=LOW

VDDVDD/2

IDS,P

VOUT

IDSAT,P

pMOS current flow


CL

, ,

L OUTpdr

DSAT P DSAT P

C VQtI I

VOUT=VDD/2

Step‐respons fall‐delay model


VOUT

CL

VSS

IDSAT,N

Equivalent circuit

Load capacitance is discharged through

n‐MOSFET

2. VIN=HIGH

VDDVDD/2

IDS,N

VOUT

nMOS current flow

IDSAT,N


, ,

L OUTpdr

DSAT N DSAT N

C VQtI I

VOUT=VDD/2

Electrical inverter model


VDD

VSS

VIN VOUT

Replace MOSFETs with constant‐current sources IDSAT,N and IDSAT,P, respectively!

IDSAT,N

IDSAT,P

CDN

CDP

Add the drain capacitancesCGP

CGN

Add the gate capacitances

Electrical inverter model


VDD

VSS

VIN VOUT

IDSAT,N

IDSAT,P

CG=CGP+CGN CD=CDP+CDN

Simplify!

Ramp respons


VIN

It is obvious that a ramp approximation would give a better model –However, this is too complicated for simple analytical analysis

Spice simulations show – that for about equal input and output edge rates –The ramp respons delay is about 40% longer than the step respons delay!

Ramp‐respons delay


1 0.7 0.72

L DD L DDpd pd pd L

DSAT DSAT

C V C Vt t t RCI I

Spice simulations show – that for about equal input and output edge rates –The ramp respons delay is about 40% longer than the step respons delay!

DD

DSAT

VRI

Effective resistances of 60 nm MOSFETs

RN,eff=VDD/IDSAT,max

RP,eff=VDD/IDSAT,max

September, 2014 11Integrated Circuit Design

RN,eff=2 km RP,eff=4 km

IDSAT,max =

600 uA/um

VDD=1.2 V

N‐channel device P‐channel device

IDSAT,max =

300 uA/um

VDD=1.2 V

IDS

VDS

IDS

VDSVDD VDD

Replace current sources by resistors


VIN VOUT

VDD

VSS

Reff,N

Reff,P

CG CD

Output waveform – ramp input


Discharge trace – ramp input


Widen PMOS device to make RP,eff=RN,eff


VIN VOUT

VSS

Reff

CG CD

VIN VOUT

VSS

W=1

W=2

VDD

Inverter electrical twoport model

Reff=2 km, CG=CD=3.6 fF/m

Applying electrical two‐port model


VIN

FO1‐delay

Reff

VDDCD CG

Driver inverter Loading inverter

Electrical driver model Electrical load model

VOUT

FO1 delay=0.7Reff(CD+CG)

X1 X1R´ CG

Introduce R´=0.7ReffFO1 delay=R´(CD+CG)

• Geometry dependence of R and C:

• X1 and X4 inverters have the same RC product!• But 65 nm inverters have different RC product from 45 nm and 130 nm!


The RC product is width independent!

2´~~

~pd

G

LRt LW

C WL

´ ´D Ld G G

G G

C Ct R C R C p hC C

parasitic delay p=CD/CG

electrical effort h= CL/CG =4

FO1 delay


VIN

FO1‐delay

Driver inverter Loading inverter

VOUTX1 X1

R´ CL

65 nm: FO1 delay=10 ps!

´ 1d Gt R C p

5 ps ~2

CG


FO1 delay

FO4 delay


VIN

FO4‐delay

Driver inverter

Loading inverter

X1R´

´ 4d Gt R C p

X44CG

VOUT


5 ps ~5 electrical effort h= CL/CG =4

CG

FO4 delay

FO4 delay


VIN

FO4‐delay

Driver inverter

X1R´

VOUT


X1

X1

X1

X1Loading inverters


CG

CG

CG

CG

CG FO4 delay

Conclusion


• In this lecture we gave a background discussion to the RC delaymodel

• The RC‐delay model is based on an equivalent RC circuit• The two‐port model includes models for load and driver• We separated technology dependent time constant R´CG from

technology independent relative delay, d=p+h– Introduced parasitic delay p, and electrical effort h

• FO4 delay– Relative: p+4~5– Absolute RC*(p+4)~5RC

The CMOS RC delay model -...

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