Silicon as Wafer

8/12/2019 Silicon as Wafer

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Chapter 4

Wafer Manufacturing

and Epitaxy Growing

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Objectives Give two reasons why silicon dominate Wafer orientations

Basic steps from sand to wafer Describe the CZ and FZ methods Explain the purpose of epitaxial silicon Describe the epi-silicon deposition process.


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Crystal Structures Amorphous

No repeated structure at all Polycrystalline

Some repeated structures

Single crystal One repeated structure

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Amorphous Structure Polycrystalline Structure

Single Crystal Structure


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Why Silicon? Abundant, cheap Silicon dioxide is very stable, strong

dielectric, and it is easy to grow in thermal process.

Large band gap, wide operation temperaturerange.

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Name SiliconSymbal Si

Atomic number 14Atomic weight 28.0855

Discoverer Jns Jacob BerzeliusDiscovered at Sweden

Discovery date 1824Origin of name From the Latin word "silicis" meaning "flint"

Bond length in single crystal Si 2.352 Density of solid 2.33 g/cm3

Molar volume 12.06 cm3

Velocity of sound 2200 m/secElectrical resistivity 100,000 cm

Reflectivity 28%

Melting point 1414 C

Boiling point 2900 C

Source: http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html


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Unit Cell of Single Crystal Silicon

Si

Si

Si

Si

Si

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Unit Cells in Material


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Miller Indices

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Crystal Orientations:

x

y

z

(100) plane


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x

y

z

(100) plane (111) plane

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x

y

z

(110) plane


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Orientation PlaneAtomBasic lattice cell

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Orientation PlaneSilicon atomBasic lattice cell


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Wafer Etch Pits

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Wafer Etch Pits


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Illustration of the DefectsSilicon AtomImpurity on substitutional site

Frenkel DefectVacancy or Schottky Defect

Impurity inInterstitial Site

SiliconInterstitial

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Dislocation Defects


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Stress and Defects

Defects can be usually generatedduring high temperature steps in wafer formation or thermal process due tointrinsic stress.

Thermal gradient can be another factor

to cause stress, e.g. from oxidation,diffusion, RTA, RTO etc.

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From Sand to Wafer Quartz sand: silicon dioxide Sand to metallic grade silicon (MGS)

React MGS powder with HCl to form TCS Purify TCS by vaporization and condensation React TCS to H2 to form polysilicon (EGS) Melt EGS and pull single crystal ingot


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From Sand to Wafer (cont.) Cut end, polish side, and make notch or flat Saw ingot into wafers Edge rounding, lap, wet etch, and CMP Laser scribe

If an epitaxial layer is needed , Epitaxy deposition

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From Sand to SiliconHeat (2000

C)

SiO2 + C Si + CO2Sand Carbon MGS Carbon Dioxide

Heat (1100

C)

SiHCl 3 + H2 Si + 3HCl

TCS Hydrogen EGS Hydrochloride

Heat (300

C)Si + HCl TCS + H2


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Crystal Pulling: CZ method

Graphite Crucible

Single Crystalsilicon Ingot

Single Crystal Silicon Seed

Quartz Crucible

Heating Coils1415 CMolten Silicon

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CZ Crystal Pullers


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CZ Crystal Pulling

Source: http://www.fullman.com/semiconductors/_crystalgrowing.html

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Floating Zone Method


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Comparison of the Two Methods CZ method is more popular

Cheaper Larger wafer size (300 mm in production) Reusable materials

Floating Zone Pure silicon crystal (no crucible) More expensive, smaller wafer size (150 mm) Mainly for power devices.

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Ingot Polishing, Flat, or Notch

Flat, 150 mm and smaller Notch, 200 mm and larger


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Wafer Sawing

Orientation Notch

Crystal Ingot

Saw Blade

Diamond Coating

Coolant

IngotMovement


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Parameters of Silicon Wafer

Wafer Size (mm) Thickness m) Area (cm2) Weight (grams)279 20.26 1.32381 45.61 4.05

100 525 78.65 9.67125 625 112.72 17.87150 675 176.72 27.82200 725 314.16 52,98300 775 706.21 127.62

50.8 (2 in)76.2 (3in)

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Wafer Edge Rounding

Wafer Wafer movement

Wafer Before Edge Rounding

Wafer After Edge Rounding


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Wafer Lapping Rough polished conventional, abrasive, slurry-lapping To remove majority of surface damage To create a flat surface

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Wet Etch Remove defects from wafer surface 4:1:3 mixture of HNO3 (79 wt% in H2O),

HF (49 wt% in H2O), and pure CH

3COOH.

Chemical reaction:

3 Si + 4 HNO3 + 6 HF 3 H2SiF6 + 4 NO + 8 H2O


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Chemical Mechanical Polishing

Slurry

Polishing Pad

Pressure

Wafer Holder Wafer

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Wafer Polishing Operation


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200 mm Wafer Thickness andSurface Roughness Changes

76 m

914 mAfter Wafer Sawing

After Edge Rounding76 m914 m

12.5 m814 m


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Epitaxy: Definition Greek origin epi: upon taxy: orderly, arranged

Epitaxial layer is a single crystal layer on asingle crystal substrate.

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Epitaxy: Purpose Barrier layer for bipolar transistor

Reduce collector resistance while keep high breakdown voltage.

Only available with epitaxy layer. Improve device performance for CMOS and

DRAM because much lower oxygen,carbon concentration than the wafer crystal.


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Epitaxy Application, Bipolar Transistor

n-Epi p n+

n+

P-substrate

Electron flow

n +

Buried Layer

p+ p+SiO2

Al Cu SiBase Collector Emitter

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Epitaxy Application: CMOS

P-Wafer

N-WellP-WellSTI n+n+ USG p+ p+

Metal 1, Al Cu

BPSG

W

P-type Epitaxy Silicon


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Silicon Source GasesSilane SiH4Dichlorosilane (DCS) SiH2Cl2Trichlorosilane (TCS) SiHCl3Tetrachlorosilane SiCl4Diborane B

2H

6Phosphine PH3Arsine AsH3

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DCS Epitaxy Grow, Arsenic Doping

Heat (1100

C)

SiH2Cl2 Si + 2HClDCS Epi Hydrochloride

AsH3 As + 3/2 H2Heat (1100

C)


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Schematic of DCS Epi Grow andArsenic Doping Process

SiH2Cl2

Si

AsH3

As

AsH3

H

HCl H2

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Epitaxial Silicon Growth Rate Trends

G r o w t h R a t e

, m i c r o n / m i n

1000/T(K)

Temperature (

C)

0.7 0.8 0.9 1.0 1.1

0.01

0.02

0.05

0.1

0.2

0.5

1.01300 1200 1100 1000 900 800 700

SiH4

SiH2Cl2

SiHCl3

Surface reaction limited

Mass transportlimited


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Barrel Reactor RadiationHeatingCoils Wafers

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Vertical Reactor

HeatingCoils

Wafers

Reactants

Reactants and byproducts


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Horizontal Reactor

Heating Coils

WafersReactants

Reactants and byproducts

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Epitaxy Process, Batch System Hydrogen purge, temperature ramp up HCl clean

Epitaxial layer grow Hydrogen purge, temperature cool down Nitrogen purge Open Chamber, wafer unloading, reloading


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Single Wafer Reactor

Sealed chamber, hydrogen ambient Capable for multiple chambers on a mainframe Large wafer size (to 300 mm)

Better uniformity control

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Single Wafer Reactor Heating LampsHeat

Radiation

Wafer

QuartzWindow

Reactants

Reactants & byproducts

QuartzLiftFingers

Susceptor


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Epitaxy Process, Single Wafer System

Hydrogen purge, clean, temperature ramp up Epitaxial layer grow Hydrogen purge, heating power off Wafer unloading, reloading

In-situ HCl clean,

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Why Hydrogen Purge Most systems use nitrogen as purge gas Nitrogen is a very stable abundant

At > 1000 C, N2 can react with silicon SiN on wafer surface affects epi deposition H2 is used for epitaxy chamber purge Clean wafer surface by hydrides formation


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Defects in Epitaxy Layer

Dislocation

Stacking Fault fromSurface Nucleation

Impurity ParticleHillock

Stacking Fault formSubstrate Stacking Fault

After S.M. Zse s VLSI Technology

Substrate

Epi Layer

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Future Trends Larger wafer size Single wafer epitaxial grow

Low temperature epitaxy Ultra high vacuum (UHV, to 10-9 Torr) Selective epitaxy


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Summary Silicon is abundant, cheap and has strong,

stable and easy grown oxide. Miller indices and wafer orientation CZ and floating zone (FZ), CZ is more

popular Sawing, edging, lapping, etching and CMP

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Summary Epitaxy: single crystal on single crystal Needed for bipolar and high performance

CMOS, DRAM. Silane, DCS, TCS as silicon precursors B2H6 as P-type dopant PH3 and AsH3 as N-type dopants Batch and single wafer systems


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Future Trend Silicon on insulator (SOI) is emerging ! SOI technology for next generation IC Compound semiconductor is rising ! SiC , GaN for fast speed and high power

devices

Silicon as Wafer

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