Sandbridge’s Software Defined Radio (SDR)...

Sandbridge’s Software Defined Radio (SDR) Solution

1 North Lexington Ave, 10th FloorWhite Plains, New York 10601

914-287-8500

John Glossner, Ph.D., Co-Founder, CTO & EVP

Tanuj Raja, V.P. Business [email protected]

[email protected]

http://www.SandbridgeTech.com

Agenda

Motivation for SDR

Multithreaded SDR Processor

Software Development ToolsCompilerSimulatorIDE

Communications System Implementation2Mbps WCDMA


3 15 3570

140

0

100

200

300

400

500

600

700

M U

nits

2001 2002 2003 2004 2005

camera enabled handsets

total handset market

What is it that we eventually carry with us ?

It has a color screen, camera, audio and antenna …… but all features need high computing performance

and ultra low power consumption Wireless communication 2G – 2.5G – 3G – WLAN – BT – etc.

GSM/IS-95a,b/IS-136/PDC/ iDEN – CDMA2k/GPRS/EDGE – FDD/TDD/TD-SCDMA/Jap.WCDMA/CDMA2k-3x– 802.11a,b,g

Radio broadcast GPS – radio – TV – etc.Location based services/911/tracking services – AM/FM/DAB – Sat./Terr.TV

Encryption – decryption – media encode – media decodeGames – speech to text – natural language processing

sources: In-Stat/MDR, TSR, Dresdner, Dataquest


The Challenges of an Industry

Cost3G is >10x more complex than 2G

but cost should be same, or even less

Convergence phone 2x complexityWLAN, 2G, and 2.5G integration Traditionally implemented in HW

Moore’s law reduces cost 50% every 18 months6 years until the wireless multimedia is a real consumer market

Time-to-marketGPRS terminals were late

OEMs had to wait until bug free SoCs were available

3G terminals will be lateOEMs have to wait until bug free SoCs with ‘reasonable’ power consumption are available


A Whole Industry’s approach failed …

DSP

Fixed

ARM

WLAN802.11

GSM

Bluetooth

GPRS

CDMA2k

CDMAone

JavaWCDMA

FDD

IS-136

MPEG-4

MP3

EDGE

PDC

USB

DSP

ARM

VGA

… on advanced wireless systems …

… with multimedia

WCDMATD-SCDMA

WCDMATDD

GPS


Agenda

Motivation for SDR



Communications System Implementation2Mbps WCDMA802.11b


SandblasterTM Architecture Performs

CompilableDSP

Java ProcessorControl

Processor

SystemProductivityAdvantage

9-12+ months

3G Applications Standard 3G, xDSL, 802.11Control Stacks

C programmedLatency hiding architecture


Multithreaded Baseband Processor

High ParallelismVector / SIMD data parallelismMultiple instruction issueThread-level parallelism

I –C

ach

e64

KB

64B

Lin

es4W

(2-

activ

e)

I- DecodeI- Decode

JumpQ PCCR

JTR

LCR

Data Buffer

MPY

VRABC

VPR0

MPY

VRABC

VPR1

PABC

MPY

VPR2

MPY

VPR3

SAT

VRABC VRABC

PABCPABCPABC

ACC ACC ACC ACCADD ADD ADD ADD

AGEN

(16) 32-bit GPR

LS IQ

LRA LRB

Address

DirLRU Replace

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks

INT IQ

IRA IRB

ALU

WB

Bus/MemoryInterface

Interrupt SIMDIQI –

Cac

he

64K

B64

B L

ines

4W (

2-ac

tive)

I –C

ach

e64

KB

64B

Lin

es4W

(2-

activ

e)

I- DecodeI- Decode

JumpQ PCPCCRCR

JTRJTR

LCRLCR

Data Buffer

MPY

VRABC

VPR0

MPY

VRABC

VPR1

PABC

MPY

VPR2

MPY

VPR3

SAT

VRABC VRABC

PABCPABCPABC


AGEN

(16) 32-bit GPR

LS IQ

LRA LRB

Address

DirLRU Replace

DirLRU Replace

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks

INT IQ

IRA IRB

ALU

IRA IRB

ALU

WB

Bus/MemoryInterface

Interrupt SIMDIQ


Thread 0# Monitoring FCCH&SCHlu r1,M(r2) lu r1,M(r2) add r2,r3,r4cmp cf2,r5,r3jc cf2,(Synch_off)

Thread 7# Monitoring CPICHlu r1,M(r2)lu r1,M(r2) call (De_scrambler)

stu r3,M(r2)

Thread 6# Handover Code

ctsr r1,sr2 lu r1,M(r2).jc cf0,(UMTS_Mode)

Thread 5# FIR Filter

lvu vr1,M(r4)vmacs

vr3,vr1,vr2,wr0loop lcr0,label(4x)

Thread 4# Pulse shaping Code

lvuvr1,M(r4)vmacs vr3,vr1,vr2,wr0loop lcr0,label(4x)

Thread 3# WCDMA Handover Code

ctsr r1,sr2 lu r1,M(r2).jc cf0,(WCDMA_Mode)

Thread 2# Exit Code ..

Start Thread33..

Start Thread24)

Thread 1# WCDMA MainStart Thread0Start Thread1Start Thread2

Start Thread13Start Thread14loop lc1,0xf0

)

Multithreaded Architecture

I –C

ach

e64

KB

64B

Lin

es4W

(2-a

ctiv

e)

I- DecodeI- Decode

JumpQ PCCRJTRLCR

Data Buffer

MPY

VRABC

VPR0

MPY

VRABC

VPR1

PABC

MPY

VPR2

MPY

VPR3

SAT

VRABCVRABC

PABCPABCPABC


AGEN

(16) 32-bit GPR

LS IQ

LRA LRB

Address

DirLRU Replace

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks / 2Active

INT IQ

IRA IRB

ALU

WB

Bus/MemoryInterface

Interrupt SIMDIQ

Sea of Threads

Code&Data Sharing Across Threads

FastCross Thread

Interrupts

Key to Low Power Implementation

Hardware Scheduled

FullyInterlocked

HighlyParallel

CProgrammed


Low power design with No Compromise

CPU optimized for power/performance

Memory optimized for power/performance

180nm130nm

90nm

90nm 130nm 180nm

Multithreading decouples CPU from Memory speed

Optimized CPU Power

Optimized Memory Power

2ns 6ns3.5ns

CP

U p

ow

er c

on

sum

pti

on

300MHz 1GHz600MHz

Mem

ory

po

wer

co

nsu

mp

tio

n


Competitive Power - Cores

DSP performance vs. Power(Log Log scale)

1

10

100

1000

10000

100000

1 10 100 1000mWatts

MM

AC

/s

Sandblaster

C55x SC110

SC140

SC110

C54x

C55x

C64xSC140

MSA

1M/mW

5M/mW

5M/mW

10M/mW

10M/mW

1M/mW

50M/mW

50M/mW


… very well received by Industry

MPF Day Two: "Extreme" Processors

Intel's HyperThreading technology looks like child's play compared to SandBridge's new 8-way multithreading capable DSP (digital signal processor) targeted at 3G wireless devices. Replicating and sharing a number of processor resources (that takes about 15% more die area than a hypothetical single-threaded version), up to 8 threads can execute simultaneously in this chip. Apparently, the algorithms and processing steps required for 3G communications can be efficiently allocated across multiple threads and executed simultaneously. The SandBlaster is capable of processing 10 billion multiply/accumulate operations per second, and consumes less than 500 milliwatts on average. Special logic ensures no single thread can dominate the instruction cache, as each thread is only capable of evicting its own specific subset of cache lines. Note that threads can read instruction cache lines from other threads, so that cache is considered to be shared among threads. For power savings, if a thread is not used, itis turned off, and any functional units not presently used can be temporarily powered down.

CompilableDSP

Java ProcessorControl

Processor

SystemProductivityAdvantage

9-12+ months

3G Applications Standard 3G, xDSL, 802.11Control Stacks

C programmedLatency hiding architecture




stu r3,M(r2)


stu r3,M(r2)






lvu vr1,M(r4)vmacs



lvu vr1,M(r4)vmacs










Thread 2# Exit Code ..Start Thread33..Start Thread24

)

Thread 2# Exit Code ..Start Thread33..Start Thread24

)



)



)

I –C

ache

64K

B64

B L

ines

4W (

2-ac

tive)

I- DecodeI- Decode

JumpQ PCCRJTRLCR

Data Buffer

MPY

VRABC

VPR0

MPY

VRABC

VPR1

PABC

MPY

VPR2

MPY

VPR3

SAT

VRABCVRABC

PABCPABCPABC


AGEN

(16) 32-bit GPR

LS IQ

LRA LRB

Address

DirLRU Replace

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks / 2Active

INT IQ

IRA IRB

ALU

WB

Bus/MemoryInterface

Interrupt SIMDIQ

I –C

ache

64K

B64

B L

ines

4W (

2-ac

tive)

I –C

ache

64K

B64

B L

ines

4W (

2-ac

tive)

I- DecodeI- Decode

JumpQ PCPCCRCRJTRJTRLCRLCR

Data Buffer

MPY

VRABC

VPR0

MPY

VRABC

VPR1

PABC

MPY

VPR2

MPY

VPR3

SAT

VRABCVRABC

PABCPABCPABC


AGEN

(16) 32-bit GPR

LS IQ

LRA LRB

Address

DirLRU Replace

DirLRU Replace

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks / 2Active

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

Data Memory64KB

8-Banks / 2Active

INT IQ

IRA IRB

ALU

IRA IRB

ALU

WB

Bus/MemoryInterface

Interrupt SIMDIQ

Sea of Threads

Code&Data Sharing Across Threads

FastCross Thread

Interrupts

Key to Low Power Implementation

Hardware Scheduled

FullyInterlocked

HighlyParallel

CProgrammed


Performance

Peak3 compound operations/cycle>20 RISC-ops/cycle4 MACS/cycle (MAC-SAT-ADD-SAT)

ExampleL0: lvu %vr0,%r3,8|| vmulreds %ac0,%vr0,%vr0,%ac0|| loop %lc0,L0>20 operations packed into a 64-bit compound ISAVLIW machines may require 512+ bits

20 tap FIR3.63 taps/cycle sustained


Agenda

Motivation for SDR





Compiler Productivity

6-9 Months!6-9 Months!

DesignAlgorithms

Map toFixed Point C

Write DSPSpecific C

Write DSPAssembly

Hand ScheduleOperations on DSP

Final Product

10x every 10 years

Signal Processing Applications Complexity

1E+3

10E+3

100E+3

1985 1995 2005

Lin

es o

f C

Co

de


Compiler saves R&D and time-to-market …

SandblasterTM Provides Dramatic Improvement

6-9 Months!

SANDBRIDGE

6-9 Months!

Compile

Final Product

DesignAlgorithms

Map toFixed Point C

Write DSPSpecific C

Write DSPAssembly

Hand ScheduleOperations on DSP

Final Product

1E+3

10E+3

100E+3

1985 1995 2005

Lin

es o

f C

Co

de

10x every 10 years

Signal Processing Applications Complexity


Compiler

Programmed in C or JavaSuper-computer class compiler

VectorizationDSP instruction generation

Standard LibraryPrintf();

POSIX pthreads or Java threads50k+ testcases used for validation

Industry standards: Plum-Hall, perennial, nullstone

AMR Encoder(out-of-the-box C code)

0

100

200

300

400

500

600

700

SB TI C64x TI C62x SC140 ADI BlackFin

DSP's

Mh

z

10 MHz


Simulation Software

Compiled Simulator JIT “Flash” compilation Up to 100 MHz on high end x86Multi-threaded supported

Up to 4 orders of magnitude fasterDramatic development time reductionSignificant productivity improvement

Simulation Speed(1GHz Laptop)

0.114 0.106

0.002

0.013

24.639

0.001

0.010

0.100

1.000

10.000

100.000

Millio

ns

of I

nst

ruct

ions

Per

Sec

ond

SB 24.639

TI C64x (Code Composer) 0.114

TI C62x(Code Composer) 0.106

SC140(Metrow erks) 0.002

ADI Blackfin (Visual DSP) 0.013


Context sensitive IDE

IDE based on open source netbeansCommon Java/C programming environmentIntegrated debuggingTransparent HW / Simulation environmentWorks in multiple languages


Agenda

Motivation for SDR





IF

RF

MMI

APPLICATIONTASKS

PROTOCOLSTACK

DATA I/O

LCD, KPD …

L1 CONTROL

L1 BASEBAND SW

Integration


Application Development Methodology

MATLAB physical layerEnd-to-end UTRAN + UEChannel modelsConfigurable via test-scriptsBER/FER measurement

Simulation level CFixed pointUE onlyFixed configurationPerformance measurement

Product level CPartitioned for real-timeUsing actual peripheralsIntegrate with L1 control + L2/L3

Physical layer testingUTRAN model validated against test equipmentmodels & test cases from 34.121, 25.101, 30.03, ITU


Real-time Baseband Performance

Real-time chip, bit, and symbol rate processing1 SB9600 chip for 2Mbps Rx concurrently with 768kbps Tx<75% utilization for 384kbps Rx / 384kbps Tx

Includes functions traditionally implemented in H/WTurbo DecoderRake ReceiverTx/Rx Filters

Concurrent performance on 802.11B and GPRS

FILTER

RAKE Searcher

PN BT#1 PN BT#2 PN BT#3

De-Scrambler

Path Table Building

Timing Management

De-SpreadDe-SpreadDe-SpreadChannelEst/Derot

Path 2Path 3

Path 4

Path 1DSCH

Path 1S-CCPCH

De-ScrambleDe-ScrambleDe-Scramble

DPCH

De-SpreadDe-SpreadDe-SpreadDe-Spread

Path 2Path 3

Path 4

MRCMeasurements:

SIR

RSCP

ISCP

Ec/Io

Multi Channel Code De-Mux2nd Deinterleaver

1nd Deinterleaver Channel DecodingFurther Processing

FILTER

RAKE Searcher

PN BT#1 PN BT#2 PN BT#3

De-Scrambler

Path Table Building

Timing Management


Path 2Path 3

Path 4


Path 2Path 3

Path 4

Path 1DSCH

Path 1S-CCPCH


DPCHS-CCPCH


DPCH


Path 2Path 3

Path 4


Path 2Path 3

Path 4

MRCMeasurements:

SIR

RSCP

ISCP

Ec/Io

Multi Channel Code De-Mux2nd Deinterleaver

1nd Deinterleaver Channel DecodingFurther Processing

Physical channel Segmentation

Radio frame segmentation

2nd interleaving

Physical channel mapping

Channel coding

Rate matching

TrBk concatenation /Code block segmentation

CRC attachment

Radio frameequalization

1 st interleaving

TrCH Multiplexing

Spreading/Scrambling

Filter

Rate matching

Physical channel Segmentation

Radio frame segmentation

2nd interleaving

Physical channel mapping

Channel coding

Rate matching

TrBk concatenation /Code block segmentation

CRC attachment

Radio frameequalization

1 st interleaving

TrCH Multiplexing

Spreading/Scrambling

Filter

Rate matching

0

10

20

30

40

50

60

70

80

90

100

802.11b GPRS WCDMA1/2/5.5/11Mbps Class 10/12 64/384/2k Kbps

% S

B96

00 U

tiliz

atio

n


SBTC 8/02

DSP

Ins & Data Memory(64KB / 64KB)

EX

T IN

T

RCVRI/O

I2C

TDMInfc (2)

RF DeviceControl

TDM

A/D Data

SPI

XMTRI/O

RF DeviceControl

D/A Data

To/FromExternalMemory

Memory Bus

GPIOStatic Cntl SystemClk/Cntl

0.18um CMOS ASIC

Single DSP Core

SW Programmable

External Bus for L2 memory

Internal Inst/Data memory

Control Interfaces: I2C, SPI, TDM, A/D, D/A


J1

J5

J2 J6

SIP8_1

1

J3

J4

SW1

SW2

OFF

SW3

LE

Ds 18

Populated Multimode Baseband Card


EXT INT

AHB INT ARM

RCVR

SPI &Stat Cntl

I2C &Stat Cntl

TDMInfc (2)

XMTR

TDMInfc (2)

AHB-I/O

Internal AHB

TDMInfc (2)

TDMInfc (2)

External AHB

RF DeviceControl

RF DeviceControl

TDM

TDM

TDM

TDM

RX Data

TX Data

JTAG

DSP

Ins & Data Mem(64KB / 64KB)

L2 M

em(256K

B)

EX

T IN

T

DSP


L2 M

em(256K

B)

EX

T IN

T

DSP


L2

Mem

(256

KB

)

EX

T IN

T

DSP


L2

Mem

(256

KB

)

EX

T IN

T

DMACntlr

BlueToothI/O

802.11

GPS

XMRI/O

Bridge

SPI

I2C

GPIO

USB UART

SIM/USIM

Keypad

LCD Int.

…

APB

SystemClk/Cntl

Ext.Interrupts

SB9600 2003 Handset Chip

0.13um CMOS, custom

Replicated SBTC core

Low Power design


Capabilities

Key Sandbridge ExpertiseSoftware Systems

CompilersCompiled Simulators

Computer ArchitectureDSP / Processor DesignJava Execution

Wireless CommunicationsTransmission Systems Algorithm Design3G

Low Power VLSI Design

Design Integration CapabilityRF IntegrationCard Design

End use integration


Summary

Multithreaded baseband processorHigh-performance and low-powerDSP, Java, and Control processing

Sophisticated compiler technologyAutomatically generates DSP operationsAutomatically multithreads applicationsHand coded performance

Reconfigurable Communications ProtocolsWCDMA, GSM, GPRS, etc.802.11b, Bluetooth, etc.

Multimedia capabilityMP3MPEG4

Sandbridge’s Software Defined Radio (SDR)...

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