Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz
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Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz Ekaterina Laskin, Sean T. Nicolson, Sorin P. Voinigescu University of Toronto, Canada Pascal Chevalier, Alain Chantre, Bernard Sautreuil, STMicroelectronics, France
description
Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz. Ekaterina Laskin, Sean T. Nicolson, Sorin P. Voinigescu University of Toronto, Canada Pascal Chevalier, Alain Chantre, Bernard Sautreuil, STMicroelectronics, France. Outline. Motivation - PowerPoint PPT Presentation
Transcript of Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz
Low-Power, Low-Phase Noise SiGe HBT Static Frequency
Divider Topologies up to 100 GHz
Ekaterina Laskin, Sean T. Nicolson, Sorin P. VoinigescuUniversity of Toronto, Canada
Pascal Chevalier, Alain Chantre, Bernard Sautreuil,STMicroelectronics, France
10 October 2006 Paper Number 12.3 2/23
Outline• Motivation• Static divider topology• Fabrication technologies• Test setup and results• Conclusion
10 October 2006 Paper Number 12.3 3/23
Motivation• Applications at 80 GHz:
– Phase-locked loop– Radio circuits
• Comparison of divider topologies• Technology benchmark
10 October 2006 Paper Number 12.3 4/23
Static Divider Topology
• On-chip transformer and matching• Toggle flip-flop, 50 Ω output buffer• 2 different latch designs implemented
10 October 2006 Paper Number 12.3 5/23
Integrated Transformer
• Stacked design, top 2 metals over substrate • 30µm square, 1µm spacing, 2µm metal width
primary
secondary
30µm
10 October 2006 Paper Number 12.3 6/23
Transformer Model
• Model extracted from geometry using ASITIC• π - network includes substrate model• k = 0.855 is achieved
primary
secondaryk
substrate model
10 October 2006 Paper Number 12.3 7/23
Input Network Simulation
• Divider input matched 40 – 100 GHz• Transformer operational up to 100 GHz
10 October 2006 Paper Number 12.3 8/23
Latch Design 1 – w/o input EF• ECL latch
• Inductive peaking
• No split load
• Self-biased
• Resistive input biasing
10 October 2006 Paper Number 12.3 9/23
Latch Design 2 – with input EF
• Double-EF input buffer
10 October 2006 Paper Number 12.3 10/23
0.1 1 100
50
100
150
200
250
300
JC (mA/m2)
fT
fMAX
Implementation• Both dividers fabricated in 2 SiGe processes:
BiCMOS9
0.1 1 100
50
100
150
200
250
300
JC (mA/m2)
fT
fMAX
BipX
10 October 2006 Paper Number 12.3 11/23
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
10 October 2006 Paper Number 12.3 12/23
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
10 October 2006 Paper Number 12.3 13/23
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
10 October 2006 Paper Number 12.3 14/23
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
10 October 2006 Paper Number 12.3 15/23
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
515μm × 473μm
3.3 V
145 mW
502μm × 360μm
3.3 V
122 mW
10 October 2006 Paper Number 12.3 16/23
Test Setup
0 - 50 GHz:
50 - 75 GHz:
75 - 100 GHz:
10 October 2006 Paper Number 12.3 17/23
Measurement Results• Divider self-oscillation frequency:
404550556065707580
220 240 260 280 300Process f MAX (GHz)
Div
ider
SO
F (G
Hz)
Divider with EFDivider w/out EF
BipX
BiCMOS9
BipX1BipX2
10 October 2006 Paper Number 12.3 18/23
Sensitivity Curves
-50
-40
-30
-20
-10
0
10
20
10 20 30 40 50 60 70 80 90 100Input Frequency [GHz]
Inpu
t Pow
er [d
Bm
]
BipX, w/o EFBipX, w/ EFBiCMOS9, w/o EFBiCMOS9, w/ EF
25 °C
10 October 2006 Paper Number 12.3 19/23
Sensitivity Curves
-50
-40
-30
-20
-10
0
10
20
10 20 30 40 50 60 70 80 90 100Input Frequency [GHz]
Inpu
t Pow
er [d
Bm
]
25 °C50 °C100 °C
10 October 2006 Paper Number 12.3 20/23
Divider Phase Noise
Input Output
• 100 GHz• -90.4 dBc/Hz @
100 kHz offset
• 50 GHz• -96.4 dBc/Hz @
100 kHz offset• Phase noise -6 dB with frequency halving
10 October 2006 Paper Number 12.3 21/23
-50
-40
-30
-20
-10
0
10
20
10 20 30 40 50 60 70 80 90 100Input Frequency [GHz]
Inpu
t Pow
er [d
Bm
]
BiCMOS9, HBT onlyBiCMOS9, MOS-HBTBipX, HBT only
Further Improvements
HBT only
MOS-HBT
10 October 2006 Paper Number 12.3 22/23
Comparison to Previous Work
[6]
[5]
[9]
[7]
[8][2]
This Work
This Work
30
40
50
60
70
80
90
100
100 200 300 400 500
Technology fT [GHz]
Div
ider
SO
F [G
Hz]
InPCMOSSiGe
10 October 2006 Paper Number 12.3 23/23
Conclusion• 2 SiGe static dividers designed and
analyzed in 2 technologies• Designed divider operates up to 100 GHz• Features an integrated transformer
operating at 100 GHz• Ideal phase noise behaviour• Low power
10 October 2006 Paper Number 12.3 24/23
Thank You
10 October 2006 Paper Number 12.3 25/23
Back-up Slides
10 October 2006 Paper Number 12.3 26/23
50-Ω Output Buffer
10 October 2006 Paper Number 12.3 27/23
0.1 1 100
50
100
150
200
250
300
IC (mA)
fMAX
fT
0.1 1 100
50
100
150
200
250
300
IC (mA)
fMAX
fT
BipX Process Splits
BipX2 BipX1
10 October 2006 Paper Number 12.3 28/23
Measurement Results• Divider self-oscillation frequency:
404550556065707580
170 190 210 230 250 270Process fT (GHz)
Div
ider
SO
F (G
Hz)
Divider with EFDivider w/out EF
BiCMOS9
BipX
BipX1BipX2
10 October 2006 Paper Number 12.3 29/23
Measurement Results
with input EF w/out input EF
BiCMOS9 avg= 45.9 GHzavg= 52.03 GHz
s.dev.= 1.54 GHz
BipX avg= 65.02 GHzavg= 72.43 GHz
s.dev.= 2.06 GHz
10 October 2006 Paper Number 12.3 30/23
Source Phase Noise @ 100GHz
10 October 2006 Paper Number 12.3 31/23
BiCMOS Divider
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