Comparison of Si CMOS, SiGe BiCMOS and InP HBT Technologies for High-

Speed and Millimeter-Wave ICsSorin Voinigescu1, Timothy Dickson1,

Rudy Beerkens2, Paul Westergaard1, and Imran Khalid2

1) University of Toronto2) STMicroelectronics, Ottawa, Canada

5th. SiRF Topical Meeting, Atlanta, Sept.10, 2004

Outline• Device Structures• Figures of merit for mm-wave ICs and

high-speed logic• Circuit examples• Conclusions

Device structures• SiGe HBT

• Si n-MOSFET

• InP (GaAs) HBT

• InP(GaAs)HEMT

What drives device performance?

• Material properties– electron mobility (InP > SiGe > Si)– hole mobility (SiGe > Si > InP)– saturation velocity (InP > Si/SiGe) – breakdown field (InP > Si)– thermal conductivity (Si > SiGe > InP)

• Lithography (Si > InP)• Yield & reliability (MOS > SiGe HBT >

InP HBT)

FoMs for mm-wave ICs DevicesDevices

– fT, f

MAX, F

MIN, R

n (analog: g

m, g

o, g

m/I

C(DS), g

m/g

o)

CircuitsCircuitsFoMLNA=

G×IIP3× fF−1×P

= OIP3× fF−1×P

FoMVCO= fo

f2

Pout

L〚 f〛×P

FoMPA=Pout×G×PAE× f2

InP vs.SiGe HBT: fT, f

MAX

InP HBT: 2 mA/µmV

BE= 0.75V

SiGe HBT: 1.2 mA/µmV

BE= 0.9V

1

2 f T

=ECIC=BCkTq IC

C jeCcbReRcCcb

f MAX≈ f T

8R ' b C ' cb

Si vs. III-V FETs: fT, f

MAXAll FETs peak f

T: 0.3 mA/µm

peak fMAX

: 0.2 mA/µm

1

2 f T

=CgsCgd

gm

RsRdCgd Cgs

1gm Rs

CgdRd

gds

gm

Impact of constant field scaling: fixed MOSFET current density!

f MAX≈f T

2 Rgsq W f2

12 3 lG

gds' 2 f T C gd

' g ' ds Ri'Rs

'

Noise parameters HBT FET

Rn≈1

2gm

RERb Rn≈Pgm

R sRg

Ysopt≈f

f T Rn[ gm

2RERb− j

n2]Ysopt≈

ff T Rn[P gm RsRg− jP]

FMIN≈1 ff TP gm RsRgFMIN≈1 1

f

f T gm

2RERb

n=1 P=23

..1

NFMIN

, fMAX

& linearity

• MOSFET: opt. NFMIN

current density = peak fMAX

• SiGe HBT: opt. NFMIN

current density =1/3 peak fMAX

• InP HBT: opt. NFMIN

current density << peak fMAX

No compromise between NFMIN

, GA and IIP3 in MOSFETs

• Linearity:

OIP3~fMAX

∂2 fMAX

∂ IC DS2

L. Larson, IEEE TED-2003

BiCMOS cascodes

• MOS-HBT (BiCMOS) topology:√ lowest noise, highest linearity, highest MAG√ low supply voltage (V

GS< V

BE)

x low gm

, high Rn, high sensitivity to mismatch

High-Speed Logic FoM:CML Gate Delay

SLHBT=ICpeakfT

CbcCcs

SLFET=IDpeakfT

CgdCdb

HBT≈VC bcC csI T

k RbRLV C1−AV C bcI T

FET≈VC gdC dbI T

k RgRLV C gs1−AV C gd

I T

BiCMOS≈VCC csI T

k RgRLV C gsC gd

I T

High-Speed CML gate delay

HBT-CML requires 250 .. 300 mVpp

swing, irrespective of nodeMOS-CML requires 450 .. 300 mV

pp swing decreasing with node

Circuit Examples

2.5-V, DC-to-45 GHz, SiGe BiCMOS 2.5-V, DC-to-45 GHz, SiGe BiCMOS Up/Downconv Up/Downconv (T Dickson et al. IEEE Trans. MTT-2004)(T Dickson et al. IEEE Trans. MTT-2004)

For comparison:

InP-HBT Mixer Kobayashi, 2003GaAs IC Symp.•3.3V, •DC-40GHz,•20 dB gain

LO+

RF

LO-

OUT

Si CMOS, SiGe BiCMOS, InP Low-noise Si CMOS, SiGe BiCMOS, InP Low-noise Broadband PreampsBroadband Preamps

OUT+

OUT-

IN+

IN-

IN

OUT+

OUT+

Si CMOS, SiGe BiCMOS, InP Low-noise Si CMOS, SiGe BiCMOS, InP Low-noise Broadband Preamps: InP HBTBroadband Preamps: InP HBT

(H. Tran et al. GaAs IC Symp. 2003)(H. Tran et al. GaAs IC Symp. 2003)

InP: 40 Gbs

NF at 10 Ghz Data Rate SensitivityCMOS 16.5 dB 20 Gb/s 20 mVpp

SiGe-HBT 10 dB 40 Gb/s 20 mVppInP-HBT 11.5 dB 40 Gb/s 8 mVpp

SiGe: 40 Gbs

20/30 Gb/s, 1.5-V 130-nm CMOS Driver (P. Westergaard et al. CICC-2004)

• Adjustable pre-emphasis • Eye crossing: 40%-60%• Output swing: 0.15V

pp to 0.35V

pp

• Sensitivity: 20mVpp

@20Gb/s

• Dynamic range: 30 dB• 1.5-V supply, 150 mW.• 0.6 mm x 1 mm

20 Gbs

30 Gbs

43 Gb/s,150-nm GaAs p-HEMT Driver (D.McPherson et al. GaAs IC Symp. 2002)

• Adjustable DC offset • Eye Crossing: 30%-70%• Output swing: 1.7V

pp to 3V

pp

• Sensitivity: 600mVpp

@43Gb/s

• -5.2-V supply, 2.8 W.

20 Gbs

2 mm x 4 mm1-metal + airbridge

fT=110 GHz

fMAX

= 180 GHz

40 Gbs

2.5-V, 58-mW, 45-GHz MS DFF2.5-V, 58-mW, 45-GHz MS DFF(T Dickson et al. VLSI Symp.-2004)(T Dickson et al. VLSI Symp.-2004)

45 Gbs

80-Gb/s 2:1 MUX in BiCMOS 80-Gb/s 2:1 MUX in BiCMOS ECL LogicECL Logic

DFF 25 Ghz 60 Ghz? 60-GHz 80-GHz2:1 MUX 60 Gbs 130 Gbs 110 Gb/s 144 GbsDiv by 2 110 Ghz 150 Ghz

80 Gbs

In the pipeline ...

60-GHz WLAN chipset

SiGe and CMOS LNAs @ 52 GHz(M. Gordon and S.Voinigescu, ESSCIRC-2004)

• SiGe HBT 2-stage cascode: 20-dB gain• 90-nm MOS 1-stage cascode: 3-dB gain

SiGe HBT 65-GHz BPSK Transmitter(C. Lee, T. Yao, et al, CSICS-2004)

• VCO with built-in quad switch

SiGe HBT VCOs to 120 GHz(C. Lee, et al CSICS-2004)

Conclusion• Production 1mm InP HBT, 180-nm SiGe

BiCMOS and 90-nm CMOS technologies adequate for most 50-80 GHz applications

• FETs should be biased at constant current density (0.3 mA/mm or 0.2 mA/mm)

• True BiCMOS topology ideal for tuned mm-wave and high-speed ICs

• Circuits in the 50-120 GHz range

Acknowledgments• M. Gordon, A. Mangan, C. Lee, T. Yao, K. Yau

• M. LaCroix, B. Prokes, M. Tazlauanu, H. Tran, D. McPherson

• STMicroelectronics for fabrication

• Micronet, NSERC, Gennum Corporation and STMicroelectronics for financial support

• Quake Technologies for access to 40 Gb/s BERT, GaAs and InP data

• OIT and CFI for equipment grant

• CMC for CAD licenses

Backup

Cutoff Frequency

HBT:

FET: 1

2 f T

=CgsCgd

gm

RsRdCgd Cgs

1gm Rs

CgdRd

gds

gm

1

2 f T

=ECIC=BCkTq IC

C jeCcbReRcCcb

1

2 f T

≈

23

Cox Nf Wf lGCGDOCGSONf WfCGBO Nf lG

Nf COX

Wf

lG

VGS−VT

SiGe HBT & MOSFET VCE

/VDS

fMAX

HBT:

FET:

f MAX≈f T

2 Rgsq W f2

12 3 lG

gds' 2 f T C gd

' g ' ds R i'Rs

'

f MAX≈ f T

8R ' b C ' cb

Best research results• 25-nm InP HEMT f

T/f

MAX: 562 GHz /330 GHz

(Fujitsu, EDL 2002)

• 90-nm n-MOSFET fT/f

MAX: 210(240) GHz / 250

(210) GHz (Intel, IBM, VLSI Tech. Symp. 2004)

• 0.6 mm InP HBT fT/f

MAX: 420 GHz / 420 GHz

(Rodwell, CSICS-2004)

• 120-nm SiGe HBT fT/f

MAX: 300 GHz /300 GHz

(IBM, IMS-2004)

fT, f

MAX summary

• III-V µn/v

sat advantage over Si offset by

advanced lithography and processing• HBT scaling leads to increased power

density per AE but constant per L

E

• MOSFET peak fT/f

MAX current density is

constant over technology nodes and foundries– 0.3 mA/µm for n-channel, and – 0.15 mA/µm for p-channel and is de-coupled (i.e. <) from I

ON

MOSFET linearity: gm, C

15

25

35

45

55

65

75

85

0 0.5 1 1.5VGS(V)

Cdb

& C

ds (f

F)

LVT NMOS, VDS=0.8V L=0.13mm, W=4mm, N=10

Before de-embedding

After de-embedding

Cds

Cdb

15

17

19

21

23

25

0 0.5 1 1.5VGS(V)

Gat

e-D

rain

Cap

acita

nce

(fF)

LVT NMOS: L=0.13mm, W=4mm, N=10VDS=0.8V

Before RS, RD, RG de-embedding

After RS, RD, RG de-embedding

20

30

40

50

0 0.5 1 1.5VGS(V)

Gat

e-So

urce

Cap

acita

nce

(fF)

LVT NMOS: L=0.13mm, W=4mm, N=10VDS=0.8V

Before RS, RD, RG de-embedding

After RS, RD, RG de-embedding

0

10

20

30

40

50

0 0.5 1 1.5VGS(V)

gm (m

S)

0

2

4

6

8

10

gds

(mS)

LVT NMOS, VDS=0.8V L=0.13mm, W=4mm, N=10

After de-embedding gm

Before de-embedding

gds

•Extracting capacitance from S-param meas. & de-embedding R

S, R

G, R

D critical

to MOSFET model accuracy

•CGD/C

GS = 0.45

(not captured by BSIM3/4)

Beyond peak fT bias, g

m, C

GS, C

GD, C

DB are de-facto constant.

Voinigescu et al.,ICMTS-2004

FMIN

FMIN FET≈12 k1ff T gm

' Rs'

gm' Rgsq Wf

2

123 lG

k212 R i

2 Cgs2

FMIN HBT ≈1 1

f

f T IC

2 VT

RERb1 f T2

f 2 f T2

4 f 2

FMIN MOS ≈1Constf

gm

≈1Constf

VGS−VT

Passives

Why inductors @mm-waves?• Low-noise feedback and matching

• Shunt peaking increases bandwidth by >30% or reduces tail current by 30%

• Higher Q and smaller footprint than at 2-10 GHz

• Significantly smaller area than t-lines

... but harder to measure & model

BW3dB=1

2RLCL

; Lp=CLRL

2

3.1; RL=

Vswing

ITAIL

InP vs. Si inductors

Si mm-wave transformers(T.Dickson et al, IMS-2004)

III-V vs. Si t-lines: similar performance

RF-CMOS: 0.6 dB/mm @ 50 GHzGaAs: 0.4 dB/mm @ 50 GHz

InP: 0.8 dB/mm @ 50 GHzSiGe: 0.4 dB/mm @ 50 GHz

Why AMOS vs. pn-junction varactors @ mm-waves?

• Higher Q • Larger cap. ratio• Linear tuning curve• Lower supply

voltage

C. Lee et al. CSICS-2004

Biasing at IpeakfT (linearity), 0.5*I

peakfT (CML)

and at optimum NFMIN (LNA, VCO, MiXER)

n-MOSFET:

Peak fT bias0.3mA/µm

Min. NFMIN

0.15mA/µm