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EE241 - Spring 2007Advanced Digital Integrated Circuits

Lecture 19: MultipliersVariability

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AnnouncementsHomework 4 due on Thursday (4/12)

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Class MaterialLast lecture

MultipliersToday’s lecture

Finish multipliersIntroduction to variability

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Final Addition

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Final Addition

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Example: CPL Multiplier

BlockDiagram

CriticalPath

Yano,JSSC 4/90

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Example: DPL Multiplier

Ohkubo, JSSC 3/95

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Example: DPL Multiplier

Booth encoder Partial product generator

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Example: DPL Multiplier

FA-based 4:2 Modified 4:2

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Example: DPL Multiplier

Tree construction

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Example: DPL Multiplier

Final adder

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Regularly Structured Tree

Goto, JSSC 9/92

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Regularly Structured Tree

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Regularly Structured Tree

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Regularly Structured Tree

Itoh, JSSC 2/01

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Regularly Structured Tree

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Design Variability

Sources and Impact on Design

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Roadmap Acknowledges VariabilityInternational Technology Roadmap for Semiconductors2005 data

0.50.711.42LER 3σ [nm]

0.50.711.42Lithography 3σ [nm]

0.60.91.41.92.6Total gate CD 3σ [nm]

1622324565DRAM ½ pitch [nm]

20192016201320102007Node year

http://www.itrs.net/Common/2005ITRS/Home2005.htm

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Sources of VariabilityTechnology

Front-end (Devices)Systematic and random variations in Ion, Ioff, C, …

Back-end (Interconnect)Systematic and random variations in R, C

EnvironmentSupply (IR drop, noise)Temperature

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Temporal vs. Spatial VariabilityTemporal variability/correlation

Within-node scaling, Electromigration, Hot-electron effect, NBTI, self-heating, temperature, SOI history effect, supply voltage, crosstalk

Spatial variability/correlationDevice parameters (CD, tox, …)Supply voltage, temperature

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Spatial Variability

Fab to fabDeployed environment

Lot to lot

106 103 100 10-3 10-6 10-9

Across wafer

Across reticle

Across chipAcross block

After RohrerISSCC’06 tutorial

TemperatureMetal polishing

Transistor Ion, IoffLine-edge roughness

Dopant fluctuation

Film thickness

Global Local

Spatial range [m]

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Temporal Variability

Tech. node scalingWithin-node scaling

Electromigration

1012 103 100 10-3 10-6 10-12

NBTI

Hot carrier effect

Tooling changesLot-to-lot

After RohrerISSCC’06 tutorial

TemperatureData stream

SOI history effectSelf heating

Supply noise

Coupling

Technology Environment

Temporal range [s]10-9109 106

Charge

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Systematic vs. Random VariationsSystematic

A systematic pattern can be traced down to lot-to-lot, wafer-to-wafer, within reticle, within die, from layout to layout,…Within-die: usually spatially correlated

RandomRandom mismatch (dopant fluctuations, line edge roughness,…)

Things that are systematic, but e.g. change with a very short time constant (for us to do anything about it). Or we don’t unedrstand it well enough to model it as systematic. Or we don’t know it in advance (“How random is a coin toss?”).

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Dealing with Systematic Variations

Lin, DAC’06 tutorial

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Chip Yield Depends on Inter-Path Correlation

Bowman et al, JSSC, Feb 2002 .

K u

ncor

rela

ted

path

s

Yield = Pr (max delay of K paths < clock period) K = 1 gives highest yield

Normalized Critical Path DelayMax delay of P paths

Nor

mal

ized

PD

F

0.8 0.9 1 1.1 1.20

Mean delay increases as K increases for uncorrelated paths

K =1K =2K =10000

aP bP cPD D

a1 b2 c1D D

Correlated paths reduce impact of variation

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Chip Yield Depends on Inter-Gate Correlation

d1 d2 dn

n stages

D D

Yield = Pr (sum of n delays < clock period)ρ = 0 gives highest yield through increased averaging

Variation remains constant with correlated gates, ρ = 1

∼ 1 / √n0%

5%

10%

15%

20%

0 2 4 6 8 10

Number of stages (n)

σ/m

ean

of to

tal d

elay Variation is reduced with

non-correlated gates, ρ = 0

Non-correlated gates in a path reduce impact of variation

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Impact of Variation on Performance Gain

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5

10

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25 50 75 100 125 150 175 200Technology Node (nm)

Dec

reas

e in

Max

Pro

c.Fr

eque

ncy

(%)

WID+D2Dcorrelated

WIDcorrelated

WID+D2Duncorrelated

WIDuncorrelated

Frequency gain due to scaling

Bowman et al, JSSC, Feb 2002 .

Decrease in frequency due to variation offsets gain due to scaling

Overall gain in performance decreases with scaling

Variations diminish scaling benefits

3*σLWID+D2D = 20%*L

σ2LWID = 50%* σ2LWID+D2D

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Corners

TypicalSlow Fast

Within wafer

Within die

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Systematic (?) Temporal VariabilityMetal 3 resistance over 3 months

P. Habitz, DAC’06 tutorial

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Next LectureVariability - sources