EE241 - Spring 2000bwrcs.eecs.berkeley.edu/.../icdesign/ee241_s00/LECTURES/lecture1-i… · EE241 1...

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UC Berkeley EE241 B. Nikoli c

EE241 - Spring 2000Advanced Digital Integrated Circuits

Tu-Th 2:00 – 3:30pm203 McLaughlin


Practical Information

l Instructor: Borivoje Nikolic570 Cory Hall , 3 -9297, [email protected] hours: TuTh 3:30-5:00pm

l TA: TBA

l Admin: Alev Burton - 558 Cory Hall

l Class Web pagehttp://www-inst.eecs.berkeley.edu/~ee241

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Class Organization

l +/- 5 assignmentsl 1 term-long design project

» Phase 1: Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report

by final week)

l Take-home Final


Class Material

l No textbookl Must be familiar with “Digital Integrated Circuits

- A Design Perspective”, by J. M. Rabaeyl Other reference books:

» “High-Speed CMOS Design Styles, by K. Bernstein, et al.

» “Digital Systems Engineering” by W. Dally» “High-Performance System Design: Circuits and

Logic,” by V.G. Oklobdžija» “Low-Power CMOS Design,” by Chandrakasan and

Brodersen

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Class Material

l List of background material available on web-site

l Selected papers will be made available on web-site» Protected area

l Papers on http://www.melvyl.ucop.edul Class-notes on web-site


Sources

l IEEE Journal of Solid-State Circuits (JSSC)

l IEEE International Solid-State Circuits Conference (ISSCC)

l Symposium on VLSI Circuits (VLSI)l Other conferences and journals

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Class Topics

l This course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies . Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.

l SPECIAL FOCUS in SPRING 2000:» high-performance low -power logic (as needed for digital radio)» interconnect» timing» arithmetic circuits» memory


Class Topics

l Fundamentals - Technology and modeling - Design Tolerances – Limits of scaling (1 week)

l Design for deep-submicron devices - HIGH SPEED (2 weeks)» transistor sizing, buffer design, bootstrapping, reduced swing

l Design techniques for LOW POWER (2 weeks) » analysis of power consumption sources » power minimization at the technology, circuit, and architecture level

l Arithmetic circuits – adders, multipliers (2 weeks) l Impact of interconnect (2 weeks) l Timing (2 weeks)

» Clock skew, Clocking strategies, Self-timed design , arbiters / phase-locked loops

l Memory design (2 week) l Design of array structures (1 week)

» FPGAs and reconfigurable logic

l Design for test (1 week)

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Project Topics

l High-performance low-power logic (radio)l Low voltage designl Interconnect in deep-submicronl Arithmetic circuitsl High-speed communicationl Timing of gigascale circuitsl Reconfigurable logicl Reliability of deep-submicron circuits l Embedded DRAM and/or flashl Other important circuit topics


Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months

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Moore’s Law1 61 51 41 31 21 11 0

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG

2 O

F TH

E N

UM

BE

R O

FC

OM

PO

NE

NT

S P

ER

INT

EG

RA

TE

D F

UN

CT

ION

Electronics, April 19, 1965.


Transistor Count

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

808680286

i386i486

Pentium®Pentium® Pro

K1 Billion

Transistors

Source: Intel

Projected

Pentium® IIPentium® III

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Processor Frequency Trend

386486

Pentium(R)

Pentium Pro(R)

Pentium(R) II

MPC750604+604

601, 603

21264S

2126421164A

2116421064A

21066

10

100

1,000

10,000

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

Mh

z

1

10

100

Gat

e D

elay

s/ C

lock

Intel

IBM Power PC

DEC

Gate delays/clock

Processor freq scales by 2X per

generation

Ê Frequency doubles each generationË Number of gates/clock reduce by 25%

V.De, S. BorkarISLPED’99


Technology Scaling

l Goals of scaling the dimensions by 30%:» Reduce gate delay by 30% (increase operating

frequency by 43%)» Double transistor density» Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequencyl Technology generation spans 2-3 years, but

µP speed doubles every generation (not increased only by 43%)

S. Borkar, IEEE Micro, July 1999.

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Total Transistor Width

Transistors scale by ~ 30% per generation

Sou

rce:

Inte

l

Pentium II (R)Pentium (R)

Pentium (R)

Pentium MMX (TM)

Pentium II (R)Pentium Pro (R) Pentium MMX

(TM)

Pentium MMX (TM)

Pentium (R) Pentium MMX(TM)

Pentium (R)

Pentium II (R)

Pentium Pro (R)

Pentium II (R)

1

10

100

3 4 5 6 7 8Process Technology Generation

Tran

sist

or S

ize

(met

ers) Total Transistor

Average Transistor


Technology Evolution (1997 data)

National Technology Roadmap for Semiconductors

17000100006000350021001250750Max frequency [MHz],Local

1831751701601309070Max µP power [W]

1098-97-876-76Metal layers

0.40.5-0.60.6-0.90.9-

1.21.2-1.5

1.5-1.8

1.8-2.5Supply [V]

25355070100140200Channel length

[nm]

2014201120082005200219991997Year of Introduction

http://www.sematech.org

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Technology Roadmap


Moore’s Law – Logic Density

A. Masaki, 1992.IEEE Circuits & Devices

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Moore’s Law - Logic Density

hrinks and compactions meet density goals

ew micro-architectures drop density

Sou

rce:

Inte

lPentium (R)Pentium Pro (R) 486

386

i860

1

10

100

1000

1.5µ

1.0µ

0.8µ

0.6µ

0.35

µ

0.25

µ

0.18

µ

0.13

µ

Lo

gic

Den

sity

2x trend

Lo

gic

Tra

nsi

sto

rs/m

m2

Pentium II (R)


Interconnect Scaling TrendsMinimum Widths (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

M 5

M 4

M 3

M 2

M 1

Poly

Minimum Spacing (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

M 5

M 4

M 3

M 2

M 1

Poly

Interconnect Stack

01

2

34

5

67

89

10

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

M 5ILD4M 4

ILD3M 3ILD2

M 2ILD1M 1

ILD0PolyField oxide

Gate oxide

Minimum Pitch (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

M 5

M 4

M 3

M 2

M 1

Poly

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Interconnect Distribution

Interconnect distribution does not change significantly

10 100 1,000 10,000 100,000

Length (u)

No

of n

ets

(Lo

g S

cale

)Pentium Pro (R)

Pentium(R) IIPentium (MMX)Pentium (R)

Pentium (R) II

Sou

rce:

Inte

l


Processor Power

386386

486 486

Pentium(R)Pentium(R)

MMX

Pentium Pro (R)

Pentium II (R)

1

10

100

1.5µ 1 µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ

Max

Pow

er (W

atts

) ?

Ê Lead processor power increases every generation

Ë Compactions provide higher performance at lower power

Sou

rce:

Inte

l

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If We Sustain Die Size Trend …

386486

Pentium (R)

Pentium Pro (R)

604

603601

62021066

21064A

21164

100

1,000

10,000

1985 1990 1995 2000 2005 2010

Die

siz

e (m

ils)

Pentium Pro (R)

Pentium (R)

486386

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.5µ 0.8µ 0.35µ 0.18µ 0.1µ

di/d

t in

AU

Pentium (R)

486386

Pentium Pro (R)

0

1

10

100

1,000

10,000

1985 1990 1995 2000 2005 2010

Icc

(am

ps)

386486

Pentium (R)

Pentium Pro (R)

1

10

100

1,000

10,000

1985 1990 1995 2000 2005 2010

Pow

er (

Wat

ts)

Die size grows by 25% to satisfy the trend

di/dt noise increases

100-2,000W100-3,000amps

Due to 30% Vdd scaling


Power Density

0

10

20

30

40

50

60

70

Wat

ts/c

m2

Power density will increase

Surpassed hot-plate power density in 0.6µ

Junction Temp <= 100 C is necessary

– Performance (higher freq)– Exponential growth in leakage– Exponential impact on reliability

Low cost and more efficient heat spreading techniques are needed

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Productivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty


Feature Size

Pessimistic scenario(very much so)

Mainstream scenarioOptimistic scenario(?)

J. Meindl, Apr. 1995.Proceedings IEEE

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Chip Dimension

1960: 1.2 mm1980: 6.5-7mm2000: 25-30mmDriven by economy


Packing Efficiency

Unused silicon area

3D Packing

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Integration Density

N=D2PE/F


Trends in Power Dissipation

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Energy


Chip Performance Index

EE241 - Spring 2000bwrcs.eecs.berkeley.edu/.../icdesign/ee241_s00/LECTURES/lecture1-i… · EE241 1...

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