EE241 - Spring 2002bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s02/Lectures/lectur… ·...

16
EE241 1 UC Berkeley EE241 B. Nikolic EE241 - Spring 2002 Advanced Digital Integrated Circuits Lecture 26 High-Speed Links Based on materials by M. Horowitz, S. Sidiropoulos UC Berkeley EE241 B. Nikolic Announcements l No class, office hour on Tuesday, May 7. » Class will be pre-taped on May 6, 12:30-2pm l Homework #5 due on May 7 l Last lecture is on May 14 l Project presentations are on May 16, 9am- 12pm, in BWRC l Final exam is in 103 GPB, Wednesday, May 22, 8-11am

Transcript of EE241 - Spring 2002bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s02/Lectures/lectur… ·...

  • EE241

    1

    UC Berkeley EE241 B. Nikolic

    EE241 - Spring 2002Advanced Digital Integrated Circuits

    Lecture 26High-Speed Links

    Based on materials by M. Horowitz, S. Sidiropoulos

    UC Berkeley EE241 B. Nikolic

    Announcementsl No class, office hour on Tuesday, May 7.

    » Class will be pre-taped on May 6, 12:30-2pm

    l Homework #5 due on May 7l Last lecture is on May 14l Project presentations are on May 16, 9am-

    12pm, in BWRCl Final exam is in 103 GPB, Wednesday, May

    22, 8-11am

  • EE241

    2

    UC Berkeley EE241 B. Nikolic

    Readingl Chapter 19, High-Speed Inter-Chip

    Signaling, by Sidiropoulos, Yang, Horowitz

    l Digital Systems Engineering, by W.J. Dally and J.W. Poulton, Cambridge’98

    UC Berkeley EE241 B. Nikolic

    TerminationsOff- versus On-chip Terminations

    Should be linear and process, supply-voltage and temperature independent

  • EE241

    3

    UC Berkeley EE241 B. Nikolic

    FET Terminations

    IV-characteristicof two-element resistor

    [Dally]

    UC Berkeley EE241 B. Nikolic

    Pass-gate Style Termination

  • EE241

    4

    UC Berkeley EE241 B. Nikolic

    Adjustable Terminators

    Thermometer-codedAdjustmentsReduces switch-noise

    UC Berkeley EE241 B. Nikolic

    Link Issuesl Signaling: sending and receiving the information

    l Clocking: Determining which bit is which

    RxTx

    RTERM

    Channel

    RTERM

    tbit /2

    1 0 0 01 01

  • EE241

    5

    UC Berkeley EE241 B. Nikolic

    Transmitter Design

    l Critical components: Sync, Mux, Tx

    l Design issues:» Slew rate control vs ISI, jitter» Output current and impedance control

    l Clock and Driver power dissipation

    Data Generation Pre-Driver Driver

    Tx50Ω

    Sync MuxEncoder

    UC Berkeley EE241 B. Nikolic

    Transmitter Frequency Limits

    l Max clock frequency > 8-FO4 (I.e. 1-GHz @ 0.25u)l Faster links should use multiple clocks:

    » Critical on mux/demux

    2.5 3.5 4.5 5.50.0

    10.0

    20.0

    30.0

    40.0

    50.0

    60.0

    Clock pulse width (FO-4)

    Pulse am

    plitude reduction %

  • EE241

    6

    UC Berkeley EE241 B. Nikolic

    Simple Transmitter

    l DDR: send a bit per clock edgel Critical issues:

    » 50% duty cycle» Tbit > 4-FO4

    Data_O

    Data_E1 2 3 4 50

    10

    20

    30

    bit time (normalized to FO4)

    outp

    ut p

    ulse

    wid

    th c

    losu

    re (

    %)

    UC Berkeley EE241 B. Nikolic

    Fastest Transmitter» Off chip time constant smaller than on chip:ÞGenerate current pulse at the output

    » Limited only by the output capacitance

    out

    out_bRTERMRTERM

    x 8

    d0 d0

    ck3

    D0 D1 D2data(ck0)

    clock(ck3)

    0.50 0.60 0.70 0.80 0.90 1.000.0

    10.0

    20.0

    30.0

    Bit-width (#FO-4)

    % e

    ye c

    losu

    re

    » Limiting time constant 25-Ω*Cpad» Cpad = 8*Cdriver + Cesd

  • EE241

    7

    UC Berkeley EE241 B. Nikolic

    Simple Receiver

    l Preconditioning stage: filter/integrate rectify CMl Latch makes decision (4-FO4)l DAC can be used to compensate offsets

    in

    ref

    clk

    A latch

    D/A

    clk

    UC Berkeley EE241 B. Nikolic

    Fastest Receiver

    l Use multiple input receivers» Simplest 2, more complex 4-8» Decouples Tbit from latch resolution» Leverage high input impedance amplifiers

    D0 D1 D2 D7

    clk0

    clk1

    clk2

    clk3

    Ring Oscillatorclk0 clk1 clk2 clk3

    ck0

    ck1

    ck2

    ck3

    ck4

    din

    To A

    mp

    lifie

    rs

  • EE241

    8

    UC Berkeley EE241 B. Nikolic

    Generating the Sample ClockTwo options:l Send clock with data

    » Hope that wire delays match

    l Extract clock from data» Use data transitions

    l PLL/DLL» Uses feedback» Adj phase of int clk» Many different designs

    – Delay line based– VCO based

    DLL

    clk

    ref clk

    data

    ref

    ref clk

    D0 D1 D2 D3data

    clk

    UC Berkeley EE241 B. Nikolic

    Dual-Loop PLLPD/CP

    FSMPD

    inCLK

    C0 CΠ

    CLK

    DCA

    B0 BΠ

    0o 30o 60o 90o 120o 150o

    φ-I

    φ

    ψ

    φ’

    ψ’AMP

    CLK BUF

    refCLK

    +

    PERIPHERALDLL

    CORE DLL

    Θ

  • EE241

    9

    UC Berkeley EE241 B. Nikolic

    Silicon Trends l Scaling

    » Vdd scales, transistors get smaller» Idsat/µ stays constant» Gates get faster

    l Speed: should scale with technologyl Power:

    » For constant output current– Device size roughly constant– Output capacitance roughly constant

    l Output current constant, on-chip power scales

    l Pretty picture, but...

    UC Berkeley EE241 B. Nikolic

    Problem #1: Silicon Is Not Ideal

    l Noise: » Both on timing and signaling» Both AC and DC

    l Timing noise:

    » AC: jitter (scales with process), DC: offset (does not)

    l Signaling noise:» AC (two kinds: proportional to swing and uncorrelated)» DC offsets (do not scale but are correctable)

    Time Reference

  • EE241

    10

    UC Berkeley EE241 B. Nikolic

    DC Timing Offset Compensation

    l E.g.: Third generation Rambus DRAM Clocking

    » Offsets compensated once at boot time and stay VT independent through bias tracking

    » Main limitation is PC boot time

    Mixer Clk BufAmp

    Ph.Det.CTM

    up/dnCNT

    Decoder

    8

    Adder

    Decoder

    Mixer Clk BufAmp

    8

    8

    8From

    Core DLL

    FromCore DLL

    TOFFS

    FbClk

    Core DLLCTM

    CTM

    8

    TCLKTOFFS Peripheral T-DLL

    CFM

    RCLKROFFS Peripheral R-DLL

    8

    UC Berkeley EE241 B. Nikolic

    Offset Compensation Linearity

    0 64 128 192Offset Register Value

    0

    90

    180

    270

    360

    Ph

    ase

    Off

    set

    (deg

    rees

    )

    400 MHz533 MHz

    255

    » Digital-to-time converter is better than 5-bits accuracy

  • EE241

    11

    UC Berkeley EE241 B. Nikolic

    Problem #2: Channel Is NOT Ideal

    » At high frequencies– Wires have loss– Packages have crosstalk– ESD becomes important– Si-substrate losses non-negligible

    100MHz 1GHz 10GHz-21.0

    -15.0

    -9.0

    -3.0

    6m H(s)12m H(s)

    UC Berkeley EE241 B. Nikolic

    Other Channel Non-Idealitiesl Image currents are largel High density IO may dictate pseudo-differential

    l AC-ground impedance is worse at HF» A lot of vias close to package

    á Small system voltage margins» Systems shipping in volume with

  • EE241

    12

    UC Berkeley EE241 B. Nikolic

    Solution: Use Signal Processing

    l Modems have been using it forever..

    l True random noise is really small

    l Deterministic noise is what degrades margins» Figure out where the noise is coming from and cancel it

    l ISI is frequency dependent attenuationl Crosstalk is data dependent coupling

    UC Berkeley EE241 B. Nikolic

    Equalization Example

    l ZFE: Transmitter Tx(s) is approx 1/Ch(s)

    0.0 0.3 0.6 0.9 1.2-0.3

    -0.1

    0.1

    0.3

    0.5

    0.7UnequalizedEqualization PulseEnd of Cable

    time (ns)

    Vol

    tage

  • EE241

    13

    UC Berkeley EE241 B. Nikolic

    More Signal Processingl Get multiple bits/Hz:

    » Step-1: – Simultaneous bi-directional

    Vlinedrv

    VrefVrefH (shared)VrefL (shared)

    rcvr

    receive signal

    transmit signal

    VlineVref

    (Vline - Vref)+ve

    -ve

    VrefH

    VrefL

    UC Berkeley EE241 B. Nikolic

    Simultaneous Bidirectional Eyes

    voltagemargin

    timing margin timing margin

    *Transmit signal & receive signal in quadrature phase

    Fixed VrefL= Vdd – 1.5*Vswing

  • EE241

    14

    UC Berkeley EE241 B. Nikolic

    More Bits/Hzl Multi-level signaling (aka PAM)

    » Convert extra voltage margin to more bits

    l For constant bits/sec» 1/2 Tsymbol» 1/3 Vmargin

    » Real problem is that we rarely have enough marginÜNeed even more signal processing

    UC Berkeley EE241 B. Nikolic

    Electrostatic Discharge (ESD)l IC handling environment can generate

    voltages of 5kV (humid) or 35kV (dry)l Industry standard stress tests:

    » Human body model: discharge 100pF through 1.5kΩ

    » Machine model: discharge 200pF through 0.75µH, small R

    » Charged device model: discharging IC to ground

  • EE241

    15

    UC Berkeley EE241 B. Nikolic

    Human Body Model

    UC Berkeley EE241 B. Nikolic

    ESD ProtectionBidirectional I/O

  • EE241

    16

    UC Berkeley EE241 B. Nikolic

    Double Diode ESD in N-Well