EE241 - Spring 2011
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1 EE241 Spring 2011 EE241 - Spring 2011 Advanced Digital Integrated Circuits Lecture 20: High-Performance Logic Styles Styles Announcements Quiz #3 today Homework #4 posted This lecture until 4pm Reading: Chapter 8 in the Bowhill text (by Gronowski) Background material from Rabaey, 2 nd ed, Chapters 6,10 2
Transcript of EE241 - Spring 2011
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EE241 Spring 2011EE241 - Spring 2011Advanced Digital Integrated Circuits
Lecture 20: High-Performance Logic StylesStyles
Announcements
Quiz #3 today
Homework #4 posted
This lecture until 4pm
Reading: Chapter 8 in the Bowhill text (by Gronowski)
Background material from Rabaey, 2nd ed, Chapters 6,10
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Outline
Last lectureLeakage management
Power gating
Back bias
This lectureOptimal leakage
Back to design for performance
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Optimal VDD VThOptimal VDD, VTh
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Optimal VDD, VTh
Adjusting VDD, VTh trades of energy and delay
We studied energy-limited designThere are alternate ways for optimizing energy and delay together
E.g. energy-delay product (EDP)
Or EnDm, n,m > 1
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Optimal EDP Contours
6Gonzalez, JSSC 8/97
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Topology Inverter Adder Decoder
(ELk/ESw)ref 0.1% 1% 10%Reference Design:Dref (Vdd
max,Vthref)
Sizing, Supply, Threshold Optimization
Large variation in optimal circuit parameters Vddopt, Vth
opt, wopt
Vddmax Vth
max
7Technology parameters (Vdd
max, Vthref) rarely optimal
Vddmin Vth
min
Energy efficient curvef (W,Vdd,Vth)
gy
(Ere
f)
Sensitivity W Vdd Vth
(Dref,Eref) 1.5 0.2
(D E ) 1
Result: E-D Tradeoff in an Adder
ReferenceDesign(Dref,Eref)
(Dmin,Eref)
En
erg (Dref,Emin) 1
(Dmin,Eref) 22 16 22
-80%
-40%
80% of energy savedwithout delay penalty
8Delay (Dref)
(Dref,Emin) 40% delay improvement without energy penalty
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Energy-constrained delay
Active power2
DDact fCVP
f = 1/LDtp
Leakage power
Eli i t i bl (V ) d fi d P (V )
DDS
VV
leak VeIPDDTh
0
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Eliminate one variable(VTh) and find Pmin(VDD)
Nose, ASP-DAC’00
Large (ELk/ESw)opt
Flat EOp minimum
T l d d t
Minimum energy: ESw = 2ELk
0.8
1
Opef
Vthref-180mV
0 81Vmax
2
ln
Lk Sw optd
avg
E EL
K
Topology dependent
0.2
0.4
0.6
EO
p /
nom
inal
EOre
nominalparallelpipeline
0.81Vdd
Vthref-95mV
0.57Vddmax
Vthref-140mV
0.52Vddmax
10Optimal designs have high leakage (ELk/ESw ≈ 0.5)
10-2
10-1
100
101
0
ELeakage
/ESwitching
pipeline
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Subthreshold Optimum
f = 30kHz Minimum is independent of VT
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Minimum is independent of VT
Calhoun, JSSC 9/05
High-Performance High Performance Logic Styles
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CMOS Logic Styles
CMOS tradeoffs:Speed
P ( )Power (energy)
Area
Design tradeoffsRobustness, scalability
Design time
Many styles: don’t try to remember the names –
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Many styles: don t try to remember the names –remember the principles
CMOS Logic Styles
VDD
Complementary
Pass Transistor Logic
PUN
PDN
ABC
OUT
ABC
LOGIC
NETWORK
ABC
OUT
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GND
robustscales
large and slow
simple and fastnot always very efficientversatile
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CMOS Logic Styles
VDD
Ratioed Logic
VDD
Dynamic Logic
LOAD
ABC PDN
OUT
GND
RPDN <<RLOAD
PDN
In1In2
In3
Out
CL
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GND
small & faststatic power
Small & fastest!Noise issuesScales?
Pulsed Static CMOS
RH – Reset highRL – Reset low
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Fast pull-up Fast pull-down
Chen, Ditlow, US Pat. 5,495,188 Feb. 1996.
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PS-CMOS
Evaluation and reset waves: reset is 1.5x slower
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PS-CMOS
Advantages:
No dynamic nodes – good noise immunity
R t d l l th l tiReset delay slower than evaluation
No data dependent delay (worst case gets better)
No false transitions
Disadvantages
Width of reset wave limits logic depth
M i i d i
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Margin in design
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Pass-Transistor LogicPass Transistor Logic
Pass-Transistor Logic
B
Inpu
ts Switch
Network
OutOut
A
BB
• N transistors
• No static consumption B
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No static consumptionA
BF = AB
0
• Transistor implementation using NMOS
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Pass-Transistor Logic Families
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Pass-Transistor Logic
Performance of PTL:Advantage over CMOS in implementing XOR, MUXDisadvantage in implementing AND, OR.
Datapaths, arithmetic circuits are examples of use:Adders and multipliers use XOR, MUXAdvantage of complementary implementation
Comparisons:Wh l i f il i i t d d th l h t
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When a new logic family is introduced, the examples are chosen to show its advantages; (not disadvantages).Comparison papers sometimes point to the disadvantages
Full-custom design
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Examples of PTL Styles
Complementary Pass-Transistor Logic (CPL)NMOS-only pass-transistor network
Transmission-gate logicNMOS+PMOS pass gates
Double Pass-Transistor Logic (DPL)NMOS+PMOS network
Numerous other logic families
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Numerous other logic families
Complementary Pass-Transistor Logic (CPL)
FPass-Transistor
Network
AABB
FPass-TransistorNetwork
B
AABB
Complementary
• Complementary functions• Reduced number of logic levels
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• Reduced number of logic levels• Less transistors than CMOS • Fast – reduced load• Complementary inputs – complementary outputs• VT drop – several solutions
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CPL
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Level restoration
Yano et al, CICC’89, JSSC 4/90
CPL
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Same topology of networksJust different signal arrangements
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CPL vs. CMOS
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Leap Cell Library
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Yano et al, CICC’94, JSSC 6/96
Goal: Implement full logic functionality with small libraryRely on automated design methodology
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Various Logic Functions of the Lean Library
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Double Pass-Transistor Logic (DPL)
B
A B B A
VDD
BA BAND/NAND
A A
OO
A B BA
AB
B A B A
A B
XOR/XNOR
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A
B
B
OO
A
B
A
XOR/XNOR
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Applications of DPL
1.5ns 32-bit ALU in 0 25 m CMOS
Full adder:
in 0.25m CMOS
31Suzuki, ISSCC’93JSSC 11/93
Applications of DPL
54x54bit DPL Multiplier in 4.4ns
32Ohkubo, CICC’94, JSSC 5/95
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4:2 Compressor in DPL
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Adder in DPL
344-bit adder 8-bit adder
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Domino LogicDomino Logic
Reading
Chapter 8 in the Bowhill text (by Gronowski)
Background material from Rabaey, 2nd ed, Chapters 6,10
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Dynamic Logic
VDD VDD
Mp
M
PDN
In1In2
In3
OutMe
M
PUN
In1In2
In3
Out
CL
CL
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Me Mp L
p networkn network
2 phase operation:• Evaluation
• Precharge
Dynamic Gates
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NMOS Inverter PMOS Inverter
Courtesy of IEEE Press, New York. 2000
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Dynamic Logic
Advantages:FastCompactCompact
Need to watch out for:PowerNoise marginsCharge leakageCharge sharing
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Charge sharingNoise couplingCharge injectionCascading dynamic gates
Logical Effort
In
Out
40LE =
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Logical Effort
Out
Out
41LE =
LE =
Charge Leakage
42Courtesy of IEEE Press, New York. 2000
ILeak = (IN sub + IN diode) – (IP sub + IP diode)
Time to switch the next gate: tsw = (CDYN * Vsw)/ILeak
Limits the minimum frequency:fmin = 1/(tsw * #phases per clk cycle)
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Compensating Leakage
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Charge Sharing (Redistribution)
VDD case 1) if Vout < VTn
MpOut
ACL
C
MaX
CLVDD CLVout t Ca VDD VTn VX – +=
or
Vout Vout t VDD–CaCL-------- VDD VTn VX – –= =
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Me
B = 0Ca
Cb
Mb
Vout VDD
CaCa CL+----------------------
–=
case 2) if Vout > VTn
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Charge Sharing - Solutions
VDDVDD
Mp
Out
A
B
Ma
Mb
Mbl MpOut
A
B
Ma
Mb
Mbl
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Me Me
(b) Precharge of internal nodes(a) Static bleeder
Aside: Dynamic Latch
46Courtesy of IEEE Press, New York. 2000
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Charge Sharing
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A,B = 0DYN prechargedCharge sharing ifSEL toggles
Courtesy of IEEE Press, New York. 2000
Aside: Noise in ICs
Sources of noiseCoupling
Device couplingDevice couplingCapacitive coupling between wiresInductive coupling
Supply line bounceCharge Injection
From substrate
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-particles, cosmic rays
Robustness of a circuitNoise marginsSensitivity to noise
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Clock Feedthrough
VDD
MpOut
ACL
Ca
MaX
2.5V
h t
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Me
B Ca
Cb
Mb overshoot
out
Miller and Back-gate Coupling
50Courtesy of IEEE Press, New York. 2000
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Capacitive Coupling
51Courtesy of IEEE Press, New York. 2000
Capacitive Coupling
Dynamic node: Static node:
52Courtesy of IEEE Press, New York. 2000
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Capacitive Coupling
Lateral coupling: Shielding
53Courtesy of IEEE Press, New York. 2000
Minority Charge Injection
54Courtesy of IEEE Press, New York. 2000
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Supply Noise
55Courtesy of IEEE Press, New York. 2000
Next Lecture
Design in domino logic
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