EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm
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EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm May 7, 2009 Richard Dorrance & Newton Hang
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EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm. May 7, 2009 Richard Dorrance & Newton Hang. Motivation. Reduce power dissipation Subthreshold logic as alternative to CMOS Improve full adder design Low power arithmetic and computation Increase robustness in subthreshold logic - PowerPoint PPT Presentation
Transcript of EE241 Spring 2009: Robust Subthreshold Adder Design in 32nm
EE241 Spring 2009:Robust Subthreshold Adder Design in 32nm
May 7, 2009
Richard Dorrance &Newton Hang
Motivation
•Reduce power dissipation▫ Subthreshold logic as alternative to CMOS
•Improve full adder design▫ Low power arithmetic and computation▫ Increase robustness in subthreshold logic▫ Make subthreshold 32nm full adder feasible
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Current and Proposed Techniques•Sizing
▫ Super-threshold sizing ratio not optimal in subthreshold▫ Up size transistors x3-10 for increased robustness
•Sub-DTMOS▫ “Dynamic Body-Biasing”▫ Reduced Threshold Voltage &
Increased Mobility (Subthresholdslope approaches 60 mV/dec)
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1-Bit Full Adder Cells
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Experimental Setup
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Noise Margins: Sum
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Noise Margins: Carry
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Failure Rates in N-Bit Ripple Carry Adders
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Reasons for Failure•Lack of individual cell robustness•Pass Transistor (14I & SERF)•Asymmetric inputs (“non-inverter-like”)•Large stacks not compensated for (inverter)
Power-Performance Comparison:Mirror vs Bridge
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Pavg [nW] Tp_sum [ns] Tp_cout [ns]
% FailureMAX AVG STDEV MAX AVG STDEV MAX AVG STDEV
MINIMUM SIZE 14.21 12.92 0.61 2483.00 2124.79 162.82 2418.70 2085.00 163.32 66.00%
SIZING 25.99 23.56 0.92 2674.70 2301.08 166.56 2610.40 2259.04 159.20 1.00%
DTMOS 16.02 14.79 0.50 1550.00 1310.26 96.76 1530.00 1291.86 96.22 0.00%
SIZING & DTMOS 38.31 35.16 1.16 1692.60 1452.87 91.33 1679.40 1439.37 91.23 0.00%
Pavg [nW] Tp_sum [ns] Tp_cout [ns]% Failure
MAX AVG STDEV MAX AVG STDEV MAX AVG STDEV
MINIMUM SIZE 12.99 12.99 NA 2397.90 2397.90 NA 2238.60 2238.60 NA 99.00%
SIZING 32.11 29.10 0.93 4856.20 3909.37 347.18 4466.90 3880.75 353.46 11.00%
DTMOS 16.30 14.80 0.57 1926.00 1599.37 141.64 1530.50 1556.01 137.58 0.00%
SIZING & DTMOS 52.29 47.42 1.64 2442.50 2088.27 148.82 2083.90 2057.27 146.67 0.00%
32-bit Bridge Adder
32-bit Mirror Adder
Same power butMirror Adder
faster!
Conclusion
•Results▫ Mirror adder most practical (best performance)▫ Pass transistor logic more susceptible
•Pros vs. Cons▫ Overall power dissipation still much lower than standard
CMOS technology▫ Possible area issues (independent trenches)
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Future Work•Other Full Adders:
▫ Dynamic
•Other Adder Topologies:▫ Carry Look-ahead Adder▫ Carry Bypass (Skip) Adder▫ Carry Select Adder
•Energy-Delay Optimization
•Questions?
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