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EE 330

Lecture 33

Basic amplifier architectures• Common Emitter/Source

• Common Collector/Drain

• Common Base/Gate

Basic Amplifiers

• Analysis, Operation, and Design

Exam 3 Friday April 13

V1 V2

I1 I2RIN ROUT

AVV1AVRV2

Two Port (Thevenin)

y11A y22A

y12AV2A

y21AV1A

V1A V2A

i1Ai2A

R1

RB

V1B V2B

I1B I2B

g22B

g21BV2B g12BV1B

g11B

Two Port (Norton)

i1C

Linear Two Port

v1C

i2C

v2C

H-parameters

(Hybrid Parameters)

1 11 1 12 2C C C C Ch h V i v

2 21 1 22 2C C C C Ch h i i v

RXX

V1

i1

V2

i2

Two-Port Equivalents of Interconnected Two-ports

Review Previous Lecture

Apply V1, open V2 to get AV but short V2 to get RIN

Apply V2, open V1 to get AVR but short V1 to get ROUT

Circuit analysis steps• Large signal Q-point analysis

– Open cap, short inductors

– Assume operation regions for active devices

– Replace each nonlinear device by its simplified

piecewise linear model

– Compute Q-point: node voltages and device currents

– Verify assumed region

• Small signal DC analysis

– Short DC V-source, open DC I-source

– Short coupling caps

– Replace each nonlinear device by its ss model

– Perform standard linear analysis as in 201


Basic Amplifier Structures

Common Source or Common Emitter

Common Gate or Common Base

Common Drain or Common Collector

Common Input Output Common Input Output

S G D E B C

G S D B E C

D G S C B E

MOS BJT

D

S

G B

E

C

Small Signal Transistor Models

as 3-terminal Devices


Objectives in Study of Basic Amplifier Structures

1. Obtain key properties of each basic amplifier

2. Develop method of designing amplifiers with specific

characteristics using basic amplifier structures

The three basic amplifier types for both

MOS and bipolar processes

Common Emitter

Common Base

Common Collector

Common Source

Common Gate

Common Drain

Will focus on the performance of the bipolar structures and then obtain

performance of the MOS structures by observation

Revie

w P

revio

us L

ectu

re

Methods of Obtaining Amplifier Two-Port Network

1. VTEST : iTEST Method (considered in last lecture)

2. Write V1 : V2 equations in standard form

3. Thevenin-Norton Transformations

4. Ad Hoc Approaches

Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A V

VR 2 1 1 IN

2 2 O V0 1

= R

= R +

A

A

+ V i V

V i V

Two-Port Models of Basic Amplifiers widely used for

Analysis and Design of Amplifier Circuits

Any of these methods can be used to obtain the two-port model

testin

test

R V

i

Ro

V1

i1

v0 1A VV2

Rin

i2

vR 2A VVtestVout-test

out-testVR

test

A V

V

test0

test

R V

i

out-testV0

test

A V

V

Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A VVtest

iTEST

Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A VVtest

Vout-test

Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A VVtest

iTEST

test test: V i Method for Obtaining Two-Port Amplifier Parameters

SUMMARY from PREVIOUS LECTURE

If Unila

tera

l A V

R =

0

Common Emitter

Common Base

Common Collector

Common Source

Common Gate

Common Drain

Will now develop two-port model for each of the three basic

amplifiers and look at one widely used application of each

Consider Common Emitter/Common Source

Two-port Models

Common Emitter

Common Base

Common Collector

Common Source

Common Gate

Common Drain

Will focus on Bipolar Circuit since MOS counterpart is a special case obtained by setting gπ=0

Basic CE/CS Amplifier Structures

R1

VIN

VOUT

RM1

VIN

VOUT

The CE and CS amplifiers are themselves two-ports !

Common Emitter AmplifierCommon Source Amplifier

R1

VIN

VOUT

RM1

VOUT

VIN

Common Emitter

Amplifier

Common Source

Amplifier

Can include or exclude R and R1 in two-port models (of course they are different circuits)

Two-port model for Common Emitter Configuration

Common Emitter

VbegOgmVbe

gπ

B

E

C

Ro

V1

i1

v0 1A V V2Rin

i2

{Ri, AV0 and R0}

?


1. VTEST : iTEST Method




Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A V

VR 2 1 1 IN

2 2 O V0 1

= R

= R +

A

A

+ V i V

V i V




Common EmitterVbe

gOgmVbegπ

B

E

C

Ro

V1

i1

v0 1A V V2Rin

i2

By Thevenin : Norton Transformations

in1

Rg

mV0

0

gA

g 0

0

1R

g 0VRA


1. VTEST : iTEST method




Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A V

VR 2 1 1 IN

2 2 O V0 1

= R

= R +

A

A

+ V i V

V i V




Common Emitter

Ro

V1

i1

v0 1A V V2Rin

i2

{Rin, AV0 and R0}

itest

Vtest VbegOgmVbe

gπ

testin

test

R V

i

in1

Rg

To obtain Rin

Alternately, by VTEST : iTEST Method


Common Emitter

Ro

V1

i1

v0 1A V V2Rin

i2

{Rin, AV0 and R0}

To obtain AV0

Vout-testVtest Vbe

gOgmVbegπ

out-testV0

test

A V

V

0

mout test test

g

g

V V

mV0

0

gA

g



Common Emitter

Ro

V1

i1

v0 1A V V2Rin

i2

{Rin, AV0 and R0}

To obtain g0

0test testi gV

VbegOgmVbe

gπ

itest

Vtest

test0

test

R V

i

00

1R

g



Common Emitter

Ro

V1

i1

v0 1A V V2Rin

i2

00

1R

gm

V00

gA

g in

1R

g

• Input impedance is mid-range

• Voltage Gain is Large and Inverting

• Output impedance is large

• Unilateral

• Widely used to build voltage amplifiers

ti

CQ

VR

I

AF

V0t

VA

V AF

0CQ

VR

I

In terms of operating point and model parameters:

In terms of small signal model parameters:

Characteristics:

0VRA

0VRA

Common Emitter Configuration

Consider the following CE application

B

E

C

VDD

Vin

RC

Vout

VEE

Ro

V1 v0 1A VRin

C

B

E

RC

Vout

Vin

CE Two-Port Model

0 0 V0 inAout Cg g g V V0

0

0 0

ouC

tV

V0

in

AA

Cg g

m

C C

m C

gR

g

g g gg

g

V

V

iinC πn= RR = r

outC o CR = R //R0

0

1ou o CtC CR = R //R R

C

g

C

g

g g

CE Two-port including RC

(this will also generate a two-port model for

this CE application)

Common Emitter inc RC

RC

0VRA



This circuit can also be analyzed directly without using 2-port

model for CE configuration

VbegOgmVbe

gπ RCVin

B

E

CVout

0

1out m in

C

gg g

V V

0

0

CA R

C

out m

in C

g g

mgg

g gV

V=

V

in πR = r

0

0

1out CR = R

Cg

C

g

g g

(this will also generate a two-port model for this CE application)


RC

0VRA



0

CA R

C

g g

mgV

in πR = r

• Input impedance is mid-range

• Voltage Gain is large and Inverting

• Output impedance is mid-range

• Unilateral

• Widely used as a voltage amplifier

0

0

1out CR R

Cg g

Cg g

0

CQ C

t

I RA

V

C

g g

V

0

out CR R

C

g g

tin

CQ

VR =

I

(this is also a two-port model for this CE application)


RC

Small signal parameter domainOperating point and model parameter domain

Characteristics:

0VRA

Common Source/ Common Emitter Configurations

Common Emitter

Common Source

00

1R

gm

V00

gA

g in

1R

g

tin

CQ

VR

I

AF

V0t

VA

V AF

0CQ

VR

I


00

1R

gm

V00

gA

g

inR

inR

22 AF

V0EBQ EBQ

VA

V V

AF0

DQ DQ

V1R

I I

• Input impedance is mid-range (infinite for MOS)


• Output impedance is large

• Unilateral

• Widely used to build voltage amplifiers

Characteristics:

0VRA 0VRA

Common Source/Common Emitter Configuration

0

CA R

C

g g

mgV

in πR = r

• Input impedance is mid-range (infinite for MOS)



• Unilateral

• Widely used as a voltage amplifier

0

0

1out DR R

Dg g

Dg g

0

CQ C

t

I RA

V

C

g g

V

0

out CR R

C

g g

tin

CQ

VR =

I


RC

Common Source inc RD

RD


0

0

1out CR R

Cg g

Cg g0

DA R

D

g g

mgV

inR

inR

0 2 D

EBQ

RA

V

D

g gDQI

V

0

out DR R

D

g g

Characteristics:

0VRA 0VRA

Consider Common Collector/Common Drain

Two-port Models

Common Emitter

Common Base

Common Collector

Common Source

Common Gate

Common Drain


Two-port model for Common Collector Configuration

{RiX, AV0, AV0r and R0X}

?

VbegOgmVbe

gπ

Common Collector

RoX

V1v0 1A V V2

RiXi2i1

v0r 2A V

B

C

E






Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A V

VR 2 1 1 IN

2 2 O V0 1

= R

= R +

A

A

+ V i V

V i V




1 1 2i g V V

Common Collector

VbegOgmVbe

gπV1

i1

V2

i2

2 2 1m o mi g g g g g V V

Applying KCL at the input and output node, obtain

These can be rewritten as

1 1 2πri V V

2 2 1

1 m

m o m o

g g

g g g g g g

V i V

RiX=rπ AVOr=11

0XRm og g g

V0A m

m o

g g

g g g

It thus follows that

RoX

V1

i1

v0 1A VV2

RiX

i2

vR 2A V

V1 : V2 equations in standard form

1 1 2

2 2 1

iX

oX

R

R

VR

V

i A

i A

V V

V V

Standard Two-Port Amplifier Representation


Common Collector

VbegOgmVbe

gπV1

i1

V2

i2

RiX=rπ

AVOr=1

10XR

m og g g

V0A m

m o

g g

g g g

RoX

V1v0 1A V

V2

Rixi2i1

v0r 2A V

B

C

E

Two-port Common Collector Model

1

mg

1

Common Collector Configuration

Consider the following CC application

B

E

C

VSS

VDD

Vin

RE

Vout

RoX

V1v0 1A V V2

Rixi2i1

v0r 2A V

VinRE

Vout

B

C

E

1V V0A = A =

m Eif g g

ox m m o m m

ox E m o m o E m o E m E

g g g g g g g g g

g g g g g g g g g g g g g g g

0X in 1 ix v0r v0 in

0X E

g= R A A

g +gV i V

1E0

m E 0 π m E m E

R1 1R = =

g +g +g +g g +g 1+g R

m E

g g

mg

Determine Rin, R0, and A V

(this is not asking for a two-port model for the CC

application – Rin and AV defined for no additional load

on output, Ro defined for short-circuit input)

1in π π E

rR = r r +βR

E og g

m o E

m o E

m o E

g g g g

g g g g

g g g g

Common Collector

REVIN

VOUT


Consider the following CC applicationB

E

C

VSS

VDD

Vin

RE

Vout

Alternately, this circuit can also be analyzed directly

V1gOgmV1

gπ

RE

Vin

VOUT

iin

0 1out E in mg g g g g V V V

1in out V V V0

CQ EV

CQ E t

I RA

I R +V

m m

m E m E

g g g

g g g g g g

0out m E in mg g g g g g V V

0out m E in mg g g g g g V V

in in outg i V V 0 0in m E in Eg g g g g g g i V

in π EπR r += βR r

E og g

m o E

o E

g g g g

g g


application, – Rin and AV defined for no additional

load on output, Ro defined for short-circuit input -) Common Collector

REVIN

VOUT



E

C

VSS

VDD

Vin

RE

Vout

V1gOgmV1

gπ

RE

Vin

VOUT

iin

0 out out E m outg g g gi V V

1 1out= R

E og g

m o E mg g g g g



load on output, Ro defined for short-circuit input -) Common Collector

REVIN

VOUT

To obtain R0, set 0inV

V1gOgmV1

gπ

RE

VOUT

iout



E

C

VSS

VDD

Vin

RE

Vout

1 1out= R

E og g

m o E mg g g g g



load on output, Ro defined for short-circuit input -)

0

1CQ EV

CQ E t

I RA

I R +V

m m

m E m E

g g g

g g g g g g

in π EπR r += βR r

E og g

m o E

o E

g g g g

g g

Question: Why are

these not the two-port

parameters of this

circuit?

RoX

V1v0 1A V

V2

Rixi2i1

v0r 2A V

B

C

E

Common Collector

REVIN

VOUT

• Rin defined for open-circuit

on output instead of short-

circuit (see previous slide : -2

slides)

• AV0r ≠0


For this CC application B

E

C

VSS

VDD

Vin

RE

Vout

0

VA m

m E

g g

g g g g

in π ER r +βR

E o

g g

1 1E0

m E

RR

1+g R

m E

g R

mg

• Output impedance is low

• AV0 is positive and near 1

• Input impedance is very large

• Widely used as a buffer

• Not completely unilateral but output-input transconductance (or AVr)

is small and effects are generally negligible though magnitude same as AV

CQ EV

CQ E t

I RA

I R +V

CQ E tI R V

in ER βR

CQ E tI R V

t0

CQ

VR

I

(this is not a two-port model for this CC application)

1

m E

if g g

1CQ E tI R V

Common Collector

REVIN

VOUT

Small signal parameter domain Operating point and model parameter domain

Characteristics:

Common Collector/Common Drain ConfigurationsFor these CC/CD applications

B

E

C

VEE

VCC

Vin

RE

Vout

0

VA m

m E

g g

g g g g

in π ER r +βR

E o

g g

1 1E0

m E

RR

1+g R

m E

g R

mg

• Output impedance is low

• AV0 is positive and near 1

• Input impedance is very large

CQ EV

CQ E t

I RA

I R +V

CQ E tI R V

in ER βR

CQ E tI R V

t0

CQ

VR

I

(not two-port models for these applications)

1

m E

if g g

1CQ E tI R V

Common Collector

REVIN

VOUT

Common Drain

RDVIN

VOUT

G

S

D

VSS

Vin

RS

Vout

VDD

0

VA m

m S

g

g g g

1

m S

if g g

inR

1 1S0

m S

RR

1+g R

m S

g R

mg


• Widely used as a buffer

• Not completely unilateral but output-input

transconductance is small

DQ SV

DQ S EBQ

2I RA

2I R +V

1DQ EBQ

2I R V

S

if

DQ S EBQ2I R V

EBQ S EBQ0

EBQ DQ S DQ

V R VR

V +2I R 2I

inR

Consider Common Base/Common Gate

Two-port Models

Common Emitter

Common Base

Common Collector

Common Source

Common Gate

Common Drain


Two-port model for Common Base Configuration

?

VbegOgmVbe

gπ

Common Base

RoX

V1v0 1A V V2

RiXi2i1

v0r 2A V

B

E C

{RiX, AV0, AV0r and R0X}






Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A V

VR 2 1 1 IN

2 2 O V0 1

= R

= R +

A

A

+ V i V

V i V




Common Base

1 1 1 2 0 1mg g g i V V V V

2 2 1 0 1mg g i V V V

From KCL

VbegOgmVbe

gπV1

i1

V2

i2

01 1 2

0 0

1

m m

g

g g g g g g

V i V

2 2 1

0 0

11 mg

g g

V i V

0

1 1iXR

m mg g g g

These can be rewritten as

It thus follows that:0

0

VOrAm

g

g g g

0 0

1V0A m mg g

g g 0

1oXR

g

V1 : V2 equations in standard form

VR 2 1 1 IN

2 2 O V0 1

= R

= R +

A

A

+ V i V

V i V

Standard Form for Amplifier Two-Port

Ro

V1

i1

v0 1A V V2

Rin

i2

vR 2A V


Common Base

VbegOgmVbe

gπV1

i1

V2

i2

0

1 1iXR

m mg g g g

0 0

0

VOrA

m m

g g

g g g g

0 0

1V0A m mg g

g g

0

1oXR

g

RoX

v0 1A VV2

Rini2

v0r 2A V

B

E C

i1

V1

Two-port Common Base Model

Common Base Configuration

Consider the following CB application

B

E

C

VBB

VDD

Vin

RC

Vout

RoX

V1v0 1A V V2

RiXi2i1

v0r 2A V

B

E CVin

RC

Vout

0 0 0

0 0 0

CV V0

C 0X

RA = A

R +R

m mm

C

C

C

g g g g g

g g gg

gR

g

1 iX V0r out inin

1 1

R +AR = =

i VV

i i 0

0 0

1in

iX

V0r V

R=

1-A AR

C

C mm

g g

g g g g g g g

Cout

0 C

RR

1+g R

out C 0XR R //R

(this is not asking for a two-port model for this CB

application - – Rin and AV defined for no load on

output, Ro defined for short-circuit input ) VIN

Common Base

RC

VOUT

Common Base Configuration

Consider the following CB application

B

E

C

VBB

VDD

Vin

RC

Vout

Cout C

0 C

RR R

1+g R

Alternately, this circuit can also be analyzed directly

VbegOgmVbe

gπV1

i1

V2

i2

RCVin

B

E

CVout

By KCL at the output node, obtain

C 0 0 m 0 ing +g = g +gV V 0

0

VA =

mm

C

C

g g

gg R

gBy KCL at the emitter node, obtain

01 m 0 in out= g +g +g g i V V

0 C

C m π 0 π 0in

m

g +g=

g g +g +g +g g

1R

g

out C 0R R //r

(this is not asking for a two-port model for this CB

application – Rin and AV defined for no load on output,

Ro defined for short-circuit input ) VIN

Common Base

RC

VOUT

Common Base Application

B

E

C

VBB

VDD

Vin

RC

Vout

C 0R <<r

out CR R

VA m Cg R

inm

1R

g

CQ CV

t

I RA

V

tin

CQ

VR

I

C 0R <<r

out CR R


• AV0 is large and positive (equal in mag to that to CE)

• Input impedance is very low



(this is not a two-port model for this CB application) VIN

Common Base

RC

VOUT

Characteristics:

Common Base/Common Gate Application

B

E

C

VBB

VDD

Vin

RC

Vout

D 0R <<r

out DR RVA m Cg R

inm

1R

g

DQ DV

EBQ

2I RA

Vt

inCQ

VR

I

CQ C AFI R <<V

out CR R


• AV0 is large and positive (equal in mag to that to CE)

• Input impedance is very low



(these are not a two-port models)

VIN

Common Base

RC

VOUT


Common Gate

VIN RD

VOUT

G

S

D

VGG

VDD

Vin

RD

VOUT

V DA R mg

C 0R <<r

out CR Rin

m

1R

g

CQ CV

t

I RA

V

EBQin

DQ

VR

2I

DQ D

1I R <<

out DR R

Characteristics:

Common Emitter with Emitter Resistor Configuration

B

E

C

VDD

Vin

RC

Vout

RE

VEE

VbegOgmVbe

gπVin

RC

RE

Vout

VE

By KCL at two non-grounded nodes

0 0in E E-out C mg g g g V V V V

0 0E E in E out in- mg g g g g g V V V V V

out m E 0 π C

Vin C m C 0 π E 0 π E E

-g g +g g RA = -

g g +g g +g +g +g g +g R

V

V


B

E

C

VDD

Vin

RC

Vout

RE

VEE

VbegOgmVbe

gπVin

RC

RE

Vout

VE

CV

E

RA -

R

It can also be shown that

out CR R

in π ER r +βR

Nearly unilateral (is unilateral if go=0)


B

E

C

VDD

Vin

RC

Vout

RE

VEE

CV

E

RA -

R

out CR R

in π ER r +βR

• Analysis would simplify if g0 were set to 0 in model

• Gain can be accurately controlled with resistor ratios

• Useful for reasonably accurate low gains

• Input impedance is high

(this is not a two-port model)

Characteristics:

(not two-port models for the four basic structures)

Can use these equations only when small signal circuit is EXACTLY like that shown !!

Basic Amplifier Structures

1. Common Emitter/Common Source

2. Common Collector/Common Drain

3. Common Base/Common Gate

4. Common Emitter with RE/ Common Source with RS

5. Cascode (actually CE:CB or CS:CG cascade)

6. Darlington (special CC:CE or CD:CS cascade)

The first 4 are most popular

Will be discussed later

Why are we focusing on these basic circuits?

1. So that we can develop analytical skills

2. So that we can design a circuit

3. So that we can get the insight needed to design a circuit

Which is the most important?

End of Lecture 33

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