EE 330 Lecture 15 Devices in Semiconductor Processes

52
EE 330 Lecture 15 Devices in Semiconductor Processes Diodes Capacitors MOSFETs

Transcript of EE 330 Lecture 15 Devices in Semiconductor Processes

Page 1: EE 330 Lecture 15 Devices in Semiconductor Processes

EE 330Lecture 15

Devices in Semiconductor Processes

• Diodes

• Capacitors

• MOSFETs

Page 2: EE 330 Lecture 15 Devices in Semiconductor Processes

Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

Review from Last Lecture

Page 3: EE 330 Lecture 15 Devices in Semiconductor Processes

Analysis of Nonlinear Circuits (Circuits with one or more nonlinear devices)

What analysis tools or methods can be used?

KCL ?

KVL?

Superposition?

Voltage Divider ?

Current Divider?

Thevenin and Norton Equivalent Circuits?

Nodal Analysis

Mesh Analysis

Two-Port Subcircuits

Review from Last Lecture

Page 4: EE 330 Lecture 15 Devices in Semiconductor Processes

Diode Models

ID

VD

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Which model should be used?

The simplest model that will give acceptable results in the analysis of a circuit

Review from Last Lecture

Page 5: EE 330 Lecture 15 Devices in Semiconductor Processes

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Id (

am

ps)

Vd (volts)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Id (

am

ps)

Vd (volts)

Diode Characteristics

ID

VD

Diode Model Summary

Diode Equation

d

t

V

V

d SI = I e -1

d d

d d

I = 0 if V < 0.6V

V =0.6V if I > 0

d d

d d

I = 0 if V < 0

V =0 if I > 0

d d

d d d d

I = 0 if V < 0.6

V =0.6+I R if I > 0

Piecewise Linear Models

Review from Last Lecture

Page 6: EE 330 Lecture 15 Devices in Semiconductor Processes

Diode Model Summary

Diode Equation

d

t

V

V

d SI = I e -1

d d

d d

I = 0 if V < 0.6V

V =0.6V if I > 0

d d

d d

I = 0 if V < 0

V =0 if I > 0

d d

d d d d

I = 0 if V < 0.6

V =0.6+I R if I > 0

Piecewise Linear Models

When is the second piecewise-linear model adequate?

When is the ideal model adequate?

When it doesn’t make much difference whether Vd=0V or Vd=0.6V

When it doesn’t make much difference whether Vd=0.6V or Vd=0.7V

Review from Last Lecture

Page 7: EE 330 Lecture 15 Devices in Semiconductor Processes

Example: Determine IOUT for the following circuit

10K

12V

IOUT

D1

Solution:

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

4. Validate state of guess in step 2 (verify the “if” condition in model)

5. Assume PWL with VD=0.7V

6. Guess state of diode (ON)

7. Analyze circuit with model

8. Validate state of guess in step 6 (verify the “if” condition in model)

9. Show difference between results using these two models is small

10. If difference is not small, must use a different model

Strategy:

Val

idat

e M

od

el

Sele

ct

Mo

del

Review from Last Lecture

Page 8: EE 330 Lecture 15 Devices in Semiconductor Processes

Solution:

10K

12V

IOUT

0.6V

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

1 14OUT

12V-0.6VI = .

10KmA

4. Validate state of guess in step 2

To validate state, must show ID>0

D OUTI =I =1.14mA>0

Review from Last Lecture

Page 9: EE 330 Lecture 15 Devices in Semiconductor Processes

Solution:

10K

12V

IOUT

0.7V

5. Assume PWL model with VD=0.7V, RD=0

6. Guess state of diode (ON)

7. Analyze circuit with model

1 13OUT

12V-0.7VI = .

10KmA

8. Validate state of guess in step 6

To validate state, must show ID>0

D OUTI =I =1.13mA>0

Review from Last Lecture

Page 10: EE 330 Lecture 15 Devices in Semiconductor Processes

Solution:

9. Show difference between results using these two models is small

OUT OUTI =1.14mA and I =1.13 mA are close

Thus, can conclude OUTI 1.14mA

Review from Last Lecture

Page 11: EE 330 Lecture 15 Devices in Semiconductor Processes

Example: Determine IOUT for the following circuit

10K

0.8V

IOUT

D1

Solution:

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

4. Validate state of guess in step 2

5. Assume PWL with VD=0.7V

6. Guess state of diode (ON)

7. Analyze circuit with model

8. Validate state of guess in step 6

9. Show difference between results using these two models is small

10. If difference is not small, must use a different model

Strategy:

Page 12: EE 330 Lecture 15 Devices in Semiconductor Processes

Solution:

10K

0.8V

IOUT

0.6V

1. Assume PWL model with VD=0.6V, RD=0

2. Guess state of diode (ON)

3. Analyze circuit with model

20OUT

0.8 - 0.6VI =

10KA

4. Validate state of guess in step 2

To validate state, must show ID>0

D OUTI =I =20 A>0

Page 13: EE 330 Lecture 15 Devices in Semiconductor Processes

Solution:

10K

0.8V

IOUT

0.7V

5. Assume PWL model with VD=0.7V, RD=0

6. Guess state of diode (ON)

7. Analyze circuit with model

10OUT

0.8V-0.7VI =

10KA

8. Validate state of guess in step 6

To validate state, must show ID>0

D OUTI =I =10 A>0

Page 14: EE 330 Lecture 15 Devices in Semiconductor Processes

Solution:

9. Show difference between results using these two models is small

OUT OUTI =10 A and I =20 A are not close

10. If difference is not small, must use a different model

Thus must use diode equation to model the device

10K

0.8V

IOUT

0.6V

VDD

OUT

0.8-VI =

10K

D

t

V

V

OUT SI =I e

Solve simultaneously, assume Vt=25mV, IS=1fA

Solving these two equations by iteration, obtain VD= 0.6148V and IOUT=18.60μA

Page 15: EE 330 Lecture 15 Devices in Semiconductor Processes

Use of Piecewise Models for Nonlinear Devices

when Analyzing Electronic Circuits

Process:

1. Guess state of the device

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify model (if necessary)

Observations:

o Analysis generally simplified dramatically (particularly if piecewise model is linear)

o Approach applicable to wide variety of nonlinear deviceso Closed-form solutions give insight into performance of circuito Usually much faster than solving the nonlinear circuit directlyo Wrong guesses in the state of the device do not compromise solution

(verification will fail)

o Helps to guess right the first timeo Detailed model is often not necessary with most nonlinear deviceso For practical circuits, the simplified approach usually applies

Key Concept For Analyzing Circuits with Nonlinear Devices

Page 16: EE 330 Lecture 15 Devices in Semiconductor Processes

Use of Piecewise Models for Nonlinear Devices when

Analyzing Electronic Circuits

Process:1. Guess state of the device

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify model (if necessary)

What about nonlinear circuits (using piecewise models) with time-varying inputs?

80Vsin500t

1K

1K

Vout

D1

Same process except state verification (step 3) may include a range where solution is valid

Page 17: EE 330 Lecture 15 Devices in Semiconductor Processes

80Vsin500t

1K

1K

Vout

D1VIN

Example: Determine VOUT for VIN=80sin500t

Guess D1 ON (will use ideal diode model)

1K

Vout

D1

ID

1K

VIN

VOUT=VIN=80sin(500t)

Valid for ID>01

IND

VI

K

Thus valid for VIN > 0

Page 18: EE 330 Lecture 15 Devices in Semiconductor Processes

80Vsin500t

1K

1K

Vout

D1VIN

Example: Determine VOUT for VIN=80sin500t

Guess D1 OFF (will use ideal diode model)

VOUT=VIN/2=40sin(500t)

Valid for VD<02

IND

VV

Thus valid for VIN < 0

1K

Vout

D1

VD

1K

VIN

Page 19: EE 330 Lecture 15 Devices in Semiconductor Processes

80Vsin500t

1K

1K

Vout

D1VIN

Example: Determine VOUT for VIN=80sin500t

Thus overall solution

80sin 500 0

40sin 500 0

IN

OUT

IN

t for VV

t forV

t

80V

t

80V

-40V

VIN

VOUT

Page 20: EE 330 Lecture 15 Devices in Semiconductor Processes

Use of Piecewise Models for Nonlinear Devices when

Analyzing Electronic Circuits

Process:

1. Guess state of the device

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify model (if necessary)

What about circuits (using piecewise models) with multiple nonlinear devices?

80V

20V1K

4K

Vout

D1 D2

Guess state for each device (multiple combinations possible)

Page 21: EE 330 Lecture 15 Devices in Semiconductor Processes

Example: Obtain VOUT

80V

20V1K

4K

Vout

D1 D2

Page 22: EE 330 Lecture 15 Devices in Semiconductor Processes

Example: Obtain VOUT

80V

20V1K

4K

Vout

D1 D2

Guess D1 and D2 on

80V

20V1K

4K

Vout

D1 D2ID1 ID2

VOUT=-20V

Valid for ID1>0 and ID2>0

2

205 0

4D

VI mA

K

1 2

8085 0

1D D

VI I mA

K

Since validates, solution is valid

Page 23: EE 330 Lecture 15 Devices in Semiconductor Processes

Use of Piecewise Models for Nonlinear

Devices when Analyzing Electronic Circuits

Process:

1. Guess state of the device

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify model (if necessary)

1. Guess state of each device (may be multiple combinations)

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify models (if necessary)

Single Nonlinear Device

Multiple Nonlinear DevicesProcess:

Analytical solutions of circuits with multiple nonlinear devices are often impossible to obtain if detailed non-piecewise nonlinear models are used

Page 24: EE 330 Lecture 15 Devices in Semiconductor Processes

Types of Diodes

Vd

Id Id

Vd

Id

VdVd

Id

Vd

Id

Vd

Id

Vd

Id

Vd

Id

pn junction diodes

Metal-semiconductor junction diodes

Signal or

Rectifier

Pin or

Photo

Light Emitting

LED

Laser Diode

Zener Varactor or

Varicap

Schottky Barrier

Vd

Id

Page 25: EE 330 Lecture 15 Devices in Semiconductor Processes

Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

Page 26: EE 330 Lecture 15 Devices in Semiconductor Processes

Capacitors

• Types

– Parallel Plate

– Fringe

– Junction

Page 27: EE 330 Lecture 15 Devices in Semiconductor Processes

Parallel Plate Capacitors

C

d

A1

A2

cond1

cond2

insulator

A = area of intersection of A1 & A2

d

AC

One (top) plate intentionally sized smaller to determine C

Page 28: EE 330 Lecture 15 Devices in Semiconductor Processes

Parallel Plate Capacitors

ACC d

d

AεC

areaunit

CapC If d

d

εCd

where

Page 29: EE 330 Lecture 15 Devices in Semiconductor Processes

Fringe Capacitors

d

C

d

AεC

A is the area where the two plates are parallel

Only a single layer is needed to make fringe capacitors

Page 30: EE 330 Lecture 15 Devices in Semiconductor Processes

Fringe Capacitors

C

Page 31: EE 330 Lecture 15 Devices in Semiconductor Processes

Capacitance

2

φV

φ

V1

ACC B

FBn

B

D

jo

for

ddepletion

region

C

Junction Capacitor

d

AC

Note: d is voltage dependent

-capacitance is voltage dependent

-usually parasitic caps

-varicaps or varactor diodes exploit

voltage dep. of C

d

p

n

VD

0.6VφB n ; 0.5

Page 32: EE 330 Lecture 15 Devices in Semiconductor Processes

Capacitance

2

φV

φ

V1

ACC B

FBn

B

D

jo

for

Junction Capacitor

0.6VφB n ; 0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

-4 -3 -2 -1 0 1

j0

C

C A

VD

Voltage dependence is substantial

VD

Page 33: EE 330 Lecture 15 Devices in Semiconductor Processes

Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

Page 34: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET

Poly

n-active

Gate oxide

p-sub

Page 35: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET

LEFF

L

W

Source

DrainGate

Bulk

Page 36: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET

Poly

n-active

Gate oxide

p-subdepletion region (electrically induced)

Page 37: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Apply small VGS

(VDS and VBS assumed to be small)ID=0

IG=0

IB=0

Depletion region electrically induced in channel

IDIG

IB

Termed “cutoff” region of operation

Page 38: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS

(VDS and VBS assumed to be small)ID=0

IG=0

IB=0Depletion region in channel becomes larger

IDIG

IB

Page 39: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

ID=0

IG=0

IB=0

IDIG

IB

Model in Cutoff Region

Page 40: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS more

IDRCH=VDS

IG=0

IB=0

Inversion layer forms in channel

IDIG

IB

(VDS and VBS small)

Inversion layer will support current flow from D to S

Channel behaves as thin-film resistor

Critical value of

VGS that creates

inversion layer

termed threshold

voltage, VT)

Page 41: EE 330 Lecture 15 Devices in Semiconductor Processes

Triode Region of Operation

OXTGS

CHCVV

1

W

LR

0II

VVVL

WμCI

BG

DSTGSOXD

For VDS small

VDS

VBS = 0

VGS

ID

IG

IB

VDSRCH

Behaves as a resistor between

drain and source

Model in Deep Triode Region

Page 42: EE 330 Lecture 15 Devices in Semiconductor Processes

Triode Region of Operation

OXTGS

CHCVV

1

W

LR

For VDS small

VBS = 0

VGS

ID

IG

IB

RCH

Resistor is controlled by the voltage VGS

Termed a “Voltage Controlled Resistor” (VCR)

Page 43: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS more

IDRCH=VDS

IG=0

IB=0

Inversion layer in channel thickens

IDIG

IB

(VDS and VBS small)

RCH will decrease

Termed “ohmic” or “triode” region of operation

Page 44: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS

ID=?

IG=0

IB=0

Inversion layer thins near drain

IDIG

IB

(VBS small)

ID no longer linearly dependent upon VDS

Still termed “ohmic” or “triode” region of operation

Page 45: EE 330 Lecture 15 Devices in Semiconductor Processes

Triode Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

OXTGS

CHCVV

1

W

LR

0II

V2

VVV

L

WμCI

BG

DSDS

TGSOXD

For VDS larger

Model in Triode Region

Page 46: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS even more

ID=?

IG=0

IB=0

Inversion layer disappears near drain

IDIG

IB

(VBS small)

Termed “saturation”region of operation

Saturation first occurs when VDS=VGS-VT

Page 47: EE 330 Lecture 15 Devices in Semiconductor Processes

Saturation Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

0II

VV2L

WμCI

VV2

VVVV

L

WμCI

V2

VVV

L

WμCI

BG

2

TGSOX

D

TGSTGS

TGSOXD

DSDS

TGSOXD

lyequivalentor

lyequivalentorFor VDS at onset of

saturation

Page 48: EE 330 Lecture 15 Devices in Semiconductor Processes

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS even more (beyond VGS-VT)

ID=?

IG=0

IB=0

Nothing much changes !!

IDIG

IB

(VBS small)

Termed “saturation”region of operation

Page 49: EE 330 Lecture 15 Devices in Semiconductor Processes

Saturation Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

0II

VV2L

WμCI

BG

2

TGSOX

D

For VDS in Saturation

Model in Saturation Region

Page 50: EE 330 Lecture 15 Devices in Semiconductor Processes

Model SummaryVDS

VBS = 0

VGS

ID

IG

IB

GS T

DSD OX GS T DS GS DS GS T

2

OX GS T GS T DS GS T

G B

0 V V

VWI μC V V V V V V V V

L 2

WμC V V V V V V V

2L

I =I =0

T

Note: This is the third model we have introduced for the MOSFET

Cutoff

Triode

Saturation

OXTGS

CHCVV

1

W

LR

(Deep triode special case of triode where VDS is small )

This is a piecewise model (not piecewise linear though)

Page 51: EE 330 Lecture 15 Devices in Semiconductor Processes

Model Summary

VDS

VBS = 0

VGS

ID

IG

IBVBS

TGSDSTGS

2

TGSOX

TGSDSGSDSDS

TGSOX

TGS

D

VVVVVVV2L

WμC

VVVVVV2

VVV

L

WμC

VV0

I T

Observations about this model (developed for VBS=0):

D 1 GS DS

G 2 GS DS

B 3 GS DS

I = f V ,V

I = f V ,V

I = f V ,V

This is a nonlinear model characterized by the functions f1, f2, and f3 where

we have assumed that the port voltages VGS and VDS are the independent

variables and the drain currents are the dependent variables

G BI = I = 0

Page 52: EE 330 Lecture 15 Devices in Semiconductor Processes

End of Lecture 15