EE 330 Lecture 10 - Iowa State University
Transcript of EE 330 Lecture 10 - Iowa State University
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EE 330
Lecture 10
IC Fabrication Technology
‒ Oxidation
‒ Epitaxy
‒ Polysilicon
‒ Planarization
‒ Contacts, Interconnect, and Metallization
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IC Fabrication Technology
• Crystal Preparation
• Masking
• Photolithographic Process
• Deposition
• Ion Implantation
• Etching
• Diffusion
• Oxidation
• Epitaxy
• Polysilicon
• Contacts, Interconnect and Metalization
• Planarization
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Oxidation
• SiO2 is widely used as an insulator– Excellent insulator properties
• Used for gate dielectric– Gate oxide layers very thin
• Used to separate devices by raising threshold voltage– termed field oxide
– field oxide layers very thick
• Methods of Oxidation– Thermal Growth (LOCOS)
• Consumes host silicon
• x units of SiO2 consumes .47x units of Si
• Undercutting of photoresist
• Compromises planar surface for thick layers
• Excellent quality
– Chemical Vapor Deposition• Needed to put SiO2 on materials other than Si
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Oxidation
SiO2
Thermally Grown SiO2 - desired growth
Photoresist
Patterned Edges
X
0.47 X
p- Silicon
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Oxidation
SiO2
Thermally Grown SiO2 - actual growth
Photoresist
Patterned Edges
Bird’s Beaking
p- Silicon
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Oxidation
Thermally Grown SiO2 - actual growth
Patterned Edges
Nonplanar
Surface
p- Silicon
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Photoresist Pad Oxide
Silicon Nitride
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Pad Oxide
Silicon Nitride
Etched Shallow
Trench
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Pad Oxide
Silicon Nitride
CVD SiO2
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
Planarity ImprovedPlanarization Target
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Oxidation
Shallow Trench Isolation (STI)
p- Silicon
After Planarization
CVD SiO2
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IC Fabrication Technology
• Crystal Preparation
• Masking
• Photolithographic Process
• Deposition
• Etching
• Diffusion
• Ion Implantation
• Oxidation
• Epitaxy
• Polysilicon
• Planarization
• Contacts, Interconnect and Metalization
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Epitaxy
• Single Crystaline Extension of Substrate
Crystal
– Commonly used in bipolar processes
– CVD techniques
– Impurities often added during growth
– Grows slowly to allow alignmnt with substrate
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Epitaxy
p- Silicon
Original Silicon Surface
Epitaxial Layer
epi can be uniformly doped or graded
Question: Why can’t a diffusion be used to create the same effect
as an epi layer ?
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IC Fabrication Technology
• Crystal Preparation
• Masking
• Photolithographic Process
• Deposition
• Etching
• Diffusion
• Ion Implantation
• Oxidation
• Epitaxy
• Polysilicon
• Planarization
• Contacts, Interconnect and Metalization
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Polysilicon
• Elemental contents identical to that of single crystaline silicon– Electrical properties much different
– If doped heavily makes good conductor
– If doped moderately makes good resistor
– Widely used for gates of MOS devices
– Widely used to form resistors
– Grows fast over non-crystaline surface
– Patterned with Photoresist/Etch process
– Silicide often used in regions where resistance must be small
• Refractory metal used to form silicide
• Designer must indicate where silicide is applied (or blocked)
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Polysilicon
Single-Crystaline Silicon
Polysilicon
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IC Fabrication Technology
• Crystal Preparation
• Masking
• Photolithographic Process
• Deposition
• Etching
• Diffusion
• Ion Implantation
• Oxidation
• Epitaxy
• Polysilicon
• Planarization
• Contacts, Interconnect and Metalization
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Planarization
• Planarization used to keep surface planar
during subsequent processing steps
– Important for creating good quality layers in
subsequent processing steps
– Mechanically planarized
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IC Fabrication Technology
• Crystal Preparation
• Masking
• Photolithographic Process
• Deposition
• Etching
• Diffusion
• Ion Implantation
• Oxidation
• Epitaxy
• Polysilicon
• Planarization
• Contacts, Interconnect and Metalization
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Contacts, Interconnect and Metalization
• Contacts usually of a fixed size
– All etches reach bottom at about the same time
– Multiple contacts widely used
– Contacts not allowed to Poly on thin oxide in
most processes
– Dog-bone often needed for minimum-length
devices
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Contacts
Vulnerable to pin holes(usually all contacts are same size)
A A’
Unacceptable Contact
B
B’
Acceptable Contact
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Contacts
Acceptable Contact
B
B’
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Contacts
2λ
1.5λ
2λ
1.5λ
Design Rule Violation
2λ
“Dog Bone” Contact
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Contacts
Common
Circuit
Connection
Standard Interconnection Buried Contact
Can save area but not
allowed in many processes
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Metalization
• Aluminum widely used for interconnect
• Copper often replacing aluminum in recent
processes
• Must not exceed maximum current density
– around 1ma/u for aluminum and copper
• Ohmic Drop must be managed
• Parasitic Capacitances must be managed
• Interconnects from high to low level metals
require connections to each level of metal
• Stacked vias permissible in some processes
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Metalization
Aluminum
• Aluminum is usually deposited uniformly over entire surface and
etched to remove unwanted aluminum
• Mask is used to define area in photoresist where aluminum is to be
removed
Copper
• Plasma etches not effective at removing copper because of absence
of volatile copper compounds
• Barrier metal layers needed to isolate silicon from migration of
copper atoms
• Damascene or Dual-Damascene processes used to pattern copper
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Patterning of Aluminum
PhotoresistContact Opening
from Mask
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Patterning of Aluminum
PhotoresistContact Opening
after SiO2 etch
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Patterning of Aluminum
PhotoresistContact Opening
after SiO2 etch
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Patterning of Aluminum
Metal Applied to Entire Surface
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Patterning of Aluminum
Photoresist Patterned
with Metal Mask
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Patterning of Aluminum
Aluminum After Metal Etch
(photoresist still showing)
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Copper Interconnects
Limitations of Aluminum Interconnects
• Electromigration
• Conductivity not real high
Relevant Key Properties of Copper
• Reduced electromigration problems at
given current level
• Better conductivity
Challenges of Copper Interconnects• Absence of volatile copper compounds
(does not etch)
• Copper diffuses into surrounding
materials (barrier metal required)
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Source:
Sept 13, 2017
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Copper Interconnects
Practical methods of realizing copper
interconnects took many years to
develop
Copper interconnects widely used in
some processes today
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Patterning of Copper
PhotoresistContact Opening
after SiO2 etch
Damascene Process
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Patterning of Copper
Tungsten (W)
Damascene Process
CMP Target
W has excellent conformality when formed from WF6
Applied with CVD WF6+3H2 →W+6HF
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Chemical-Mechanical Planarization (CMP)
http://en.wikipedia.org/wiki/Chemical-mechanical_planarizationAcknowledgement:
• Polishing Pad and Wafer Rotate in
non-concentric pattern to thin, polish,
and planarize surface
• Abrasive/Chemical polishing
• Depth and planarity are critical
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Patterning of Copper
W-plug
Damascene Process
CMP TargetAfter first CMP Step
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Patterning of CopperDamascene Process
Oxidation
After first CMP Step
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Patterning of CopperDamascene Process
Photoresist Patterned with
Metal Mask Defines Trench
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Patterning of CopperDamascene Process
Shallow Trench after Etch
W-plug
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Patterning of CopperDamascene Process
(Barrier metal added before copper to contain the copper atoms)
Barrier
Metal
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Patterning of CopperDamascene Process
Copper DepositionW-plug
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Patterning of CopperDamascene Process
Copper DepositionW-plug
CMP Target
Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)
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Patterning of CopperDamascene Process
After Second CMP Step
W-plug
CMP Target
Copper
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Patterning of Copper
PhotoresistShallow Trench Defined
in PR with Metal Mask
Dual-Damascene Process
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Patterning of Copper
PhotoresistShallow Trench After Etch
Dual-Damascene Process
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Patterning of Copper
PhotoresistVia Defined in PR
with Via Mask
Dual-Damascene Process
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Patterning of Copper
PhotoresistVia Etch Defines
Contact Region
Dual-Damascene Process
(Barrier Metal added before copper but not shown)
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Patterning of Copper
Copper Deposited on Surface
Dual-Damascene Process
Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)
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Patterning of Copper
Copper Deposited on Surface
Dual-Damascene Process
CMP Target
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Patterning of Copper
Copper Interconnect
Dual-Damascene Process
CMP Target
Copper Via
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Patterning of Copper
Dual-Damascene Process
Both Damascene Processes Realize Same Structure
Damascene ProcessTwo Dielectric Deposition Steps
Two CMP Steps
Two Metal Deposition Steps
Two Dielectric Etches
W-Plug
One Dielectric Deposition Steps
One CMP Steps
One Metal Deposition Steps
Two Dielectric Etches
Via formed with metal step
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Multiple Level Interconnects
3-rd level metal connection to n-active without stacked vias
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Multiple Level Interconnects
3-rd level metal connection to n-active with stacked vias
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Metalization
Interconnect Layers May Vary in Thickness or Be Mostly Uniform
12.5μ
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Interconnects
• Metal is preferred interconnect
– Because conductivity is high
• Parasitic capacitances and resistances of concern in all interconnects
• Polysilicon used for short interconnects
– Silicided to reduce resistance
– Unsilicided when used as resistors
• Diffusion used for short interconnects
– Parasitic capacitances are high
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Interconnects
• Metal is preferred interconnect
– Because conductivity is high
• Parasitic capacitances and resistances of concern in all interconnects
• Polysilicon used for short interconnects
– Silicided to reduce resistance
– Unsilicided when used as resistors
• Diffusion used for short interconnects
– Parasitic capacitances are high
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Resistance in Interconnects
L
W
H
A
B
BA
R
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Resistance in Interconnects
L
W
HA
B
BD
R
D
ρA
LR
A=HW
ρ independent of geometry and
characteristic of the process
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Resistance in Interconnects
L
W
HA
B
D
H
ρ
W
Lρ
A
LR
H << W and H << L in most processes
Interconnect behaves as a “thin” film
Sheet resistance often used instead of conductivity to characterize film
R□=ρ/H R=R□[L / W]
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Resistance in Interconnects
R=R□[L / W]
L
W
The “Number of Squares” approach to resistance determination in thin films
1 2 3 21NS = 21
L / W=21
R=R□NS
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Resistance in Interconnects
R=R□13.25
Corners Contribute
about .55 Squares
Fractional Squares
Can Be Represented
By Their Fraction
In this example:
NS=12+.55+.7=13.25
The “squares” approach is not exact but is good enough for
calculating resistance in almost all applications
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Example:
The layout of a film resistor with electrodes A and B is shown. If
the sheet resistance of the film is 40 Ω/□, determine the
resistance between nodes A and B.
10u
3u1u
A
B
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10u
3u1u
A
B
Solution
NS =9+9+3+2(.55)=22.1
RAB=R□NS=40x22.1=884Ω
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Resistance in Interconnects(can be used to build resistors!)
• Serpentine often used when large resistance required
• Polysilicon or diffusion often used for resistor creation
• Effective at managing the aspect ratio of large resistors
• May include hundreds or even thousands of squares
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Resistance in Interconnects(can be used to build resistors!)
d1
2d
2
Area requirements determined by both minimum
width and minimum spacing design rules
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End of Lecture 10