EE 330Lecture 12

Devices in Semiconductor Processes

• Diodes

Guest Lecture:

Joshua AbbottNon Volatile Product EngineerMicron Technology

NAND Memory: Operation, Testing and Challenges

Intro to Flash Memory Design

Josh Abbott (ISU BSEE’14)

NVE Product Engineering | Micron Technology

EE330 –Iowa State University | 9/21/2015

September 23, 2016

Agenda

o Types of Memory o Flash Memory Cells o Program, Erase, Read Operationso 2D to 3D NAND o Basic Device Physicso Technical Issues with 3D NAND

o

o

September 23, 2016

Micron’s Core Memory Technologies

September 23, 2016

Volatile Non-Volatile

DRAM NAND

Flash

NOR

Flash

Types of Semiconductor Memory

• Volatile – loses data when power is removed (within milliseconds)

• Non-volatile – retains data when power is removed (for years)

DRAM

NAND

Package Technology

New Memory Technology

Leading-Edge Technology Status

Images are not to scale

Hybrid Memory Cube

1Xnm DRAM

3D NAND

3D X-point

September 23, 2016

Flash Memory Cell

• Single FET with dual gate

• Electrically isolated floating gate is the storage element

• Electrons added to or removed from the floating gate shift the Vt of the cell to store a 1 or a 0

• Two types: NAND and NOR

• NAND – Better array efficiency, lower cost per die for mass-storage

• NOR – Faster read/write speeds for code storage and execution

NAND vs NOR – Physical Comparison

SourceDrainDrain

Gate

DrainSource

NOR

Parallel layout

NAND

Serial layout

Basic NAND Flash Operation• The operation of the NAND Flash cell depends on two

basic electrical concepts:

– Capacitive division

– Fowler-Nordheim tunneling

Capacitive Division

• If you have capacitors in series, a voltage applied to one node will be distributed across the intermediate nodes• V2 = V1 * C1 / (C1+C2)

Fowler-Nordheim Tunneling• By setting up a large potential difference across an insulator, you

can decrease the effective width of the energy barrier, and increase the probability that an electron will tunnel through the insulator.

SemiconductorInsulator

Semiconductor

eee

e

e

eee e

- +

NAND Flash Operation – Program

• Store a 0 to a cell

– Inject electrons onto floating gate through F-N tunneling

Control gate

Floating gate

N+ N+

p-well

N-well

p-sub

Floating 0V

20V

0V 0V

Program ‘0’

NAND Flash Operation – Erase

• Store a 1 to a cell

– Remove electrons from the floating gate through F-N tunneling

Control gate

e- e- e- e- e- e-

N+ N+

p-well

N-well

p-sub

Floating Floating

0V

0V 20V

Erase

Floating

Gate

Bitline

Rowline

VRead

To read the cell, apply a voltage (VRead) to the rowline

(VT > VRead) => No current, logic ‘0’

(VT < VRead) => Current, logic ‘1’

• By storing electrons on the floating gate, we can change the effective threshold voltage (VT)

• FET conducts current if VGS > VT

NAND Flash Operation – Read

NAND Read Operation

3V

1V

2V

-3V

-1V

-2

0V

5V

“1”“0”

5V

5V

5V

5V

5V

5V

SGD

SGS

Vc

c

WL

WL

WL

WL

WL

WL

1. Precharge bitline and unselected wordlines

3. Sense current

2. Drive selected wordline and connect stringto bitline

Vt Distributions

• Single-Level Cell (SLC)

• Multi-Level Cell (MLC)

Num

berof B

its

Num

berof

Bits

‘1’ ‘0’

’11’ ’10’’00’‘LP’’01’

Can be extended further to 3 bits per cell (TLC) with 8 distinct states

The NAND String

• Notice that it has n doping on the source and drain that is repeated across a horizontal plane.

September 23, 2016

| Micron Confidential

Moving to 3D NAND – Change to the Channel• Elimination of Pwell/Atub• Loss of LDD (Lightly Doped Drain) – Pillar

• Vertical Stacking of Cell’s

• Device Physics Change

September 23, 2016

1. With n- LDD (2D)

2. No LDD, P-type channel

3. No LDD, N-type thin channel

n np

n

p

Low Vt-ldd

Low Vt-ldd

High Vt-ldd

Si Substrate

Ch

ann

el \

‘Pillar’

Si Substrate (Pwell/Atub)

Si Substrate

Ch

ann

el \

‘Pillar’

How does the Channel Conduct with No LDD?

September 23, 20162

1| Micron Confidential

With All E fields the channel can be formed in the pillar and thus conduct effectively.

Fringe Fields allow for E Field to activate area

between cells.

Si Substrate

Ch

ann

el \

‘Pillar’

Challenges with the Channel – Erase Verify Example

September 23, 20162

2| Micron Confidential

Fringe Fields are to weak to

create channel in the space

between Cells.

AKA, my Space Vt is too

high to activate with 1V.

The result is a non-

conductive channel even

though my Vt’s of my cell’s

are lower than the Gate

Voltage.

Assume the cell is erased

What goes into designing a Flash memory chip?

• Core memory array

September 23, 2016

• Lots of other circuitry:

Sense amplifiers and digital registers to read and store the contents of the memory array

Command and address decoders to select which location to read/write, and which operation to perform

Bandgap reference to generate a voltage reference that is stable across temperature and supply voltage

Charge pumps to generate voltages above or below the supply voltages for the chip

Voltage regulators to regulate the precise voltages required to read/write the array

Thermometer to adjust voltages as needed vs. temperature

DACs and ADCs for converting internal signals between analog and digital domains

Current sources/mirrors to be used for providing reference currents to key circuits throughout the chip

Microcontroller and digital control logic to control the read/write algorithms for the array

I/O drivers for communicating with the outside world

High speed datapath for sending data back and forth between the Chip I/Os and memory array

©2009 Micron Technology, Inc. | 24

Questions?

September 23, 2016

http://www.dayah.com/periodic/Images/periodic%20table.png

Review from Last Lecture

Review from Last Lecture

B (Boron) widely used a dopant for creating p-type regions

P (Phosphorus) widely used a dopant for creating n-type regions(bulk doping, diffuses fast)

As (Arsenic) widely used a dopant for creating n-type regions(Active region doping, diffuses slower)

Silicon Dopants in Semiconductor Processes

Review from Last Lecture

Diodes (pn junctions)

Depletion region created that is ionized but void of carriers

pn Junctions

Physical Boundary

Separating n-type and

p-type regions

If doping levels identical, depletion region extends

equally into n-type and p-type regions

pn Junctions

Physical Boundary

Separating n-type and

p-type regions

Extends farther into p-type region if p-doping lower

than n-doping

pn Junctions

Physical Boundary

Separating n-type and

p-type regions

Extends farther into n-type region if n-doping lower

than p-doping

pn Junctions

VD

ID

• Positive voltages across the p to n junction are referred to forward bias

• As forward bias increases, depletion region thins and current starts to flow

• Current grows very rapidly as forward bias increases

• Current is very small under revere bias

• Negative voltages across the p to n junction are referred to reverse bias

pn Junctions

ID

VD

Anode

Cathode

Anode

CathodeCircuit Symbol

pn Junctions

• As forward bias increases, depletion region thins and current starts to flow

• Current grows very rapidly as forward bias increases

ID

VD

Anode

Cathode

Simple Diode Model:

D D

D D

V =0 I >0

I =0 V

pn JunctionsID

VD

Simple Diode Model:

VD

ID

pn junction serves as a rectifier passing current in one direction and blocking it

In the other direction

Rectifier Application: Simple Diode Model:

VD

ID

1K

VOUT

D1

VIN=VMsinωt

VIN

VM

t

VM

t

VIN

VOUT

I-V characteristics of pn junction(signal or rectifier diode)

Vd

Id

1eII t

d

V

V

SD

Diode Equation

Improved Diode Model:

IS in the 10fA to 100fA range

What is Vt at room temp?

t

kTV =

q

k= 1.380 6504(24) × 10−23JK-1

q = −1.602176487(40)×10−19 C

k/q=8.62× 10−5 VK-1

Vt is about 26mV at room temp

Diode equation due to William

Schockley, inventor of BJT

In 1919, William Henry Eccles

coined the term diode

In 1940, Russell Ohl “stumbled

upon” the p-n junction diode

http://en.wikipedia.org/wiki/William_Henry_Eccles

I-V characteristics of pn junction(signal or rectifier diode)

Vd

Id

SD II

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

1eII t

d

V

V

SDDiode Equation

Under reverse bias (Vd0), t

d

V

V

SD eII

Diode Equation or forward bias simplification is unwieldy to work with analytically

Improved Diode Model:

Simplification of Diode Equation:

Simplification essentially identical model except for Vd very close to 0

IS in the 10fA to 100fA range

Vt is about 26mV at room temp

t

kTV =

q

k= 1.380 6504(24) × 10−23JK-1

q = −1.602176487(40)×10−19 C

k/q=8.62× 10−5 VK-1

I-V characteristics of pn junction(signal or rectifier diode)

SD II

1eII t

d

V

V

SDDiode Equation

Under reverse bias,

Under forward bias, td

V

V

SD eII

Improved Diode Model:

Simplification of Diode Equation:

IS often in the 10fA to 100fA range

Vt is about 26mV at room temp

How much error is introduced using the simplification for Vd > 0.5V?

9

0 5

026

14 4 10

.

.

.

e

How much error is introduced using the simplification for Vd < - 0.5V? 0 5

9026 4 4 10.

. .e

Simplification almost never introduces any significant error

1eI

eI1eI

t

d

t

d

t

d

V

V

S

V

V

S

V

V

S

IS proportional to junction area

Will you impress your colleagues or your boss if you use the more exact diode equation when Vd < -0.5V or Vd > +0.5V ?

Will your colleagues or your boss be unimpressed if you use the more exact diode equation when Vd < -0.5V or Vd > +0.5V ?

pn Junctions

VI

0V0

0VAeJITnV

V

S

I

V

Diode Equation:(good enough for most applications)

JS= Sat Current Density (in the 1aA/u2 to 1fA/u2 range)

A= Junction Cross Section Area

VT=kT/q (k/q=1.381x10-23V•C/°K/1.6x10-19C=8.62x10-5V/°K)

n is approximately 1

Anode

Cathode

Note: IS=JsA

pn Junctions

0V0

0VAeJITnV

V

S I

V

Diode Equation:Anode

CathodeJS is strongly temperature dependent

G0 D

t t

-V V

V Vm

SXI(T) J T e Ae

With n=1, for V>0,

Typical values for key parameters: JSX=0.5A/μ2, VG0=1.17V, m=2.3

pn JunctionsI

VG0 D

t t

-V V

V Vm

SXI(T) J T e Ae

What percent change in IS will occur for a 1°C change in temperature

at room temperature?

Example:

G0 G0G0 G0 G0D

t 1 t 1t 2 t t 2 t 2

@ 1 2 1

G0 G0G0

t 1 t 1t 2

1 1

-V -V-V -V -VV

V T V TV (T ) V V (T ) V (T )m m m m

SX T SX T T T

S

-V -V-V

V T V TV (T )m m

SX T T

J T e Ae - J T e Ae T e - T eI

J T e Ae T eS

I

15 15

15

1 240 10 1 025 10100 21

1 025 10S

x x

I x

S

. - .I% %

.

End of Lecture 12