8/29/06 and 8/31/06 ELEC5270-001/6270-001 Lecture 3 1 ELEC 5270-001/6270-001 (Fall 2006) Low-Power...

8/29/06 and 8/31/068/29/06 and 8/31/06 ELEC5270-001/6270-001 Lecture 3ELEC5270-001/6270-001 Lecture 3 11

ELEC 5270-001/6270-001 (Fall 2006)ELEC 5270-001/6270-001 (Fall 2006)Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits

(ELEC 5970/6970)(ELEC 5970/6970)

Low Voltage Low Power Devices Low Voltage Low Power Devices

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering

Auburn UniversityAuburn Universityhttp://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal

[email protected]@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal

mailto:[email protected]


CapacitancesCapacitances

In Out

C1

C2

VDD

GND

CW


Miller CapacitanceMiller Capacitance

In Out

C1

C2

VDD

GND

CW

CM


Before TransitionBefore Transition

In Out

C1

C2

VDD

GND

CW

CM

0 +VDD


After TransitionAfter Transition

In Out

C1

C2

VDD

GND

CW

CM

0-VDD

Energy from supply = 2 CM VDD

2

Effective capacitance = 2 CM

from pullupdevices ofprevious gate


Capacitances in MOSFETCapacitances in MOSFET

Source Drain

Gate oxide

Gate

BulkCs Cd

Cg

CgdCgs


Bulk nMOSFETBulk nMOSFET

n+

p-type body (bulk)

n+

L

W

SiO2

Thickness = tox

Gate

SourceDrain

Polysilicon


Gate CapacitanceGate CapacitanceCg = Cox WL = C0, intrinsic cap.

Cg = Cpermicron W

εoxCpermicron = Cox L= ── L

tox

where εox = 3.9ε0 for Silicon dioxide

= 3.9×8.85×10-14 F/cm


Intrinsic CapacitancesIntrinsic Capacitances

CapacitanceCapacitanceRegion of operationRegion of operation

CutoffCutoff LinearLinear SaturatioSaturationn

CgbCgb CC00 00 00

CgsCgs 00 CC0 0 /2/2 2/32/3 C C00

CgdCgd 00 CC0 0 /2/2 00

Cg = Cg = Cgs+Cgd+CgbCgs+Cgd+Cgb

CC00 CC00 2/3 2/3 CC00

Weste and Harris, CMOS VLSI Design, Addison-Wesley, 2005, p. 78.


Low-Power TransistorsLow-Power Transistors

Device scaling to reduce capacitance Device scaling to reduce capacitance and voltage.and voltage.

Body bias to reduce threshold Body bias to reduce threshold voltage and leakage.voltage and leakage.

Multiple threshold CMOS (MTCMOS).Multiple threshold CMOS (MTCMOS). Silicon on insulator (SOI)Silicon on insulator (SOI)


Device ScalingDevice Scaling

Reduced dimensionsReduced dimensions Reduce supply voltageReduce supply voltage Reduce capacitancesReduce capacitances Reduce delayReduce delay Increase leakage due to reduced Increase leakage due to reduced VVDD DD / V/ Vthth


A Simplistic ViewA Simplistic View

Assume:Assume: Dynamic power dominatesDynamic power dominates Power reduces as square of supply voltage; Power reduces as square of supply voltage;

should reduce with device scalingshould reduce with device scaling Power reduced linearly with capacitance; Power reduced linearly with capacitance;

should reduce with device scalingshould reduce with device scaling Delay is proportional to Delay is proportional to RCRC time constant; time constant; RR

is constant with scaling, is constant with scaling, RCRC should reduce should reduce

Power reduces with scalingPower reduces with scaling


Simplistic View (Continued)Simplistic View (Continued) What if voltage is further reduced What if voltage is further reduced

below the constant electric field value?below the constant electric field value? Will power continue to reduce? Yes.Will power continue to reduce? Yes. Since RC is independent of voltage, can clock Since RC is independent of voltage, can clock

rate remain unchanged?rate remain unchanged?

Answer to last question:Answer to last question: Yes, if threshold voltage was zero.Yes, if threshold voltage was zero. No, in reality. Because No, in reality. Because higher threshold voltagehigher threshold voltage

will delay the beginning of capacitor will delay the beginning of capacitor charging/discharging.charging/discharging.


Consider Delay of InverterConsider Delay of Inverter

In Out

VDD

GND

C

R

t B t B

Charging ofC begins


Idealized Input and OutputIdealized Input and Output t f

Vth

t B

0.5VDD

VDD

time0.69CR

INPU

TO

UTPU

T

Gate delay

t B = t f Vth /VDD

0.5VDD


Gate DelayGate Delay

For VDD >Vth

Gate delay = (t fVth/VDD) + 0.69RC – 0.5 t

f

= t f (Vth/VDD – 0.5 ) + 0.69RC

For VDD ≤Vth

Gate delay = ∞


Approx. Gate Delay vs. Approx. Gate Delay vs. VVDDDD

0.69RC

0.5t f

0.5t f

0 1 2 3 4 5

Gate

dela

y

VDD /Vth


Power - Delay vs. Power - Delay vs. VVDDDD

0.69RC

0.5t f

0.5t f

0 1 2 3 4 5

Gate

dela

y

VDD /Vth

Pow

er

With leakage


Optimum Threshold VoltageOptimum Threshold Voltage

VDD / Vth

0 1 2 3 4 5 6

Delay orEnergy-delayproduct

Delay

Energy-delay product

Vth = 0.7V

Vth = 0.3V


Bulk nMOSFETBulk nMOSFET

n+

p-type body (bulk)

n+

L

W

SiO2

Thickness = tox

Gate

Source Drain

Polysilicon

Vgs Vgd


Transistor in Cut-Off StateTransistor in Cut-Off State

+- Vg < 0

- - - - - - - - - - - - - - - - - -

+ + + + + + + + + + + + + + + + + + + + + + + + + +

+ + + + + + + + + + + + +

Polysilicon gateSiO2

p-type body


Threshold Voltage, Threshold Voltage, VVthth

+-0 < Vg < Vth

+ + + + + + + + + +

+ + + + + + + + + + + + +

+ + + + + + + + + + + + +

Depletion region


p-type body

+-Vg > Vth

+ + + + + + + + + + + + +

- - - - - - - - - - - - - - - - - - -Depletion region

+ + + + + + + + + + + + ++ + + + + + + + + + + + +


p-type body

Vth is a function of:Dopant concentration,Thickness of oxide


αα-Power Law Model-Power Law ModelVgs > Vth and Vds > Vdsat = Vgs – Vth (Saturation region):

βIds = Pc ─ (Vgs – Vth)α

2

where β = μCoxW/L, μ = mobility

For fully ON transistor, Vgs = Vds = VDD:

βIdsat = Pc ─ (VDD – Vth)α

2

T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,”IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990.


αα-Power Law Model (Cont.)-Power Law Model (Cont.)

Vgs = 1.8V

Shockley

α-power law

Simulation

Vds

I ds

(μA

)

0 0.3 0.6 0.9 1.2 1.5 1.8

400

300

200

100

0

Idsat



0 Vgs < Vth cutoff

Ids = Idsat×Vds/Vdsat Vds < Vdsat linear

Idsat Vds > Vdsat saturation

Vdsat = Pv (Vgs – Vth)α/2



αα = 2, for long channel devices or low = 2, for long channel devices or low VVDDDD

αα ~ ~ 1, for short channel devices1, for short channel devices


Power and DelayPower and Delay

Power = CVDD2

CVDD 1 1Inverter delay = ──── (─── + ─── )

4 Idsatn Idsatp

KVDD= ───────

(VDD – Vth)α


Power-Delay ProductPower-Delay Product VDD

3

Power × Delay = constant × ─────── (VDD – Vth)α

0.6V 1.8V 3.0V VDD

Power

Delay


Optimum Threshold VoltageOptimum Threshold Voltage

For minimum power-delay product:

3VthVDD = ───

3 – α

For long channel devices, α = 2, VDD = 3Vth

For very short channel devices, α = 1, VDD = 1.5Vth


LeakageLeakage

IG

ID

Isub

IPT

IGIDL

n+ n+

GroundVDD

R


Leakage Current Leakage Current ComponentsComponents

Subthreshold conduction, Subthreshold conduction, IIsubsub

Reverse bias pn junction conduction, Reverse bias pn junction conduction, IIDD Gate induced drain leakage, Gate induced drain leakage, IIGIDLGIDL due to due to

tunneling at the gate-drain overlaptunneling at the gate-drain overlap Drain source punchthrough, Drain source punchthrough, IIPTPT due to due to

short channel and high drain-source short channel and high drain-source voltagevoltage

Gate tunneling, Gate tunneling, IIGG through thin oxidethrough thin oxide


Subthreshold LeakageSubthreshold LeakageVgs – Vth

Isub = I0 exp( ───── ) nvth

0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs

Ids

1mA100μA10μA1μA

100nA10nA1nA

100pA10pA

Vth

Sub

thre

shol

dre

gion

Saturation region


Normal CMOS InverterNormal CMOS Inverter

Polysilicon (input)SiO2

p+ n+ n+ p+ p+ n+

n-well p-substrate (bulk)

metal 1VDDGND output

input output

VDD

GND

o


Leakage Reduction by Body Leakage Reduction by Body BiasBias

Polysilicon (input)SiO2

p+ n+ n+ p+ p+ n+

n-well p-substrate (bulk)

metal 1VDDGND output

input output

VBBp

VDD

GNDVBBn

VBBn VBBp

o


Body Bias, Body Bias, VVBBnBBn

+-0 < Vg < Vth

+ + + + + + + + + +

+ + + + + + + + + + + + +

+ + + + + + + + + + + + +

Depletion region


p-type body

+-Vg < 0

- - - - - - - - - - - - - - - - - - + + + + + + + + + + + + ++ + + + + + + + + + + + ++ + + + + + + + + + + + ++ + + + + + + + + + + + +


p-type body

Vt is a function of:Dopant concentration,Thickness of oxide


Further on Body BiasFurther on Body Bias

Large body bias can increase gate Large body bias can increase gate leakage (leakage (IIGG) via tunneling through ) via tunneling through oxide.oxide.

Body bias is kept less than 0.5V.Body bias is kept less than 0.5V. For For VVDDDD = 1.8V = 1.8V

VVBBnBBn = - 0.4V = - 0.4V VVBBpBBp = 2.2V = 2.2V


SummarySummary Device scaling down reduces supply Device scaling down reduces supply

voltagevoltage Reduced powerReduced power Increases delayIncreases delay

Optimum power-delay product by Optimum power-delay product by scaling down threshold voltagescaling down threshold voltage

Threshold voltage reduction increases Threshold voltage reduction increases subthreshold leakage powersubthreshold leakage power

Use body bias to reduce subthreshold leakageUse body bias to reduce subthreshold leakage Body bias may increase gate leakageBody bias may increase gate leakage

8/29/06 and 8/31/06 ELEC5270-001/6270-001 Lecture 3 1 ELEC 5270-001/6270-001 (Fall 2006) Low-Power...

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Transcript of 8/29/06 and 8/31/06 ELEC5270-001/6270-001 Lecture 3 1 ELEC 5270-001/6270-001 (Fall 2006) Low-Power...