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Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 11
ELEC 5270-001/6270-001 Spring 2009ELEC 5270-001/6270-001 Spring 2009Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Power Dissipation of CMOS CircuitsPower Dissipation of CMOS Circuits
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr09/course.html
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 22
nMOS Logic (Inverters)nMOS Logic (Inverters)
Saturated-load nMOS Pseudo-nMOS
For logic 1 input, continuous static power is dissipated.
R. C. Jaeger and T. N. Blalock, Microelctronic Circuit Design, Third Edition, McGraw-Hill, 2006, Chapter 6.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 33
CMOS Logic (Inverter)CMOS Logic (Inverter)
F. M. Wanlass and C. T. Sah, “Mamowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid-State Circuits Conference Digest, vol. IV, February 1963, pp. 32-33.
No static leakage path exists for either 1 or 0 input.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 44
Components of PowerComponents of Power
DynamicDynamicSignal transitionsSignal transitions
Logic activityLogic activityGlitchesGlitches
Short-circuitShort-circuitStaticStatic
LeakageLeakagePtotal = Pdyn + Pstat
= Ptran + Psc + Pstat
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 55
Power of a Transition: Power of a Transition: PPtrantran
VVDDDD
GroundGround
CL
Ron
R = large
vi (t) vo(t) ic(t)
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 66
Charging of a CapacitorCharging of a Capacitor
V C
R
i(t) v(t)
Charge on capacitor, q(t) = C v(t)
Current, i(t) = dq(t)/dt = C dv(t)/dt
t = 0
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 77
i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC
dv(t) dt∫ ───── = ∫ ──── V – v(t) RC
- t ln [V – v(t)] = ── + A
RC
Initial condition, t = 0, v(t) = 0 → A = ln V - t
v(t) = V [1 – exp(───)]
RC
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 88
- t v(t) = V [1 – exp( ── )]
RC
dv(t) V - ti(t) = C ─── = ── exp( ── )
dt R RC
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 99
Total Energy Per Charging Total Energy Per Charging Transition from Power SupplyTransition from Power Supply
∞ ∞ V2 - tEtrans = ∫ V i(t) dt = ∫ ── exp( ── ) dt
0 0 R RC
= CV2
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1010
Energy Dissipated per Transition in Energy Dissipated per Transition in ResistanceResistance
∞ V2 ∞ -2tR ∫ i2(t) dt = R ── ∫ exp( ── ) dt 0 R2 0 RC
1= ─ CV2
2
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1111
Energy Stored in Charged Energy Stored in Charged Capacitor Capacitor
∞ ∞ - t V - t∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt0 0 RC R RC
1 = ─ CV2
2
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1212
Transition PowerTransition PowerGate output rising transitionGate output rising transition
Energy dissipated in pMOS transistor = Energy dissipated in pMOS transistor = CVCV22/2/2Energy stored in capacitor = Energy stored in capacitor = CVCV22/2/2
Gate output falling transitionGate output falling transitionEnergy dissipated in nMOS transistor = Energy dissipated in nMOS transistor = CVCV22/2/2
Energy dissipated per transition = Energy dissipated per transition = CVCV22/2/2Power dissipation:Power dissipation:
Ptrans = Etrans α fck = α fck CV2/2 α = activity factor
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1313
Components of PowerComponents of Power
DynamicDynamicSignal transitionsSignal transitions
Logic activityLogic activityGlitchesGlitches
Short-circuitShort-circuitStaticStatic
LeakageLeakagePtotal = Pdyn + Pstat
= Ptran + Psc + Pstat
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1414
Short Circuit Power of a Transition: Short Circuit Power of a Transition: PPscsc
VVDDDD
GroundGround
CL
vi (t) vo(t) isc(t)
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1515
Short Circuit Current, Short Circuit Current, iisc sc ((tt))
Time (ns)0 1
Isc
Volt
VDD
isc(t)
0
Vi (t)Vo(t)
VDD - VTp
VTn
tB tE
Iscmaxf
p-transistor starts conducting
n-transistor cuts-off
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1616
Peak Short Circuit CurrentPeak Short Circuit Current
Increases with the size (or gain, Increases with the size (or gain, ββ) of ) of transistorstransistors
Decreases with load capacitance, Decreases with load capacitance, CCLL
Largest when Largest when CCL L = 0= 0 Reference: M. A. Ortega and J. Figueras, Reference: M. A. Ortega and J. Figueras,
“Short Circuit Power Modeling in Submicron “Short Circuit Power Modeling in Submicron CMOS,” CMOS,” PATMOS PATMOS ’96, Aug. 1996, pp. 147-’96, Aug. 1996, pp. 147-166.166.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1717
Short-Circuit Energy per TransitionShort-Circuit Energy per Transition
EEscf scf == ∫∫tBtB
ttE E VVDDDD i iscsc((tt))dt dt
== ((ttEE – t – tBB)) I Iscmaxf scmaxf VVDD DD / / 22
EEscfscf == ttff ((VVDD DD - - ||VVTpTp|| - V- VTnTn)) I Iscmaxf scmaxf / / 22
EEscrscr == ttrr ((VVDD DD - - ||VVTpTp|| - V - VTnTn)) I Iscmaxr scmaxr / / 22
EEscfscf = = EEscrscr == 0,0, when V when VDDDD = |= |VVTpTp|| ++ V VTnTn
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1818
Short-Circuit EnergyShort-Circuit Energy
Increases with rise and fall times of inputIncreases with rise and fall times of inputDecreases for larger output load Decreases for larger output load
capacitancecapacitanceDecreases and eventually becomes zero Decreases and eventually becomes zero
when when VVDDDD is scaled down but the threshold is scaled down but the threshold
voltages are not scaled downvoltages are not scaled down
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 1919
Short-Circuit Power CalculationShort-Circuit Power Calculation
Assume equal rise and fall timesAssume equal rise and fall timesModel input-output capacitive coupling Model input-output capacitive coupling
(Miller capacitance)(Miller capacitance)Use a spice model for transistorsUse a spice model for transistors
T. Sakurai and A. Newton, “Alpha-power Law T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a MOSFET model and Its Application to a CMOS Inverter,” CMOS Inverter,” IEEE J. Solid State CircuitsIEEE J. Solid State Circuits, , vol. 25, April 1990, pp. 584-594.vol. 25, April 1990, pp. 584-594.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2020
Short Circuit PowerShort Circuit Power
Psc = α fck Esc
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2121
PPscsc, Rise Time and Capacitance, Rise Time and Capacitance
VVDDDD
GroundGround
CL
Ron
R = large
vi (t) vo(t) ic(t)+isc(t)
tftr vo(t)───
R↑
vo(t)
VVDDDD
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2222
iiscsc, Rise Time and Capacitance, Rise Time and Capacitance
-tVDD[1- exp(─────)]
vo(t) R↓(t) CIsc(t) = ──── = ──────────────
R↑(t) R↑(t)
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2323
iiscmaxscmax, Rise Time and Capacitance, Rise Time and Capacitance
Small C Large C
tf
1────R↑(t)
iscmax
vo(t) vo(t)
i
t
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2424
PPscsc, Rise Times, Capacitance, Rise Times, CapacitanceFor given input rise and fall times short For given input rise and fall times short
circuit power decreases as output circuit power decreases as output capacitance increases.capacitance increases.
Short circuit power increases with increase Short circuit power increases with increase of input rise and fall times.of input rise and fall times.
Short circuit power is reduced if output rise Short circuit power is reduced if output rise and fall times are smaller than the input and fall times are smaller than the input rise and fall times.rise and fall times.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2525
Summary: Short-Circuit PowerSummary: Short-Circuit Power Short-circuit power is consumed by each Short-circuit power is consumed by each
transition (increases with input transition time).transition (increases with input transition time). Reduction requires that gate output transition Reduction requires that gate output transition
should not be faster than the input transition should not be faster than the input transition (faster gates can consume more short-circuit (faster gates can consume more short-circuit power).power).
Increasing the output load capacitance reduces Increasing the output load capacitance reduces short-circuit power.short-circuit power.
Scaling down of supply voltage with respect to Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; threshold voltages reduces short-circuit power; completely eliminated when completely eliminated when VVDD DD ≤ |≤ |VVtptp| + | + VVtntn . .
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2626
Components of PowerComponents of Power
DynamicDynamicSignal transitionsSignal transitions
Logic activityLogic activityGlitchesGlitches
Short-circuitShort-circuitStaticStatic
LeakageLeakage
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2727
Leakage PowerLeakage Power
IG
ID
Isub
IPT
IGIDL
n+ n+
GroundVDD
RDrainSource
Gate
Bulk Si (p)
nMOS Transistor
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2828
Leakage Current ComponentsLeakage Current Components Subthreshold conduction, Subthreshold conduction, IIsubsub
Reverse bias pn junction conduction, Reverse bias pn junction conduction, IIDD
Gate induced drain leakage, Gate induced drain leakage, IIGIDLGIDL due to due to
tunneling at the gate-drain overlaptunneling at the gate-drain overlap Drain source punchthrough, Drain source punchthrough, IIPTPT due to short due to short
channel and high drain-source voltagechannel and high drain-source voltage Gate tunneling, Gate tunneling, IIGG through thin oxide; through thin oxide; may may
become significant with scalingbecome significant with scaling
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 2929
Subthreshold CurrentSubthreshold Current
Isub = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel lengthW: gate widthVt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3030
IIDSDS for Short Channel Devicefor Short Channel Device
Isub= μ0 Cox(W/L)Vt2 exp{(VGS –VTH + ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3131
Increased Subthreshold LeakageIncreased Subthreshold Leakage
0 VTH’ VTH
Log
(Dra
in c
urre
nt)
Gate voltage
Scaled device
Ic
Isub
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3232
Summary: Leakage PowerSummary: Leakage Power Leakage power as a fraction of the total power Leakage power as a fraction of the total power
increases as clock frequency drops. increases as clock frequency drops. Turning Turning supply off in unused parts can save powersupply off in unused parts can save power ..
For a gate it is a small fraction of the total power; For a gate it is a small fraction of the total power; it can be significant for very large circuits.it can be significant for very large circuits.
Scaling down features requires lowering the Scaling down features requires lowering the threshold voltage, which increases leakage threshold voltage, which increases leakage power; roughly doubles with each shrinking.power; roughly doubles with each shrinking.
Multiple-threshold devices are used to reduce Multiple-threshold devices are used to reduce leakage power.leakage power.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3333
Technology ScalingTechnology Scaling
Scaling down 0.7 micron by factors 2 and Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron 4 leads to 0.35 and 0.17 micron technologiestechnologies
Constant electric field assumedConstant electric field assumed
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3434
Constant Electric Field ScalingConstant Electric Field Scaling
B. Davari, R. H. Dennard and G. G. B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Performance and Low Power—The Next Ten Years,” Ten Years,” Proc. IEEEProc. IEEE, April 1995, pp. , April 1995, pp. 595-606.595-606.
Other forms of scaling are referred to as Other forms of scaling are referred to as constant-voltage and quasi-constant-constant-voltage and quasi-constant-voltage.voltage.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3535
Bulk nMOSFETBulk nMOSFET
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3636
Technology ScalingTechnology Scaling A scaling factor (A scaling factor (S S ) reduces device dimensions as ) reduces device dimensions as
1/1/SS.. Successive generations of technology have used a Successive generations of technology have used a
scaling scaling S = √2, doubling the number of transistors , doubling the number of transistors per unit area. This produced 0.25per unit area. This produced 0.25μμ, 0.18, 0.18μμ, 0.13, 0.13μμ, , 90nm and 65nm technologies, continuing on to 90nm and 65nm technologies, continuing on to 45nm and 30nm.45nm and 30nm.
A 5% gate shrink (A 5% gate shrink (SS = 1.05) is commonly applied to = 1.05) is commonly applied to boost speed as the process matures.boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston:Pearson Addison-Wesley, 2005, Section 4.9.1.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3737
Constant Electric Field ScalingConstant Electric Field Scaling
Device ParameterDevice Parameter ScalingScaling
Length, Length, LL 1/1/SS
Width, Width, WW 1/1/SS
Gate oxide thickness, Gate oxide thickness, ttoxox 1/1/SS
Supply voltage, Supply voltage, VVDDDD 1/1/SS
Threshold voltages, Threshold voltages, VVtntn, V, Vtptp 1/1/SS
Substrate doping, Substrate doping, NNAA SS
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3838
Constant Electric Field Scaling(Cont.)Constant Electric Field Scaling(Cont.)Device CharacteristicDevice Characteristic ScalingScaling
ββ W / W / ((L tL toxox)) SS
Current, Current, IIdsds ββ ((VVDDDD – V – Vt t ) ) 22 1/1/SS
Resistance, Resistance, RR VVDD DD / I/ Idsds 11
Gate capacitance, Gate capacitance, CC W L / tW L / toxox 1/1/SS
Gate delay, Gate delay, ττ RCRC 1/1/SS
Clock frequency, Clock frequency, ff 11/ / ττ SS
Dynamic power per gate,Dynamic power per gate, P P CV CV 2 2 ff 1/1/S S 22
Chip area,Chip area, A A 1/1/S S 22
Power densityPower density P/AP/A 11
Current densityCurrent density IIds ds /A/A SS
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 3939
Problem: A Design ExampleProblem: A Design Example A battery-operated 65nm digital CMOS device is found A battery-operated 65nm digital CMOS device is found
to consume equal amounts (to consume equal amounts (P P ) of dynamic power and ) of dynamic power and leakage power. The short-circuit power is negligible. leakage power. The short-circuit power is negligible. The energy consumed by a computing task, that takes The energy consumed by a computing task, that takes TT seconds, is 2 seconds, is 2PTPT. .
Compare two power reduction strategies for extending Compare two power reduction strategies for extending the battery life:the battery life:
A. Clock frequency is reduced to half, keeping all other parameters constant.
B. Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 4040
Solution: Strategy A. Clock Solution: Strategy A. Clock Frequency ReductionFrequency Reduction
Reducing the clock frequency will reduce Reducing the clock frequency will reduce dynamic power to dynamic power to P P / 2, keep the static / 2, keep the static power the same as power the same as PP, and double the , and double the execution time of the task. execution time of the task.
Energy consumption for the task will be,Energy consumption for the task will be,
Energy = (Energy = (P P / 2 + / 2 + P P ) 2) 2TT = 3 = 3PTPT
which is greater than the original 2PT.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 4141
Solution: Part B. Supply Voltage Solution: Part B. Supply Voltage ReductionReduction
When the supply voltage and clock frequency When the supply voltage and clock frequency are reduced to half their values, dynamic are reduced to half their values, dynamic power is reduced to power is reduced to P P / 8 and static power to / 8 and static power to P P / 2. The time of task is doubled and the total / 2. The time of task is doubled and the total energy consumption is,energy consumption is,
Energy = (Energy = (P P / 8 + / 8 + P P / 2) 2/ 2) 2TT = 5 = 5PT PT / 4 =1.25/ 4 =1.25PTPT The voltage reduction strategy reduces
energy consumption while a simple frequency reduction consumes more energy.
Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC5270/6270 Spring 09, Lecture 4ELEC5270/6270 Spring 09, Lecture 4 4242
Comparing Strategies A and BComparing Strategies A and B
Original A B
Voltage V V V/2
Clock Frequency F F/2 F/2
Task Duration T 2T 2T
Power 2P 1.5P 0.625P
Energy 2PT 3PT 1.25P