© Digital Integrated Circuits 2nd Inverter Modified From "Digital Integrated Circuits", by J....

Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic. Copyright 1996 UCB

© Digital Integrated Circuits2nd Inverter

Digital Circuits

The Inverter


Modified From "Digital Integrated Circuits", by J. Rabaey, A. Chandrakasan and B. Nikolic

Outline The transistor as a switch Overview The Inverter: Basics Transfer Characteristics Propagation Delay Inverter Sizing Power Consumption



The Transistor as a switch



Switches



Overview



The Inverter

inv outv

VDD



DC OperationVoltage Transfer Characteristic

V(x)

V(y)

VOH

VOL

VM

VIH

VIL

fV(y)=V(x)

Switching Threshold

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

Nominal Voltage Levels



Mapping between analog and digital signals

VIL

VIH

Vin

Slope = -1

Slope = -1

VOL

VOH

Vout

“ 0” VOL

VIL

VIH

VOH

UndefinedRegion

“ 1”



Definition of Noise Margins

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input



Noise Immunity Noise margin measures the capability of a circuit to

overpower a noise source Noise immunity expresses the ability of a system to process

and transmit correctly in the presence of noise: Good noise immunity, input-output noise transfer function

is less than 1



Regenerative Property

(a) A chain of inverters.

v0, v2 , ...

v1, v3 , ... v1, v3 , ...

v0, v2 , ...

(b) Regenerative gate

f(v)

finv(v)

finv(v)

f(v)

(c) Non-regenerative gate

v0 v1 v2 v3 v4 v5 v6

...



Key Reliability Properties

Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low

impedance (in terms of voltage)

Noise immunity is the more important metric – the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver

and input impedance of the receiver;



Fan-in and Fan-out

N

Fan-out N Fan-in M

M



The Ideal Gate

Ri = Ro = 0Fanout = NMH = NML = VDD/2 g =

V in

V out



Delay Definitions

tpHL

tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf



Delay depends on technology and topology but also on input and output signals slopes !!!

Fall and rise times apply to individual waveforms. They are largely defined by the strength of the driving gate and the load

The de facto standard circuit for delay measurement is the ring oscillator



Ring Oscillator

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 tp N



A First-Order RC Network

vout

vin C

R

tp = ln (2) = 0.69 RC; tr = 2.2 RC

Important model – matches delay of inverter



The Inverter: Basics



The CMOS Inverter: A First Glance

V in Vout

CL

VDD



CMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well



CMOS InverterFirst-Order DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp



Voltage Transfer Characteristics

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDnVin=0

Vin=1.5

Vout

IDnVin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Vout

IDnVin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp



CMOS Inverter Load Characteristics

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS



CMOS Inverter VTC Vout

Vin0.5 1 1.5 2 2 .5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat



The Switching Threshold

Switching threshold VM is defined as the point where Vin = Vout



Switching Threshold as a function of Transistor Ratio


Yielding VM as a function of transistor geometries, threshold voltages and Vdd

22

TMp

ppTM

n

nn VVVdd

L

WKVV

L

WK

pn

TpTnpn

M

VVddVV

/1

)(/



Transistor Ratio Setting


With VM = Vdd/2 the right hand side equals, in general to 1, so that

P transistor wider than N for equal margins

2

2

TM

TM

pp

nn

VV

VVVdd

SK

SK

n

p

p

n

K

K

S

S



Switching Threshold



Switching Threshold as a function of Transistor Ratio

VM is relatively insensitive to variations in device ratio. Example: 0.25m (2.4V) process, setting Sn/Sp to 3, 2.5 and 2 yields

VM of 1.22, 1.18, 1.13

Asymmetrical characteristics: lot of sizing to obtain a significant shift. Previous example, Sn/Sp=10 is required to go to 1.5V. Further

increases are prohibitive



Noise Margins



Determining VIH and VIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simplified approach



Inverter Gain

1 2

1 2

m mg gg

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin

(V)

gain

Gain is almost purely specified by technology parameters, especially , and in minor way, by Vdd and the transistor sizes

2

1( )

2

( )

( )

m M T

A Ao

D M T

A

M T

g K V V

V Vr I K V V

Vg V V



Inverter Gain (Short Channel)

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin

(V)

gain

n

p

Dsatn

Dsatp

VK

VKr

Gain is almost purely specified by technology parameters, especially , and in minor way, by Vdd and the transistor sizes



Gain as a function of VDD

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin

(V)

Vou

t (V)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin

(V)

Vou

t(V

)

Gain=-1



Impact of Process Variations

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

Vo

ut(V

)

Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal

Simulations for standard worst case conditions



Gain as a function of VDD Reducing power supply reduces power

consumption, but it is detrimental to the delay of the gate

DC characteristics becomes sensitive to variations

Scaling the supply means reducing signal swing. This typically helps to reduce internal noise, but also makes the circuits more sensitive to noise sources that do not scale



Transient Analysis



Transient Analysis One method is to obtain an equivalent resistance for the

transistor while it is switching The input is assumed to change instantaneously Result varies slightly depending on the model assumed

a) Long channel b) Short channel



Fall time analysis



Rise time analysis



Gate delay estimation



Circuit delay estimation



Simplifying the problem



Computing Reff



NMOS transistor, logic 0



NMOS transistor, logic 1



PMOS transistors



Example of the process



Cascades



Equivalent output resistance: Short channel

2)(

2Dsat

DsatTDsat

VVVVdd

L

WKIIntegrar la curva hasta Vdsat utilizando

ID

VDS

VGS = VDD

VDD/2 VDD



Equivalent switching resistance Resistance is inversely

proportional to W/L For Vdd bigger than VT+Vdsat/2,

R becomes independent of the supply voltage Limit value:

If supply voltage approaches VT resistance increases dramatically

AMI 0.5um; S=3; K=54e-6; Ec L = 0.9V

VT = 0.5V

lim

1 1

2log(2) DSAT

RK S V

Vt Vdsat



Qualitative Analysis Response dominated by the output capacitance A fast gate has small output C or small resistance (increase

W/L) Notice that output resistance of the switch is not constant !!



(CMOS) Important Properties

High and low levels are VDD and GND (high noise margins) Logic levels are independent of device sizes (ratioless) Steady-state finite resistance path between VDD or GND and

output (low output resistance) Zero DC input current: A single inverter can theoretically

drive an infinite number of gates … No steady-state direct current path between VDD and GND

(no static power consumption)



Design for Performance



Computing capacitances: Input (GD) Cgd by Miller appears a

2Cgd at the input and the output

Also Cgs and Cgd Wiring (include if noticeable)

( 2 ) ( 2 )in GS n GDn Gn GS p GD p Gp W inC C C C C C C C

Assuming M1 and M2 are saturated Cg=Cgs=2/3 WLCox

2 2( 2 ) ( 2 )3 3n n p pin ox n n GDo GSo ox n n GDo GSo W inC C W L C C C W L C C C



Computing capacitances: Output (GD) overlap at the output due to

Miller (DB) Drain Diffusions

Cdb has to be linearized Wiring

(2 ) (2 )out GDn DBn GD p DBp W outC C C C C C



Computing capacitances: Inverter Load

( ) ( )L GS n GDn n n ox GS p GD p Gp p p oxC C C W L C C C C W L C

Fan out capacitance: M3/M4 do not change mode until

Vout reaches 50% (Vout2 is constant). No Miller

Cox changes (one saturated and one in cut-off). It is approximated for the worst case (10% error)

( ) ( )L GS n GDn Gn GS p GD p GpC C C C C C C



Example Minimum size inverter in 0.25µm

NMOS: 3λ/2λ (0.375/0.25); PMOS: 9λ/2λ (1.125/0.25) Capacitances:

Cgson=0.115fF; Cgdon=0.115fF;

Cgsop=0.305fF; Cgdop=0.305fF;

Cdbn=0.8fF; Cdbp=1.35fF;

WLCoxn=0.53fF; WLCoxp=1.67fF;

Inverter capacitances Cin=2.72fF Cout=2.68 CL=3.04fF

2.72 fF 5.72 fF



Computing Capacitances: Pass Transistor From the gate:

If output does not change Cg=Cgso+Cgdo+WLCox Triode

If output changes Cg=Cgso+2Cgdo+(2/3) WLCox

Cav=Cgso+1.5 Cgdo+1.5 WLCox From the S/D terminal

If gate is ON 1 ->0: Cin=Cgso+Cdiff+(2/3) WL Cox

During the transition the transistor is in saturation and we drive the source 0->1: Cin=Cgso+Cdiff

During the transition the transistor is in saturation and we drive the drain If gate is OFF

Cin=Cgso+Cdiff



Design for Performance Keep capacitances (internal, interconnect and fan-out) small

by good layout Increase transistor sizes

watch out for self-loading! Once that the intrinsic capacitance dominates the delay, W/L does not help anymore

Increase VDD (????): There are limits to the maximum. Increases power consumption



Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(nor

mal

ized

)

The shape of this curve is the same as R vs. VDD

Smaller VDD implies smaller current Id, and slower transition



If a symmetrical characteristic is not important, inverter can be optimized for speed by reducing the P-size. Design variable:

NMOS/PMOS ratio

1 1 2 2

1 2

( ) ( )

(1 )( )

L dp dn dp dn w

L dn gn w

C C C C C C

C C C C

1 2

0 1p wopt

dn gn

t Cr

C C

1 1 2 2, , / ,

/ /

dp dn gp gn p eqp

eqp eqn p n

C C C C R R

r R R

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

t p(sec

)

tpLH tpHL

tp

= Wp/Wn If Cw<<C, then optimum factor is sqrt(r) instead of r (symm. swing)Considering two identical cascaded inverters:

1 2(1 )( ) R 1p dn gn w eq

rt C C C



Device Sizing Assuming a symmetrical inverter, the capacitance is composed of:

Cint is the self-load, associated with diffusion and gate-drain (Miller) Cext is extrinsec, load, wiring, etc.

Where is the intrinsec delay (Cext=0)

What are the consequences of scaling ?

extL CCC int

)/1()(69.0 int0int CCtCCRt extpexteqp

int0 69.0 CRt eqp



Device Sizing Cint scales with size ratio S, and also Req:

The delay is:

int , / ,iref eq irefC SC R R S

)/1(0 irefextpp SCCtt

• The intrinsic delay is independent of sizing and is determined by technology and layout.

• Making S infinitely large gives the maximum performance gain, eliminating the impact of an external load. Yet, a big enough sizing produces similar results with a gain in Silicon area

• A big inverter has big input capacitance and affects the previous stages !



2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(sec

)

Device Sizing

(for fixed load)

Self-loading effect:Intrinsic capacitancesdominate



Inverter Chain Sizing



Inverter Chain

CL

If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?

May need some additional constraints.

In Out



Inverter Delay Minimum length devices, L Assume the same electrical

characteristics Wn = 2 Wp approx. equal rise tpLH and fall

tpHL delays

tpHL = k RNCL tpLH = k RPCLDelay (D):

2W

W



Delay Formula

/1/1

~

0int ftCCCkRt

CCRDelay

pintLWp

LintW

Cint = Cgin with 1

f = CL / Cgin - effective fanout

Delay is only a function of the ratio between its external load capacitance and its input capacitance

Inverter 0.25µm

γ=2.68/2.72=0.98



Apply to Inverter Chain

CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

jgin

jginunitunitpj C

CCRt

,

1,1~

LNgin

N

i jgin

jginp

N

jjpp CC

C

Cttt

1,

1 ,

1,0

1, ,1



Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay

Size of each stage is the geometric mean of two neighbors1,1,, jginjginjgin CCC



Optimum Delay and Number of Stages

1,/ ginLN CCFf

When each stage is sized by f and has same eff. fanout f:

N Ff

/10N

pp FNtt

Minimum path delay

Effective fanout of each stage:



Example

CL= 8 C1

In Out

C11 f f2

283 f

CL/C1 has to be evenly distributed across N = 3 stages:



Optimum Number of Stages

For a given load, CL and given input capacitance Cin

Find optimal sizing f

00

ln1

ln lnp

p p

t Ff ft Nt

f f

0ln

1lnln2

0

f

ffFt

f

t pp

f

FNCfCFC in

NinL ln

ln with

ff 1exp

f that minimizes total delay results from:



Optimum Effective Fanout fOptimum f for given process defined by g

ff 1exp

fopt = 3.6for =1

For = 0, f = e, N = lnF



Trade-offs in the choice of N Number of stages large, intrinsic delay dominates Too small, the effective fan-out dominates

With more stages (smaller f), N grows exponencially and f decreases linearly: tp increases

With fewer stages (bigger f), N reduces and f increases: tp remains roughly constant

0

log( )1 / ,

log( )p p

Ft Nt f N

f



Choice of N: Example Example: Ci=1fF, Cout=1pF:

F=1000 /10

Npp FNtt

tp (normalized delay)N (number of stages)

f fMake f slightly larger than optimum (to round off stages. Typ.=4)



Normalized delay function of F Values of tp/Optimum(tp) for several designs

F Unbuffered Two Stage Inverter chain

10 11 8.3 8.3

100 101 22 16.5

1000 1001 65 24.8

10,000 10,001 202 33.1



Buffer Design

1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3



Impact of Rise Time on Delay

t pH

L(n

sec

)0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20



Practical Rules Keep signal rise times smaller than or equal to gate

propagation delays (for both performance and power consumption)

Keep rise and fall times small and of similar values (challenge known as slope engineering)



Power Dissipation



Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors



Dynamic Power Dissipation

2

000

)( VddCdvCdtdt

dvCVdddtVddtiE L

Vdd

outLout

LVddVdd

Vin Vout

CL

Vdd

2)(

2

000

VddCdvvCdtv

dt

dvCdtvtiE L

Vdd

outoutLoutout

LoutVddC



Dynamic Power Dissipation

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd, and f to reduce power.

Vin Vout

CL

Vdd

Not a function of transistor sizes!

Dependence with supply voltage is quadratic !!!



Node Transition Activity and PowerConsider switching a CMOS gate for N clock cycles

EN CL Vdd 2 n N =

n(N): the number of 0->1 transition in N clock cycles

EN : the energy consumed for N clock cycles

Pavg N lim

ENN

-------- fclk= n N

N------------

N lim

C

LVdd

2fclk

=

0 1

n N N

------------N

lim=

Pavg = 0 1 C

LVdd

2 fclk



Vin Vout

CL

Vdd

I VD

D (m

A)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0

Short Circuit CurrentsI peak is a function of transistor sizes.

Reading Material

CMOS Circuit Speed and Buffer OptimizationHedenstierna, N.; Jeppson, K.O.;Computer-Aided Design of Integrated Circuits and Systems,

IEEE Transactions onVolume 6, Issue 2, March 1987 Page(s):270 - 281

21( )

2 TP K Vdd V VddT

It is also a strong function of the input and output slopes …



Short Circuit Currents

If the output is too slow, then the P transistor is off and there’s no direct current

Vin Vout

CL

Vdd



Short Circuit Current

If the output is too fast, then the P transistor goes quickly to saturation (Vds = Vcc) and power consumption is maximum

Vin Vout

CL

Vdd



Short Circuit Current

Graph of direct current versus output capacitance

Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so ...



How to keep Short-Circuit Currents Low?

Graph of power dissipation versus output capacitance for various rise times (fixed freq. and Vdd)



Minimizing Short-Circuit Power

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin

/tsout

Pno

rm

Vdd =1.5

Vdd =2.5

Vdd =3.3



Leakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-Threshold Current Dominant FactorSub-threshold current one of most compelling issuesin low-energy circuit design!



Reverse-Biased Diode Leakage

Np+ p+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS A

JS = 1-5pA/m2 for a 1.2m CMOS technology

Js double with every 9oC increase in temperature

JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOSJS doubles for every 9 deg C!



Subthreshold Leakage Component



Static Power Consumption

Vin=5V

Vout

CL

Vdd

Istat

Pstat = P(In=1).Vdd . Istat

• Dominates over dynamic consumption

• Not a function of switching frequency

Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)



Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav tp

Energy-Delay Product (EDP) =

quality metric of gate = E tp



Power Delay Product or Energy/Operation The PDP is a measure of Energy

Assuming that the gate is switched at the maximum possible rate of

PDP gives the average energy per switching event

ptf 2/1max

pavtPPDP

2

2VddCPDP L



Energy-Delay Product (EDP) PDP is questionable as a performance index. A low supply gives a

reduced PDP but at the cost of speed. EDP measures energy and performance:

ptPDPEDP p

L tVddC

EDP2

2

Energy

Vdd

Energy-Delay

Delay

0.5 2.51.2



Principles for Power Reduction Prime choice: Reduce voltage!

Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by

2010!)

Reduce switching activity Reduce physical capacitance



Short Channel Model Short channel model

Vdsat is no longer Vgt=Vg-Vt, but:

For small Vgt, Vdsat=Vgt and coincides with the long channel case For bigger drives (Vgt), Vdsat reaches a limit value of Vdsat=Ec L

,1 /

,

eff

sat

EE Ec

v E Ecv E Ec

c GT

c GT

E LVVdsat

E L V

1( / 2)

1 /D eff ox GT DS DSDS c

I C S V V VV E L



Triode and saturation region

c GT

c GT

E LVVdsat

E L V

triode

Id

Vds

Vel. saturation

Ec L



Transfer characteristic

cuadratic

linear

Asymptote: Vt+EcL/2

Id

Vg



Digital case For the digital case, Vgt is generally big, therefore:

Referencias: Sodini C. G., P. Ko, J. L. Moll, “The effect of high fields on MOS

device and circuit performance,” IEEE Trans. El. Devices, Vol. ED31, No. 10, Oct. 1984, pp. 1386-1393.

Toh K., Ko P., Meyer R. G., “An engineering model for short-channel MOS devices,” IEEE J. Solid state circuits, Vol. 23, No. 4. August 1988, pp. 950-958.

cVdsat E L1

( )2D GT DSAT DSATI KS V V V

© Digital Integrated Circuits 2nd Inverter Modified From "Digital Integrated Circuits", by J....

Documents

Transcript of © Digital Integrated Circuits 2nd Inverter Modified From "Digital Integrated Circuits", by J....