Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Coping …baccaran/Rabaey/chapter09.pdf ·...

© Digital Integrated Circuits2nd Interconnect

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Coping withCoping withInterconnectInterconnect

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

December 15, 2002


Impact of Interconnect Impact of Interconnect ParasiticsParasitics• Reduce Robustness• Affect Performance

• Increase delay• Increase power dissipation

Classes of Parasitics

• Capacitive

• Resistive

• Inductive


INTERCONNECTINTERCONNECT


Capacitive Cross TalkCapacitive Cross Talk

X

YVXCXY

CY


Capacitive Cross TalkCapacitive Cross TalkDynamic NodeDynamic Node

3 x 1 µm overlap: 0.19 V disturbance

CY

CXY

VDD

PDN

CLK

CLK

In1In2In3

Y

X

2.5 V

0 V


Capacitive Cross TalkCapacitive Cross TalkDriven NodeDriven Node

τXY = RY(CXY+CY)

Keep time-constant smaller than rise time

V ( V o l t )

0

0.50.450.4

0.350.3

0.250.2

0.150.1

0.050 10.80.6

t (nsec)0.40.2

X

YVXRY CXY

CY

tr↑


Dealing with Capacitive Cross TalkDealing with Capacitive Cross Talk

Avoid floating nodesProtect sensitive nodesMake rise and fall times as large as possibleDifferential signalingDo not run wires together for a long distanceUse shielding wiresUse shielding layers


ShieldingShielding

GND

GND

Shieldingwire

Substrate (GND )

Shieldinglayer

VDD


Cross Talk and PerformanceCross Talk and Performance

Cc

- When neighboring lines switch in opposite direction of victim line, delay increases

DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORING WIRES

Miller EffectMiller Effect

- Both terminals of capacitor are switched in opposite directions (0 → Vdd, Vdd → 0)

- Effective voltage is doubled and additional charge is needed (from Q=CV)


Impact of Cross Talk on Delay Impact of Cross Talk on Delay

r is ratio between capacitance to GND and to neighbor


Structured Predictable InterconnectStructured Predictable Interconnect

S

S SV V S

G

SSV

G

VS

S SV V S

G

SSV

G

VExample: Dense Wire Fabric ([Sunil Kathri])Trade-off:• Cross-coupling capacitance 40x lower, 2% delay variation• Increase in area and overall capacitance Also: FPGAs, VPGAs


Interconnect ProjectionsInterconnect ProjectionsLowLow--k dielectricsk dielectrics

Both delay and power are reduced by dropping interconnect capacitanceTypes of low-k materials include: inorganic (SiO2), organic (Polyimides) and aerogels (ultra low-k)The numbers below are on the conservative side of the NRTS roadmap

Generation 0.25µm

0.18µm

0.13µm

0.1µm

0.07µm

0.05µm

DielectricConstant

3.3 2.7 2.3 2.0 1.8 1.5

ε


Encoding Data Avoids WorstEncoding Data Avoids Worst--CaseCaseConditionsConditions

Encoder

Decoder

Bus

In

Out


Driving Large CapacitancesDriving Large Capacitances

Vin Vout

CL

VDD

• Transistor Sizing• Cascaded Buffers


Using Cascaded BuffersUsing Cascaded Buffers

CL = 20 pF

In Out

1 2 N

0.25 µm processCin = 2.5 fFtp0 = 30 ps

F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns

(See Chapter 5)


Output Driver DesignOutput Driver Design

Trade off Performance for Area and EnergyGiven tpmax find N and f

Area

Energy

( ) minminmin12 11

11...1 A

fFA

ffAfffAN

Ndriver −

−=

−−

=++++= −

( ) 2221211

1...1 DDLDDiDDiN

driver VfCVC

fFVCfffE

−≈

−−

=++++= −


Delay as a Function of F and NDelay as a Function of F and N

101 3 5 7

Number of buffer stages N

9 11

10,000

1000

100

t

p

/

t

p

0

F = 100F = 1000

F = 10,000

t p/t p

0


Output Driver DesignOutput Driver Design

Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns

Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns

0.25 µm process, CL = 20 pF


How to Design Large TransistorsHow to Design Large Transistors

G(ate)

S(ource)

D(rain)

MultipleContacts

small transistors in parallel

Reduces diffusion capacitanceReduces gate resistance


Bonding Pad DesignBonding Pad DesignBonding Pad

Out

InVDD GND

100 µm

GND

Out


ESD ProtectionESD ProtectionWhen a chip is connected to a board, there is unknown (potentially large) static voltage differenceEqualizing potentials requires (large) charge flow through the padsDiodes sink this charge into the substrate –need guard rings to pick it up.


ESD ProtectionESD Protection

Diode

PAD

VDD

R D1

D2X

C


Chip PackagingChip Packaging

ChipL

L ´

Bonding wire

Mountingcavity

Leadframe

Pin

•Bond wires (~25µm) are used to connect the package to the chip

• Pads are arranged in a frame around the chip

• Pads are relatively large (~100µm in 0.25µm technology),with large pitch (100µm)

•Many chips areas are ‘pad limited’


Pad FramePad FrameLayout Die Photo


Chip PackagingChip PackagingAn alternative is ‘flip-chip’:

Pads are distributed around the chipThe soldering balls are placed on padsThe chip is ‘flipped’ onto the packageCan have many more pads


TristateTristate BuffersBuffers

InEn

En

VDD

Out

Out = In.En + Z.En

VDD

In

En

EnOut

Increased output drive


Reducing the swingReducing the swing

tpHL = CL Vswing/2

Iav

Reducing the swing potentially yields linear reduction in delay

Also results in reduction in power dissipationDelay penalty is paid by the receiver Requires use of “sense amplifier” to restore signal

levelFrequently designed differentially (e.g. LVDS)


SingleSingle--Ended Static Driver and Ended Static Driver and ReceiverReceiver

CL

VDD

VDD VDD

driver receiver

VDDL

VDDLIn

OutOut


Dynamic Reduced Swing NetworkDynamic Reduced Swing Network

fIn2.fIn1.

f M2

M1 M3

M4

Cbus Cout

Bus Out

VDD VDD

V ( V o l t )

f

V busVasym

V sym

2 4 6time (ns)

8 10 120

0.5

1

1.5

2

2.5

0


Impact of ResistanceImpact of ResistanceWe have already learned how to drive RC interconnectImpact of resistance is commonly seen in power supply distribution:

IR dropVoltage variations

Power supply is distributed to minimize the IR drop and the change in current due to switching of gates


RI Introduced NoiseRI Introduced Noise

M1

X

I

R9

RDV

f pre

DV

VDD

VDD 2 DV9

I

© Digital Integrated Circuits2nd Interconnect19ASP DAC 2000

Power Dissipation TrendsPower Dissipation Trends

Power consumption is increasingPower consumption is increasingBetter cooling technology neededBetter cooling technology needed

Supply current is increasing faster!Supply current is increasing faster!OnOn--chip signal integrity will be a major chip signal integrity will be a major issueissuePower and current distribution are criticalPower and current distribution are criticalOpportunities to slow power growthOpportunities to slow power growth

Accelerate Accelerate VddVdd scalingscalingLow κ dielectrics & thinner (Cu) Low κ dielectrics & thinner (Cu) interconnectinterconnectSOI circuit innovations SOI circuit innovations Clock system designClock system designmicromicro--architecturearchitecture

Power Dissipation

020406080

100120140160

EV4 EV5 EV6 EV7 EV8

Pow

er (W

)

00.511.522.533.5

Vol

tage

(V)

Supply Current

020406080

100120140

EV4 EV5 EV6 EV7 EV8

Cur

rent

(A)

00.511.522.533.5

Volta

ge (V

)


Resistance and the Power Resistance and the Power Distribution ProblemDistribution Problem

Source: Cadence

•• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction•• Heavily influenced by packaging technologyHeavily influenced by packaging technology

BeforeBefore AfterAfter


Power DistributionPower DistributionLow-level distribution is in Metal 1Power has to be ‘strapped’ in higher layers of metal.The spacing is set by IR drop, electromigration, inductive effectsAlways use multiple contacts on straps


Power and Ground DistributionPower and Ground Distribution

GND

VDD

Logic

GND

VDD

Logic

GND

VDD

(a) Finger-shaped network (b) Network with multiple supply pins


3 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to the

technology for EV4 designPower supplied from two sides of the die via 3rd metal layer

2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routing

Metal 3

Metal 2Metal 1

Courtesy Compaq


4 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to the

technology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal

90% of 3rd and 4th metals used for power/clock routing

Metal 3

Metal 2Metal 1

Metal 4

Courtesy Compaq


2 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/Vss

Significantly lowers resistance of gridLowers on-chip inductance

6 Metal Layer Approach 6 Metal Layer Approach –– EV6EV6

Metal 4

Metal 2Metal 1

RP2/Vdd

RP1/Vss

Metal 3

Courtesy Compaq


ElectromigrationElectromigration (1)(1)

Limits dc-current to 1 mA/µm


ElectromigrationElectromigration (2)(2)


ResistivityResistivity and Performanceand Performance

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

vo

ltag

e (

V)

x= L /10

x = L/4

x = L/2

x= L

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

vo

ltag

e (

V)

x= L /10

x = L/4

x = L/2

x= L

Diffused signal Diffused signal propagationpropagation

Delay ~ LDelay ~ L22

CN-1 CNC2

R1 R2

C1

Tr

Vin

RN-1 RN

The distributed The distributed rcrc--lineline


The Global Wire ProblemThe Global Wire Problem

ChallengesNo further improvements to be expected after the introduction of Copper (superconducting, optical?)Design solutions

Use of fat wiresInsert repeaters — but might become prohibitive (power, area)Efficient chip floorplanning

Towards “communication-based” design How to deal with latency?Is synchronicity an absolute necessity?

( )outwwdoutdwwd CRCRCRCRT +++= 693.0377.0


Interconnect Projections: CopperInterconnect Projections: CopperCopper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97)With cladding and other effects, Cu ~ 2.2 µΩ-cm vs. 3.5 for Al(Cu) ⇒40% reduction in resistanceElectromigration improvement; 100X longer lifetime (IBM, IEDM97)

Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95)

Vias


Interconnect:Interconnect:# of Wiring Layers# of Wiring Layers

# of metal layers is steadily increasing due to:

• Increasing die size and device count: we need more wires and longer wires to connect everything

• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC

substrate

poly

M1

M2

M3

M4

M5

M6

Tins

H

WS

ρ = 2.2 µΩ-cm

0.25 µm wiring stack

Minimum Widths (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

M5M4M3M2M1Poly

Minimum Spacing (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ

M5M4M3M2M1Poly


Diagonal WiringDiagonal Wiring

y

x

destination

Manhattan

source

diagonal

• 20+% Interconnect length reduction• Clock speedSignal integrityPower integrity

• 15+% Smaller chips plus 30+% via reduction

Courtesy Cadence X-initiative


Using BypassesUsing BypassesDriver

Polysilicon word line

Polysilicon word line

Metal word line

Metal bypass

Driving a word line from both sides

Using a metal bypass

WL

WL K cells


Reducing RCReducing RC--delaydelay

Repeater

(chapter 5)


Repeater Insertion (Revisited)Repeater Insertion (Revisited)Taking the repeater loading into account

For a given technology and a given interconnect layer, there exiFor a given technology and a given interconnect layer, there exists sts an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!


L L di/dtdi/dt

Impact of inductance on supply voltages:• Change in current induces a change in voltage• Longer supply lines have larger LCL

V’DD

VDD

L i(t)

VoutV in

GND ’

L


L L di/dtdi/dt: Simulation: Simulation

0 0.5 1 1.5 2x 10-9

0

0.5

1

1.5

2

2.5V o

ut(V

)

0 0.5 1 1.5 2x 10-9

0

0.02

0.04

i L(A

)

0 0.5 1 1.5 2x 10-9

0

0.5

1

VL

(V)

time (nsec)

0 0.5 1 1.5 2x 10-9

0

0.5

1

1.5

2

2.5

0 0.5 1 1.5 2x 10-9

0

0.02

0.04

0 0.5 1 1.5 2x 10-9

0

0.5

1

time (nsec)

Input rise/fall time: 50 psec Input rise/fall time: 800 psec

decoupled

Without inductorsWith inductors


Dealing with Dealing with Ldi/dtLdi/dtSeparate power pins for I/O pads and chip core.Multiple power and ground pins. Careful selection of the positions of the power and ground pins on the package.Increase the rise and fall times of the off-chip signals to the maximum extent allowable.Schedule current-consuming transitions. Use advanced packaging technologies.Add decoupling capacitances on the board.Add decoupling capacitances on the chip.


Choosing the Right PinChoosing the Right Pin

ChipL

L ´

Bonding wire

Mountingcavity

Leadframe

Pin


Decoupling CapacitorsDecoupling Capacitors

SUPPLY

Boardwiring

Bondingwire

Decouplingcapacitor

CHIPCd

1

2

Decoupling capacitors are added: • on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)


DeDe--coupling Capacitor Ratioscoupling Capacitor RatiosEV4

total effective switching capacitance = 12.5nF128nF of de-coupling capacitancede-coupling/switching capacitance ~ 10x

EV513.9nF of switching capacitance 160nF of de-coupling capacitance

EV634nF of effective switching capacitance320nF of de-coupling capacitance -- not enough!

Source: B. Herrick (Compaq)


EV6 DeEV6 De--coupling Capacitancecoupling CapacitanceDesign for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600

MHz0.32-µF of on-chip de-coupling capacitance was added

– Under major busses and around major gridded clock drivers– Occupies 15-20% of die area

1-µF 2-cm2 Wirebond Attached Chip Capacitor (WACC) significantly increases “Near-Chip” de-coupling

– 160 Vdd/Vss bondwire pairs on the WACC minimize inductance



EV6 WACCEV6 WACC

587 IPGA

MicroprocessorWACC

Heat Slug

389 Signal - 198 VDD/VSS Pins389 Signal Bondwires

395 VDD/VSS Bondwires320 VDD/VSS Bondwires



The Transmission LineThe Transmission Line

The Wave Equation

Vin Voutr

g c

r r x

g c

r

g c g c

l l l l


Design Rules of ThumbDesign Rules of Thumb

Transmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).

tr (tf)


Should we be worried?Should we be worried?

Transmission line effects cause overshooting and non-monotonic behavior

Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]


Matched TerminationMatched Termination

Z 0 Z L

Z 0

Series Source Termination

Z 0 Z 0

Z S

Parallel Destination Termination


Segmented Matched Line DriverSegmented Matched Line Driver

Z0

c1 c2

s0 s1 s2 sn

cn

ZL

GND

VDDIn


Parallel TerminationParallel Termination──Transistors as ResistorsTransistors as Resistors

0.5

Normalized Resistance (

V

)

1

PMOS with-1V bias

NMOS-PMOS

PMOS only

NMOS only

1.5VR (Volt)

2 2.50

1.11

1.21.31.41.51.61.71.81.9

2

Out

Mr

Vdd

Out

Mr

Vdd

Vbb

Out

Mrp Mrn

Vdd


Output Driver with Varying Output Driver with Varying TerminationsTerminations

V

out

(V)

V

out

(V)

1 2 3 4

time (sec)

Revised design with matched driver impedance

Vs

Vd

Vin

5 6 7 80

1

0

1

2

3

4

1 2 3 4

Initial design

Vs

Vd

Vin

5 6 7 80

1

0

1

2

3

4

Vin

L= 2.5 nH

VDD

V s V d

VDD

ClampingDiodes

CL= 5 pF CL

L = 2.5 nH

L = 2.5 nH Z 0 = 50 Ω

275

120


The “NetworkThe “Network--onon--aa--Chip”Chip”

EmbeddedProcessorsEmbeddedProcessors

MemorySub-system

MemorySub-system

AccelatorsAccelatorsConfigurableAcceleratorsConfigurableAccelerators PeripheralsPeripherals

Interconnect Backplane

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Coping …baccaran/Rabaey/chapter09.pdf ·...

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