VHDL/PLD Design Methodology Electronic design...

Hardware Design with VHDL VHDL I ECE 443

ECE UNM 1 (8/20/09)

VHDL/PLD Design Methodology

Electronic design automation (EDA) refers to a set of software tools for the design,

verification and implementation of digital (and analog) hardware systems

Hardware decription languages, such as VHDL and Verilog, are programming lan-

guage for the design and modeling of digital hardware systems

VHDL can be used to design immutable chips (ASICs) or systems implemented on

programmable logic devices (PLDs), such as FPGAs

This course focuses on the VHDL/FPGA design methodology

The VLSI course uses VHDL and Verilog for the design of ASICs

A design methodology is a coherent set of methods, principles or rules for designing a

systems

Embodied in a design methodology are the phases (steps) used in the design

process and the EDA tools used in each phase

The complete sequence of phases defines a design flow


ECE UNM 2 (8/20/09)


The VHDL/PLD design methodology uses:

• VHDL to describe both the system being designed and the test bench used to verify

the design

• A simulator tool to simulate the design to verify its functionality and timing

• A software synthesis tool to create the logic described by the VHDL description

• A software place-and-route tool to map the synthesized logic to the target PLD and

to generate a timing model and a configuration file

• A PLD to physically implement the design

• Information in the configuration file to program the PLD

VHDL is a high-level textual programming language that includes specialized con-

structs to describe (model) the behavior or structure of a hardware system

A VHDL model is a textual description of a system that, when simulated,

behaves like the intended hardware system

VHDL appears similar to a C program, but differs in important ways such as the

inclusion of constructs to support the description of concurrency and timing


ECE UNM 3 (8/20/09)


Hardware systems are inheriently parallel so a critical feature of VHDL (or any HDL

for that matter) is the ability to describe simultaneous or concurrent signal events

VHDL allows the system to be described at an abstract and technology independent

level

Different models may be created to represent the same system at different levels

of abstraction (detail)

EDA: Contemporary digital design is very dependent on EDA software tools

Included are simulators, synthesizers and place-and-route tools

Under the VHDL/FPGA design methodology, the combined purpose of all these

tools is to convert a VHDL description to a stream of bits used to program a FPGA

EDA tools automate the more labor-intensive and error-prone design tasks, such as

logic minimization and state assignment optimization

The rapid turn-around time provided by the tools allows alternatives to be explored


ECE UNM 4 (8/20/09)


VHDL/PLD Design Flow

A design flow starts with design entry and ends with photomasks or a programming

file (for FPGAs).

A successful design might require multiple, iterative passes through all or part of this

flow.

Analyze

Develop

requirements

specification

Write

Compile

VHDL

design

Developverification

designdesc.

desc.

plan

WriteVHDL

testbench

Functionalsimulation

SelectPLD

Synthesizelogic

Post-synth.simulation

Place &route logic

Timingsimulation

to PLD

Program

Verify

PLD

PLDop.


ECE UNM 5 (8/20/09)


During requirements analysis, a written requirements document is produced that

completely describes the problem to be solved as well as any constraints.

The specification is written from the requirements analysis document.

It describes the system’s interface and its functions and includes constraints,

such as speed of operation and max power consumption.

The specification can be written in a natural language (more common) or directly in

VHDL.

The latter is better at eliminating ambiguities and allows for an executable sys-

tem model that is independent of any particular hardware implementation.

The executable system model can be simulated to verify its correctness.

Note that a specification written in VHDL may NOT be synthesizable -- a syn-

thesizable version may need to be written from it later.

Consider the requirements definition "We need to add two one-bit binary numbers"


ECE UNM 6 (8/20/09)


For the requirements definition of a half-adder, we can write the specification as "The

circuit must add two binary inputs, producing two outputs, a sum and a carry".

In addition, a timing constraint may be included and/or a block diagram:

The next two phases are write the VHDL design description and compile the design

description.

A design description is a VHDL description that can be synthesized into hardware.

It can be behavioral or structural.

A behavioral description specifies the computation of output values as a function of

input values.

a

b

sum

c_outHalf adder


ECE UNM 7 (8/20/09)


In contrast, a structural description is a hierarchical description of interconnected

components.

To be complete, each component must have an associated behavioral descrip-

tion.

From the definition of binary addition, we know:

Or we can create a truth table (if we don’t know the equations):

In this case, we write the canonical sum-of-products equation for each output.

a b sum carry_outsum

minterms

carry_out

minterms

0 0 0 0

0 1 1 0 ab

1 0 1 0 ab

1 1 0 1 ab

sum a b⋅ a b⋅+=

carry_out a b⋅=


ECE UNM 8 (8/20/09)


Once the functions are known, we can write the VHDL design description.

library ieee;

use ieee.std_logic_1164.all;

entity half_adder is

port(

a, b: in std_logic;

sum, carry_out: out std_logic);

end half_adder;

architecture dataflow of half_adder is

begin

sum <= (not a and b) or (a and not b);

carry_out <= a and b;

end dataflow;

The first two statement form a context clause, i.e., a library clause and a use clause.

A library clause is required when objects not predefined in VHDL are used.


ECE UNM 9 (8/20/09)


The half-adder program uses a data type called std_logic, which is defined in the

package STD_LOGIC_1164 in the library ieee.

A library can contain packages, which are collections of commonly used data type

declarations and/or subprograms.

The simplest VHDL design descriptions consist of a single design entity.

A design entity has well-defined inputs and outputs and performs a well-defined

function.

A design entity consists of two parts, an entity declaration and an architecture

body.

An entity declaration assigns a name and describes the interface (I/O signals).

The I/O signals are called ports.

A data type is associated with each port, which determines the values the signal may

have and the permissable operations.


ECE UNM 10 (8/20/09)


The std_logic data type provides nine different values to represent a logic signal,

including ’0’ and ’1’ plus others to be discussed.

The architecture body associated with a design entity declaration describes either its

behavior or its structure.

The architecture shown above is written in a style called dataflow, which describes a

system’s behavior in terms of how data flows through the system.

Each output is defined by a concurrent signal assignment statement, e.g.,


Here, and, or and not keywords are VHDL logical operators, NOT actual gates.

In a physical implementation, each logical operation may, in fact, be synthesized

using AND< OR and NOT gates or by other types of logic, e.g., NAND or MUXs.

Each concurrent signal assignment (CSA) stmt assigns a new value to the signal on

the left when there is an event on a signal on the the right-hand side.


ECE UNM 11 (8/20/09)


The left-hand signal is sensitive to events on signals on the right-hand side.

A CSA stmt executes only in response to an event on one or more of the signals to

which it is sensitive.

The order of execution of a CSA is solely determined by the order of events that

occur on its right-hand signals.

For example, if an event occurs on a, both CSA stmts execute:


carry_out <= a and b;

These stmts are called concurrent because they allow for simultaneous execution,

which IS the proper model for hardware gates.

This concept of concurrent execution is critically important to HDLs and is distinct

from the sequential execution of stmts in a conventional programming language.


ECE UNM 12 (8/20/09)


VHDL also has sequential statements, like those found in a programming language.

Such statement can ONLY appear inside a process statement or a subprogram.

A process statement is a concurrent statement that contains a sequence of sequential

statements.

We’ll cover these later.

A VHDL design description is compiled like a program written in a conventional

programming language.

VHDL compilers are sometimes called analyzers -- they check the design file for

syntax and static semantic errors before it is simulated.

Compilation is VHDL is ONLY associated with simulation -- execution of a com-

piled binary (in programming language) has no direct analog in hardware.


ECE UNM 13 (8/20/09)


Verification is the process used to demonstrate the correctness of a design, both func-

tional and timing correctness.

Simulation is a key element of the verification process.

It can execute a design description’s source code, it allows inputs to be applied

and outputs to be observed, and debugging.

Simulation is performed at three different phases in the design flow.

• Functional simulation: The VHDL design description is simulated to verify the sys-

tem meets the functional requirements of its specification.

• Post-synthesis simulation: The synthesized VHDL netlist (gate-level model) is sim-

ulated, again to verify that the synthesized logic is functionally correct.

• Timing simulation: The VHDL timing model (generated by the place-and-route

tool) of the synthesized logic is simulated to verify it meets the timing specs.

The simulus used in the simulation can be generated and applied in three ways:

• Interactive simulator allows the user to manually apply a stimulus.

• Command-line simulation which allow the user to specify the simulus in a file.


ECE UNM 14 (8/20/09)


These two approaches are not suitable for complex designs and are not portable.

The third, and preferred approach, is to use a VHDL testbench.

There are four steps in a VHDL testbench verification:

• Develop a verification plan

• Write a VHDL testbench

• Compile the testbench

• Functional simulation

The verification plan is a document, of substantial complexity for large systems, that

is derived from the system’s requirements and specs.

Even a simple system requires some thought as to the appropriate stimulus -- the

stimulus must cover all circumstances in which the design will be used.

A testbench is a VHDL program that applies a predetermined stimulus to a design

entity during simulation.

It can also check output values -- therefore, it is similar to an ATE.


ECE UNM 15 (8/20/09)


The design entity being verified is called the unit under test (UUT).

The testbench is also a design entity.

It consists of a testbench entity declaration and associated architecture body.

A simple testbench consists of:

• An instance of the UUT

• Signals mapped to the UUT’s ports

• A process statement that applies stimulus to the UUT, via signals.

The testbench completely encloses its UUT and simulates the environment in whcih

the design will operate.

Testbench

StimulusGenerator

UUT

a

b

a_tb

b_tb half addersum

carry

sum_tb

carry_out_tbResponseMonitor


ECE UNM 16 (8/20/09)


The testbench is entire self-contained -- it has no inputs or outputs.

Stmts in the architecture body apply stimulus to the UUT’s inputs -- other stmts

monitor the outputs.

Note that the UUT changes depending on the type of simulation, functional, post-

synthesis or timing simulation.

library ieee;

use ieee.std_logic_1164.all;

entity testbench is

end testbench;

architecture behavior of testbench is

-- declare signals

signal a_tb, b_tb, sum_tb, carry_out_tb: std_logic;

begin


ECE UNM 17 (8/20/09)


-- create an instance of the circuit to be tested.

uut: entity half_adder port map(a=>a_tb, b=>b_tb,

sum=>sum_tb, carry_out=>carry_out_tb);

-- define a process to apply input stimulus and

-- check outputs

tb: process

constant period: time:= 20 ns;

begin

-- apply all input combinations

a_tb <= ’0’;

b_tb <= ’0’;

wait for period;

assert ((sum_tb = ’0’) and (carry_out_tb = ’0’))

report "test failed for input combination 00"

severity error;


ECE UNM 18 (8/20/09)


a_tb <= ’0’;

b_tb <= ’1’;

wait for period;



severity error;

a_tb <= ’1’;

b_tb <= ’0’;

wait for period;



severity error;


ECE UNM 19 (8/20/09)


a_tb <= ’1’;

b_tb <= ’1’;

wait for period;



severity error;

wait; -- indifinitely suspend process

end process;

end;

Process tb simply applies, over time, 4 combinationss of values to the signals con-

nected to the UUT’s two inputs.

After application, the process waits 20 ns before checking the outputs using an assert

stmt -- if assert fails, the report stmt executes to display a message.

The 20 ns allows for combinational logic delays.

VHDL/PLD Design Methodology Electronic design...

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